From: "Mario Limonciello (AMD)" <superm1@kernel.org>
To: mario.limonciello@amd.com, Basavaraj.Natikar@amd.com,
Shyam-sundar.S-k@amd.com, linus.walleij@linaro.org
Cc: "Mario Limonciello (AMD)" <superm1@kernel.org>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
linux-gpio@vger.kernel.org
Subject: [PATCH v2] pinctrl: amd: Don't access irq_data's hwirq member directly
Date: Thu, 21 Aug 2025 09:49:11 -0500 [thread overview]
Message-ID: <20250821144942.2463014-1-superm1@kernel.org> (raw)
There is an irqd_to_hwirq() intended to get the hwirq number. Switch
all use to it.
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
---
v2:
* Declare a variable on stack in all functions using irqd_to_hwirq()
---
drivers/pinctrl/pinctrl-amd.c | 40 ++++++++++++++++++++---------------
1 file changed, 23 insertions(+), 17 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 127eeb0104d85..2dac5c71eb008 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -383,14 +383,15 @@ static void amd_gpio_irq_enable(struct irq_data *d)
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
- gpiochip_enable_irq(gc, d->hwirq);
+ gpiochip_enable_irq(gc, hwirq);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
- pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+ pin_reg = readl(gpio_dev->base + hwirq * 4);
pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
pin_reg |= BIT(INTERRUPT_MASK_OFF);
- writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+ writel(pin_reg, gpio_dev->base + hwirq * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
@@ -400,15 +401,16 @@ static void amd_gpio_irq_disable(struct irq_data *d)
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
- pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+ pin_reg = readl(gpio_dev->base + hwirq * 4);
pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
- writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+ writel(pin_reg, gpio_dev->base + hwirq * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
- gpiochip_disable_irq(gc, d->hwirq);
+ gpiochip_disable_irq(gc, hwirq);
}
static void amd_gpio_irq_mask(struct irq_data *d)
@@ -417,11 +419,12 @@ static void amd_gpio_irq_mask(struct irq_data *d)
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
- pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+ pin_reg = readl(gpio_dev->base + hwirq * 4);
pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
- writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+ writel(pin_reg, gpio_dev->base + hwirq * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
@@ -431,11 +434,12 @@ static void amd_gpio_irq_unmask(struct irq_data *d)
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
- pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+ pin_reg = readl(gpio_dev->base + hwirq * 4);
pin_reg |= BIT(INTERRUPT_MASK_OFF);
- writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+ writel(pin_reg, gpio_dev->base + hwirq * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
@@ -446,20 +450,21 @@ static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
int err;
pm_pr_dbg("Setting wake for GPIO %lu to %s\n",
- d->hwirq, str_enable_disable(on));
+ hwirq, str_enable_disable(on));
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
- pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+ pin_reg = readl(gpio_dev->base + hwirq * 4);
if (on)
pin_reg |= wake_mask;
else
pin_reg &= ~wake_mask;
- writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+ writel(pin_reg, gpio_dev->base + hwirq * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
if (on)
@@ -495,9 +500,10 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
- pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+ pin_reg = readl(gpio_dev->base + hwirq * 4);
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
@@ -563,10 +569,10 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg_irq_en = pin_reg;
pin_reg_irq_en |= mask;
pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
- writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
- while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
+ writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4);
+ while ((readl(gpio_dev->base + hwirq * 4) & mask) != mask)
continue;
- writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+ writel(pin_reg, gpio_dev->base + hwirq * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret;
--
2.43.0
next reply other threads:[~2025-08-21 14:49 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-21 14:49 Mario Limonciello (AMD) [this message]
2025-08-21 15:42 ` [PATCH v2] pinctrl: amd: Don't access irq_data's hwirq member directly Andy Shevchenko
2025-08-21 15:46 ` Mario Limonciello
2025-08-21 22:16 ` Linus Walleij
2025-08-22 0:30 ` Mario Limonciello
2025-08-22 6:33 ` Linus Walleij
2025-08-22 7:53 ` Andy Shevchenko
2025-08-22 13:12 ` Mario Limonciello
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250821144942.2463014-1-superm1@kernel.org \
--to=superm1@kernel.org \
--cc=Basavaraj.Natikar@amd.com \
--cc=Shyam-sundar.S-k@amd.com \
--cc=andriy.shevchenko@linux.intel.com \
--cc=linus.walleij@linaro.org \
--cc=linux-gpio@vger.kernel.org \
--cc=mario.limonciello@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.