Re: [PATCH v5 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC

Re: [PATCH v5 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC

[kernel test robot]

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250822-drm-misc-next-v5-7-9c825e28f733@foss.st.com>
References: <20250822-drm-misc-next-v5-7-9c825e28f733@foss.st.com>
TO: "Raphael Gallais-Pou" <raphael.gallais-pou@foss.st.com>
TO: Yannick Fertre <yannick.fertre@foss.st.com>
TO: Philippe Cornu <philippe.cornu@foss.st.com>
TO: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
TO: Maxime Ripard <mripard@kernel.org>
TO: Thomas Zimmermann <tzimmermann@suse.de>
TO: David Airlie <airlied@gmail.com>
TO: Simona Vetter <simona@ffwll.ch>
TO: Rob Herring <robh@kernel.org>
TO: Krzysztof Kozlowski <krzk@kernel.org>
TO: Conor Dooley <conor+dt@kernel.org>
TO: Maxime Coquelin <mcoquelin.stm32@gmail.com>
TO: Alexandre Torgue <alexandre.torgue@foss.st.com>
TO: Catalin Marinas <catalin.marinas@arm.com>
TO: Will Deacon <will@kernel.org>
TO: Christophe Roullier <christophe.roullier@foss.st.com>
CC: dri-devel@lists.freedesktop.org
CC: devicetree@vger.kernel.org
CC: linux-stm32@st-md-mailman.stormreply.com
CC: linux-arm-kernel@lists.infradead.org
CC: linux-kernel@vger.kernel.org

Hi Raphael,

kernel test robot noticed the following build warnings:

[auto build test WARNING on c8cea4371e5eca30cda8660aabb337747dabc51d]

url:    https://github.com/intel-lab-lkp/linux/commits/Raphael-Gallais-Pou/dt-bindings-display-st-add-two-new-compatibles-to-LTDC-device/20250822-224549
base:   c8cea4371e5eca30cda8660aabb337747dabc51d
patch link:    https://lore.kernel.org/r/20250822-drm-misc-next-v5-7-9c825e28f733%40foss.st.com
patch subject: [PATCH v5 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC
:::::: branch date: 2 days ago
:::::: commit date: 2 days ago
config: arm-randconfig-r072-20250824 (https://download.01.org/0day-ci/archive/20250825/202508250323.E10FG5CI-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 8.5.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202508250323.E10FG5CI-lkp@intel.com/

New smatch warnings:
drivers/gpu/drm/stm/ltdc.c:1902 ltdc_resume() warn: 'ldev->pixel_clk' from clk_prepare_enable() not released on lines: 1902.
drivers/gpu/drm/stm/ltdc.c:2077 ltdc_load() warn: 'ldev->bus_clk' from clk_prepare_enable() not released on lines: 2077.
drivers/gpu/drm/stm/ltdc.c:2077 ltdc_load() warn: 'ldev->pixel_clk' from clk_prepare_enable() not released on lines: 1947.

Old smatch warnings:
drivers/gpu/drm/stm/ltdc.c:938 ltdc_crtc_mode_set_nofb() warn: pm_runtime_get_sync() also returns 1 on success

vim +1902 drivers/gpu/drm/stm/ltdc.c

df61c776657fa5 Yannick Fertré  2019-03-21  1882  
df61c776657fa5 Yannick Fertré  2019-03-21  1883  int ltdc_resume(struct drm_device *ddev)
df61c776657fa5 Yannick Fertré  2019-03-21  1884  {
df61c776657fa5 Yannick Fertré  2019-03-21  1885  	struct ltdc_device *ldev = ddev->dev_private;
df61c776657fa5 Yannick Fertré  2019-03-21  1886  	int ret;
df61c776657fa5 Yannick Fertré  2019-03-21  1887  
df61c776657fa5 Yannick Fertré  2019-03-21  1888  	DRM_DEBUG_DRIVER("\n");
df61c776657fa5 Yannick Fertré  2019-03-21  1889  
df61c776657fa5 Yannick Fertré  2019-03-21  1890  	ret = clk_prepare_enable(ldev->pixel_clk);
df61c776657fa5 Yannick Fertré  2019-03-21  1891  	if (ret) {
df61c776657fa5 Yannick Fertré  2019-03-21  1892  		DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
df61c776657fa5 Yannick Fertré  2019-03-21  1893  		return ret;
df61c776657fa5 Yannick Fertré  2019-03-21  1894  	}
df61c776657fa5 Yannick Fertré  2019-03-21  1895  
4bc19104512f12 Yannick Fertre  2025-08-22  1896  	if (ldev->bus_clk) {
4bc19104512f12 Yannick Fertre  2025-08-22  1897  		ret = clk_prepare_enable(ldev->bus_clk);
4bc19104512f12 Yannick Fertre  2025-08-22  1898  		if (ret)
4bc19104512f12 Yannick Fertre  2025-08-22  1899  			drm_err(ddev, "failed to enable bus clock (%d)\n", ret);
4bc19104512f12 Yannick Fertre  2025-08-22  1900  	}
4bc19104512f12 Yannick Fertre  2025-08-22  1901  
4bc19104512f12 Yannick Fertre  2025-08-22 @1902  	return ret;
df61c776657fa5 Yannick Fertré  2019-03-21  1903  }
df61c776657fa5 Yannick Fertré  2019-03-21  1904  
b759012c5fa761 Yannick Fertre  2017-04-14  1905  int ltdc_load(struct drm_device *ddev)
b759012c5fa761 Yannick Fertre  2017-04-14  1906  {
b759012c5fa761 Yannick Fertre  2017-04-14  1907  	struct platform_device *pdev = to_platform_device(ddev->dev);
b759012c5fa761 Yannick Fertre  2017-04-14  1908  	struct ltdc_device *ldev = ddev->dev_private;
b759012c5fa761 Yannick Fertre  2017-04-14  1909  	struct device *dev = ddev->dev;
b759012c5fa761 Yannick Fertre  2017-04-14  1910  	struct device_node *np = dev->of_node;
b430ff7ef8b016 Yannick Fertre  2020-02-28  1911  	struct drm_bridge *bridge;
b430ff7ef8b016 Yannick Fertre  2020-02-28  1912  	struct drm_panel *panel;
b759012c5fa761 Yannick Fertre  2017-04-14  1913  	struct drm_crtc *crtc;
b759012c5fa761 Yannick Fertre  2017-04-14  1914  	struct reset_control *rstc;
b430ff7ef8b016 Yannick Fertre  2020-02-28  1915  	int irq, i, nb_endpoints;
b430ff7ef8b016 Yannick Fertre  2020-02-28  1916  	int ret = -ENODEV;
b759012c5fa761 Yannick Fertre  2017-04-14  1917  
b759012c5fa761 Yannick Fertre  2017-04-14  1918  	DRM_DEBUG_DRIVER("\n");
b759012c5fa761 Yannick Fertre  2017-04-14  1919  
b430ff7ef8b016 Yannick Fertre  2020-02-28  1920  	/* Get number of endpoints */
b430ff7ef8b016 Yannick Fertre  2020-02-28  1921  	nb_endpoints = of_graph_get_endpoint_count(np);
b430ff7ef8b016 Yannick Fertre  2020-02-28  1922  	if (!nb_endpoints)
b430ff7ef8b016 Yannick Fertre  2020-02-28  1923  		return -ENODEV;
b759012c5fa761 Yannick Fertre  2017-04-14  1924  
b759012c5fa761 Yannick Fertre  2017-04-14  1925  	ldev->pixel_clk = devm_clk_get(dev, "lcd");
b759012c5fa761 Yannick Fertre  2017-04-14  1926  	if (IS_ERR(ldev->pixel_clk)) {
1f358bc6f272b9 Fabien Dessenne 2019-04-24  1927  		if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER)
b759012c5fa761 Yannick Fertre  2017-04-14  1928  			DRM_ERROR("Unable to get lcd clock\n");
1f358bc6f272b9 Fabien Dessenne 2019-04-24  1929  		return PTR_ERR(ldev->pixel_clk);
b759012c5fa761 Yannick Fertre  2017-04-14  1930  	}
b759012c5fa761 Yannick Fertre  2017-04-14  1931  
b759012c5fa761 Yannick Fertre  2017-04-14  1932  	if (clk_prepare_enable(ldev->pixel_clk)) {
b759012c5fa761 Yannick Fertre  2017-04-14  1933  		DRM_ERROR("Unable to prepare pixel clock\n");
b759012c5fa761 Yannick Fertre  2017-04-14  1934  		return -ENODEV;
b759012c5fa761 Yannick Fertre  2017-04-14  1935  	}
b759012c5fa761 Yannick Fertre  2017-04-14  1936  
4bc19104512f12 Yannick Fertre  2025-08-22  1937  	if (of_device_is_compatible(np, "st,stm32mp251-ltdc") ||
4bc19104512f12 Yannick Fertre  2025-08-22  1938  	    of_device_is_compatible(np, "st,stm32mp255-ltdc")) {
4bc19104512f12 Yannick Fertre  2025-08-22  1939  		ldev->bus_clk = devm_clk_get(dev, "bus");
4bc19104512f12 Yannick Fertre  2025-08-22  1940  		if (IS_ERR(ldev->bus_clk))
4bc19104512f12 Yannick Fertre  2025-08-22  1941  			return dev_err_probe(dev, PTR_ERR(ldev->bus_clk),
4bc19104512f12 Yannick Fertre  2025-08-22  1942  					     "Unable to get bus clock\n");
4bc19104512f12 Yannick Fertre  2025-08-22  1943  
4bc19104512f12 Yannick Fertre  2025-08-22  1944  		ret = clk_prepare_enable(ldev->bus_clk);
4bc19104512f12 Yannick Fertre  2025-08-22  1945  		if (ret) {
4bc19104512f12 Yannick Fertre  2025-08-22  1946  			drm_err(ddev, "Unable to prepare bus clock\n");
4bc19104512f12 Yannick Fertre  2025-08-22  1947  			return ret;
4bc19104512f12 Yannick Fertre  2025-08-22  1948  		}
4bc19104512f12 Yannick Fertre  2025-08-22  1949  	}
4bc19104512f12 Yannick Fertre  2025-08-22  1950  
b430ff7ef8b016 Yannick Fertre  2020-02-28  1951  	/* Get endpoints if any */
b430ff7ef8b016 Yannick Fertre  2020-02-28  1952  	for (i = 0; i < nb_endpoints; i++) {
b430ff7ef8b016 Yannick Fertre  2020-02-28  1953  		ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge);
b430ff7ef8b016 Yannick Fertre  2020-02-28  1954  
b430ff7ef8b016 Yannick Fertre  2020-02-28  1955  		/*
b430ff7ef8b016 Yannick Fertre  2020-02-28  1956  		 * If at least one endpoint is -ENODEV, continue probing,
b430ff7ef8b016 Yannick Fertre  2020-02-28  1957  		 * else if at least one endpoint returned an error
b430ff7ef8b016 Yannick Fertre  2020-02-28  1958  		 * (ie -EPROBE_DEFER) then stop probing.
b430ff7ef8b016 Yannick Fertre  2020-02-28  1959  		 */
b430ff7ef8b016 Yannick Fertre  2020-02-28  1960  		if (ret == -ENODEV)
b430ff7ef8b016 Yannick Fertre  2020-02-28  1961  			continue;
b430ff7ef8b016 Yannick Fertre  2020-02-28  1962  		else if (ret)
b430ff7ef8b016 Yannick Fertre  2020-02-28  1963  			goto err;
b430ff7ef8b016 Yannick Fertre  2020-02-28  1964  
b430ff7ef8b016 Yannick Fertre  2020-02-28  1965  		if (panel) {
19dd9780b7ac67 Katya Orlova    2024-02-16  1966  			bridge = drmm_panel_bridge_add(ddev, panel);
b430ff7ef8b016 Yannick Fertre  2020-02-28  1967  			if (IS_ERR(bridge)) {
b430ff7ef8b016 Yannick Fertre  2020-02-28  1968  				DRM_ERROR("panel-bridge endpoint %d\n", i);
b430ff7ef8b016 Yannick Fertre  2020-02-28  1969  				ret = PTR_ERR(bridge);
b430ff7ef8b016 Yannick Fertre  2020-02-28  1970  				goto err;
b430ff7ef8b016 Yannick Fertre  2020-02-28  1971  			}
b430ff7ef8b016 Yannick Fertre  2020-02-28  1972  		}
b430ff7ef8b016 Yannick Fertre  2020-02-28  1973  
b430ff7ef8b016 Yannick Fertre  2020-02-28  1974  		if (bridge) {
b430ff7ef8b016 Yannick Fertre  2020-02-28  1975  			ret = ltdc_encoder_init(ddev, bridge);
b430ff7ef8b016 Yannick Fertre  2020-02-28  1976  			if (ret) {
648ce7fd186cfb Jagan Teki      2021-07-04  1977  				if (ret != -EPROBE_DEFER)
b430ff7ef8b016 Yannick Fertre  2020-02-28  1978  					DRM_ERROR("init encoder endpoint %d\n", i);
b430ff7ef8b016 Yannick Fertre  2020-02-28  1979  				goto err;
b430ff7ef8b016 Yannick Fertre  2020-02-28  1980  			}
b430ff7ef8b016 Yannick Fertre  2020-02-28  1981  		}
b430ff7ef8b016 Yannick Fertre  2020-02-28  1982  	}
b430ff7ef8b016 Yannick Fertre  2020-02-28  1983  
b430ff7ef8b016 Yannick Fertre  2020-02-28  1984  	rstc = devm_reset_control_get_exclusive(dev, NULL);
b430ff7ef8b016 Yannick Fertre  2020-02-28  1985  
b430ff7ef8b016 Yannick Fertre  2020-02-28  1986  	mutex_init(&ldev->err_lock);
b430ff7ef8b016 Yannick Fertre  2020-02-28  1987  
f42f540b9d0c16 Yannick Fertré  2019-04-03  1988  	if (!IS_ERR(rstc)) {
f42f540b9d0c16 Yannick Fertré  2019-04-03  1989  		reset_control_assert(rstc);
f42f540b9d0c16 Yannick Fertré  2019-04-03  1990  		usleep_range(10, 20);
f42f540b9d0c16 Yannick Fertré  2019-04-03  1991  		reset_control_deassert(rstc);
f42f540b9d0c16 Yannick Fertré  2019-04-03  1992  	}
f42f540b9d0c16 Yannick Fertré  2019-04-03  1993  
50cc9a322b5f4f Anusha Srivatsa 2025-02-25  1994  	ldev->regs = devm_platform_ioremap_resource(pdev, 0);
b759012c5fa761 Yannick Fertre  2017-04-14  1995  	if (IS_ERR(ldev->regs)) {
b759012c5fa761 Yannick Fertre  2017-04-14  1996  		DRM_ERROR("Unable to get ltdc registers\n");
cea3a330ee20e9 Philippe CORNU  2017-07-17  1997  		ret = PTR_ERR(ldev->regs);
cea3a330ee20e9 Philippe CORNU  2017-07-17  1998  		goto err;
b759012c5fa761 Yannick Fertre  2017-04-14  1999  	}
b759012c5fa761 Yannick Fertre  2017-04-14  2000  
734c26450aefaa Yannick Fertre  2021-12-15  2001  	ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg);
734c26450aefaa Yannick Fertre  2021-12-15  2002  	if (IS_ERR(ldev->regmap)) {
734c26450aefaa Yannick Fertre  2021-12-15  2003  		DRM_ERROR("Unable to regmap ltdc registers\n");
734c26450aefaa Yannick Fertre  2021-12-15  2004  		ret = PTR_ERR(ldev->regmap);
734c26450aefaa Yannick Fertre  2021-12-15  2005  		goto err;
734c26450aefaa Yannick Fertre  2021-12-15  2006  	}
734c26450aefaa Yannick Fertre  2021-12-15  2007  
544aa6cefb24d7 Yannick Fertre  2020-01-21  2008  	ret = ltdc_get_caps(ddev);
544aa6cefb24d7 Yannick Fertre  2020-01-21  2009  	if (ret) {
544aa6cefb24d7 Yannick Fertre  2020-01-21  2010  		DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
544aa6cefb24d7 Yannick Fertre  2020-01-21  2011  			  ldev->caps.hw_version);
9e759fc7dcd6d4 Fabien Dessenne 2019-04-24  2012  		goto err;
544aa6cefb24d7 Yannick Fertre  2020-01-21  2013  	}
9e759fc7dcd6d4 Fabien Dessenne 2019-04-24  2014  
ef824286128edd Yannick Fertre  2024-07-12  2015  	/* Disable all interrupts */
ef824286128edd Yannick Fertre  2024-07-12  2016  	regmap_clear_bits(ldev->regmap, LTDC_IER, IER_MASK);
7d008eecb0cfc2 Yannick Fertre  2022-06-03  2017  
544aa6cefb24d7 Yannick Fertre  2020-01-21  2018  	DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
544aa6cefb24d7 Yannick Fertre  2020-01-21  2019  
7d008eecb0cfc2 Yannick Fertre  2022-06-03  2020  	/* initialize default value for fifo underrun threshold & clear interrupt error counters */
7d008eecb0cfc2 Yannick Fertre  2022-06-03  2021  	ldev->transfer_err = 0;
7d008eecb0cfc2 Yannick Fertre  2022-06-03  2022  	ldev->fifo_err = 0;
7d008eecb0cfc2 Yannick Fertre  2022-06-03  2023  	ldev->fifo_warn = 0;
7d008eecb0cfc2 Yannick Fertre  2022-06-03  2024  	ldev->fifo_threshold = FUT_DFT;
7d008eecb0cfc2 Yannick Fertre  2022-06-03  2025  
544aa6cefb24d7 Yannick Fertre  2020-01-21  2026  	for (i = 0; i < ldev->caps.nb_irq; i++) {
544aa6cefb24d7 Yannick Fertre  2020-01-21  2027  		irq = platform_get_irq(pdev, i);
544aa6cefb24d7 Yannick Fertre  2020-01-21  2028  		if (irq < 0) {
544aa6cefb24d7 Yannick Fertre  2020-01-21  2029  			ret = irq;
544aa6cefb24d7 Yannick Fertre  2020-01-21  2030  			goto err;
544aa6cefb24d7 Yannick Fertre  2020-01-21  2031  		}
b759012c5fa761 Yannick Fertre  2017-04-14  2032  
b759012c5fa761 Yannick Fertre  2017-04-14  2033  		ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
b759012c5fa761 Yannick Fertre  2017-04-14  2034  						ltdc_irq_thread, IRQF_ONESHOT,
b759012c5fa761 Yannick Fertre  2017-04-14  2035  						dev_name(dev), ddev);
b759012c5fa761 Yannick Fertre  2017-04-14  2036  		if (ret) {
b759012c5fa761 Yannick Fertre  2017-04-14  2037  			DRM_ERROR("Failed to register LTDC interrupt\n");
cea3a330ee20e9 Philippe CORNU  2017-07-17  2038  			goto err;
b759012c5fa761 Yannick Fertre  2017-04-14  2039  		}
c188d7ebbebd0b Philippe CORNU  2017-10-26  2040  	}
b759012c5fa761 Yannick Fertre  2017-04-14  2041  
19dd9780b7ac67 Katya Orlova    2024-02-16  2042  	crtc = drmm_kzalloc(ddev, sizeof(*crtc), GFP_KERNEL);
b759012c5fa761 Yannick Fertre  2017-04-14  2043  	if (!crtc) {
b759012c5fa761 Yannick Fertre  2017-04-14  2044  		DRM_ERROR("Failed to allocate crtc\n");
b759012c5fa761 Yannick Fertre  2017-04-14  2045  		ret = -ENOMEM;
b759012c5fa761 Yannick Fertre  2017-04-14  2046  		goto err;
b759012c5fa761 Yannick Fertre  2017-04-14  2047  	}
b759012c5fa761 Yannick Fertre  2017-04-14  2048  
b759012c5fa761 Yannick Fertre  2017-04-14  2049  	ret = ltdc_crtc_init(ddev, crtc);
b759012c5fa761 Yannick Fertre  2017-04-14  2050  	if (ret) {
b759012c5fa761 Yannick Fertre  2017-04-14  2051  		DRM_ERROR("Failed to init crtc\n");
b759012c5fa761 Yannick Fertre  2017-04-14  2052  		goto err;
b759012c5fa761 Yannick Fertre  2017-04-14  2053  	}
b759012c5fa761 Yannick Fertre  2017-04-14  2054  
b759012c5fa761 Yannick Fertre  2017-04-14  2055  	ret = drm_vblank_init(ddev, NB_CRTC);
b759012c5fa761 Yannick Fertre  2017-04-14  2056  	if (ret) {
b759012c5fa761 Yannick Fertre  2017-04-14  2057  		DRM_ERROR("Failed calling drm_vblank_init()\n");
b759012c5fa761 Yannick Fertre  2017-04-14  2058  		goto err;
b759012c5fa761 Yannick Fertre  2017-04-14  2059  	}
b759012c5fa761 Yannick Fertre  2017-04-14  2060  
35ab6cfbf21178 Yannick Fertré  2019-06-03  2061  	clk_disable_unprepare(ldev->pixel_clk);
35ab6cfbf21178 Yannick Fertré  2019-06-03  2062  
4bc19104512f12 Yannick Fertre  2025-08-22  2063  	if (ldev->bus_clk)
4bc19104512f12 Yannick Fertre  2025-08-22  2064  		clk_disable_unprepare(ldev->bus_clk);
4bc19104512f12 Yannick Fertre  2025-08-22  2065  
92a57b3fb500e2 Yannick Fertré  2019-09-06  2066  	pinctrl_pm_select_sleep_state(ddev->dev);
92a57b3fb500e2 Yannick Fertré  2019-09-06  2067  
35ab6cfbf21178 Yannick Fertré  2019-06-03  2068  	pm_runtime_enable(ddev->dev);
bdf31bcf3d84ef Philippe CORNU  2017-07-17  2069  
35ab6cfbf21178 Yannick Fertré  2019-06-03  2070  	return 0;
b759012c5fa761 Yannick Fertre  2017-04-14  2071  err:
b759012c5fa761 Yannick Fertre  2017-04-14  2072  	clk_disable_unprepare(ldev->pixel_clk);
b759012c5fa761 Yannick Fertre  2017-04-14  2073  
4bc19104512f12 Yannick Fertre  2025-08-22  2074  	if (ldev->bus_clk)
4bc19104512f12 Yannick Fertre  2025-08-22  2075  		clk_disable_unprepare(ldev->bus_clk);
4bc19104512f12 Yannick Fertre  2025-08-22  2076  
b759012c5fa761 Yannick Fertre  2017-04-14 @2077  	return ret;
b759012c5fa761 Yannick Fertre  2017-04-14  2078  }
b759012c5fa761 Yannick Fertre  2017-04-14  2079  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH v5 00/13] Enable display support for STM32MP25

[Raphael Gallais-Pou]

This series aims to add and enable sufficient LVDS display support for
STM32MP257F-EV1 board.

LVDS is the default use case to drive a display panel on STM32MP257F-EV,
even though DSI panels will be supported in the near future.

The LTDC needs a pixel rate in sync with the bridge currently in use.
For that both DSI and LVDS bridges need to declare an internal clock and
become clock provider to the mux. The mux then selects the reference
clock for the LTDC pixel rate generation.

For now this mux is handled internally in the LTDC, while waiting for
the STM32 clock framework to merge a 'clk-mux' based on the SYSCFG.
This explains the link done in the patch [7/8] between the LVDS,
providing the reference clock for the LTDC internals.

  +----------+              |\
  |  DSI PHY |------------->| \           +------------+
  |          |ck_dsi_phy    |  |          |            |
  +----------+              |  |--------->|    LTDC    |
  +----------+              |  |pixel_clk |            |
  | LVDS PHY |------------->|  |          +------------+
  |          |clk_pix_lvds  |  |
  +----------+              |  |
                            |  |
   ck_ker_ltdc ------------>| /
                            |/|
                              └- SYSCFG

Clock selection applies as follow:
- 0b00: Selects ck_dsi_phy
- 0b01: Selects clk_pix_lvds
- 0b10: Selects ck_ker_ltdc (for parallel or DSI display).
- 0b11: Reserved

The reset value of the register controlling the mux is 0b01, meaning
that the default clock assigned is the clk_pix_lvds.  This causes two
things:

- In order to get basic display on the LVDS encoder, like intended,
nothing has to be done on this mux within the LTDC driver (which for now
explains the unused syscfg phandle on the LTDC node in the device-tree).

- 'pixel_clk' is dependent from 'clk_pix_lvds' because of the LTDC clock
domains.  They also need to be sync to get a coherent pixel rate though
the display clock tree (which explains the LVDS phandle on the LTDC node
in the device-tree).

Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
---
Changes in v5:
- Documentation:
  - LTDC: Clamp correctly min/maxItems value (again)
- Add Yannick's trailers where relevant except in patch [01/13] which
  has been modified
- Link to v4: https://lore.kernel.org/r/20250821-drm-misc-next-v4-0-7060500f8fd3@foss.st.com

Changes in v4:
- Documentation:
  - LTDC: Add "st,stm32mp255-ltdc" compatible.  After internal
    discussion, we came to the solution that the LTDC on STM32MP255 SoC
    needs its own compatible, since it does have the same amount of
    clocks than on STM32MP251 SoC.
- Devicetree:
  - Add "st,stm32mp255" compatible on corresponding dtsi
- Drivers:
  - LTDC: Handle "st,stm32mp255" compatible
- Remove Rob's r-b from patch [01/13] since it was modified.
- Link to v3: https://lore.kernel.org/r/20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com

Changes in v3:
- Rebased on latest drm-misc-next
- Documentation:
  - LTDC: Clamp correctly min/maxItems value
  - LVDS: Remove second 'items' keyword
- Add Krzysztof's trailer where relevant
- Link to v2: https://lore.kernel.org/r/20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com

Changes in v2:
- Documentation:
  - Add support for new compatible "st,stm32mp255-lvds"
  - Change LTDC compatible for SoC compliant one
  - Make clearer LTDC clock-names property
- Devicetree:
  - Change compatible according to the documentation
  - Change clock and clock-names order to match documentation (and avoid
    warnings)
- Drivers:
  - Change LTDC compatible
- Add Rob's trailer where relevant
- Link to v1: https://lore.kernel.org/r/20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com

---
Raphael Gallais-Pou (11):
      dt-bindings: display: st: add two new compatibles to LTDC device
      dt-bindings: display: st,stm32-ltdc: add access-controllers property
      dt-bindings: display: st: add new compatible to LVDS device
      dt-bindings: display: st,stm32mp25-lvds: add access-controllers property
      dt-bindings: display: st,stm32mp25-lvds: add power-domains property
      dt-bindings: arm: stm32: add required #clock-cells property
      arm64: dts: st: add ltdc support on stm32mp251
      arm64: dts: st: add ltdc support on stm32mp255
      arm64: dts: st: add lvds support on stm32mp255
      arm64: dts: st: add clock-cells to syscfg node on stm32mp251
      arm64: dts: st: enable display support on stm32mp257f-ev1 board

Yannick Fertre (2):
      drm/stm: ltdc: support new hardware version for STM32MP25 SoC
      drm/stm: ltdc: handle lvds pixel clock

 .../bindings/arm/stm32/st,stm32-syscon.yaml        | 31 ++++++---
 .../devicetree/bindings/display/st,stm32-ltdc.yaml | 55 ++++++++++++++-
 .../bindings/display/st,stm32mp25-lvds.yaml        | 13 +++-
 arch/arm64/boot/dts/st/stm32mp251.dtsi             | 19 ++++++
 arch/arm64/boot/dts/st/stm32mp255.dtsi             | 20 +++++-
 arch/arm64/boot/dts/st/stm32mp257f-ev1.dts         | 79 ++++++++++++++++++++++
 drivers/gpu/drm/stm/drv.c                          | 12 +++-
 drivers/gpu/drm/stm/ltdc.c                         | 58 +++++++++++++++-
 drivers/gpu/drm/stm/ltdc.h                         |  6 ++
 9 files changed, 275 insertions(+), 18 deletions(-)
---
base-commit: c8cea4371e5eca30cda8660aabb337747dabc51d
change-id: 20250617-drm-misc-next-4af406c1c45f

Best regards,
-- 
Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>

[PATCH v5 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC

[Raphael Gallais-Pou]

From: Yannick Fertre <yannick.fertre@foss.st.com>

STM32MP25 SoC features a new version of the LTDC IP.  Add its compatible
to the list of device to probe and implement its quirks.

This hardware supports a pad frequency of 150MHz and a peripheral bus
clock.

Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
---
 drivers/gpu/drm/stm/drv.c  | 12 +++++++++++-
 drivers/gpu/drm/stm/ltdc.c | 38 +++++++++++++++++++++++++++++++++++---
 drivers/gpu/drm/stm/ltdc.h |  5 +++++
 3 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
index 8ebcaf953782d806a738d5a41ff1f428b0ccff78..ab00d1a6140cc32e71e10abc82f7956328b518e3 100644
--- a/drivers/gpu/drm/stm/drv.c
+++ b/drivers/gpu/drm/stm/drv.c
@@ -236,8 +236,18 @@ static void stm_drm_platform_shutdown(struct platform_device *pdev)
 	drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
 }
 
+static struct ltdc_plat_data stm_drm_plat_data = {
+	.pad_max_freq_hz = 90000000,
+};
+
+static struct ltdc_plat_data stm_drm_plat_data_mp25 = {
+	.pad_max_freq_hz = 150000000,
+};
+
 static const struct of_device_id drv_dt_ids[] = {
-	{ .compatible = "st,stm32-ltdc"},
+	{ .compatible = "st,stm32-ltdc", .data = &stm_drm_plat_data, },
+	{ .compatible = "st,stm32mp251-ltdc", .data = &stm_drm_plat_data_mp25, },
+	{ .compatible = "st,stm32mp255-ltdc", .data = &stm_drm_plat_data_mp25, },
 	{ /* end node */ },
 };
 MODULE_DEVICE_TABLE(of, drv_dt_ids);
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index ba315c66a04d72758b9d3cfcd842432877f66d3a..17548dd3484a0a3e1015c58c752b80f8892a0ff7 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -14,6 +14,7 @@
 #include <linux/interrupt.h>
 #include <linux/media-bus-format.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/of_graph.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/platform_device.h>
@@ -51,6 +52,7 @@
 #define HWVER_10300 0x010300
 #define HWVER_20101 0x020101
 #define HWVER_40100 0x040100
+#define HWVER_40101 0x040101
 
 /*
  * The address of some registers depends on the HW version: such registers have
@@ -1779,6 +1781,7 @@ static int ltdc_get_caps(struct drm_device *ddev)
 {
 	struct ltdc_device *ldev = ddev->dev_private;
 	u32 bus_width_log2, lcr, gc2r;
+	const struct ltdc_plat_data *pdata = of_device_get_match_data(ddev->dev);
 
 	/*
 	 * at least 1 layer must be managed & the number of layers
@@ -1794,6 +1797,8 @@ static int ltdc_get_caps(struct drm_device *ddev)
 	ldev->caps.bus_width = 8 << bus_width_log2;
 	regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version);
 
+	ldev->caps.pad_max_freq_hz = pdata->pad_max_freq_hz;
+
 	switch (ldev->caps.hw_version) {
 	case HWVER_10200:
 	case HWVER_10300:
@@ -1811,7 +1816,6 @@ static int ltdc_get_caps(struct drm_device *ddev)
 		 * does not work on 2nd layer.
 		 */
 		ldev->caps.non_alpha_only_l1 = true;
-		ldev->caps.pad_max_freq_hz = 90000000;
 		if (ldev->caps.hw_version == HWVER_10200)
 			ldev->caps.pad_max_freq_hz = 65000000;
 		ldev->caps.nb_irq = 2;
@@ -1842,6 +1846,7 @@ static int ltdc_get_caps(struct drm_device *ddev)
 		ldev->caps.fifo_threshold = false;
 		break;
 	case HWVER_40100:
+	case HWVER_40101:
 		ldev->caps.layer_ofs = LAY_OFS_1;
 		ldev->caps.layer_regs = ltdc_layer_regs_a2;
 		ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2;
@@ -1849,7 +1854,6 @@ static int ltdc_get_caps(struct drm_device *ddev)
 		ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2);
 		ldev->caps.pix_fmt_flex = true;
 		ldev->caps.non_alpha_only_l1 = false;
-		ldev->caps.pad_max_freq_hz = 90000000;
 		ldev->caps.nb_irq = 2;
 		ldev->caps.ycbcr_input = true;
 		ldev->caps.ycbcr_output = true;
@@ -1872,6 +1876,8 @@ void ltdc_suspend(struct drm_device *ddev)
 
 	DRM_DEBUG_DRIVER("\n");
 	clk_disable_unprepare(ldev->pixel_clk);
+	if (ldev->bus_clk)
+		clk_disable_unprepare(ldev->bus_clk);
 }
 
 int ltdc_resume(struct drm_device *ddev)
@@ -1887,7 +1893,13 @@ int ltdc_resume(struct drm_device *ddev)
 		return ret;
 	}
 
-	return 0;
+	if (ldev->bus_clk) {
+		ret = clk_prepare_enable(ldev->bus_clk);
+		if (ret)
+			drm_err(ddev, "failed to enable bus clock (%d)\n", ret);
+	}
+
+	return ret;
 }
 
 int ltdc_load(struct drm_device *ddev)
@@ -1922,6 +1934,20 @@ int ltdc_load(struct drm_device *ddev)
 		return -ENODEV;
 	}
 
+	if (of_device_is_compatible(np, "st,stm32mp251-ltdc") ||
+	    of_device_is_compatible(np, "st,stm32mp255-ltdc")) {
+		ldev->bus_clk = devm_clk_get(dev, "bus");
+		if (IS_ERR(ldev->bus_clk))
+			return dev_err_probe(dev, PTR_ERR(ldev->bus_clk),
+					     "Unable to get bus clock\n");
+
+		ret = clk_prepare_enable(ldev->bus_clk);
+		if (ret) {
+			drm_err(ddev, "Unable to prepare bus clock\n");
+			return ret;
+		}
+	}
+
 	/* Get endpoints if any */
 	for (i = 0; i < nb_endpoints; i++) {
 		ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge);
@@ -2034,6 +2060,9 @@ int ltdc_load(struct drm_device *ddev)
 
 	clk_disable_unprepare(ldev->pixel_clk);
 
+	if (ldev->bus_clk)
+		clk_disable_unprepare(ldev->bus_clk);
+
 	pinctrl_pm_select_sleep_state(ddev->dev);
 
 	pm_runtime_enable(ddev->dev);
@@ -2042,6 +2071,9 @@ int ltdc_load(struct drm_device *ddev)
 err:
 	clk_disable_unprepare(ldev->pixel_clk);
 
+	if (ldev->bus_clk)
+		clk_disable_unprepare(ldev->bus_clk);
+
 	return ret;
 }
 
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index 9d488043ffdbc652deeede71c9d57d45fb89d3c6..ddfa8ae61a7ba5dc446fae647562d0ec8e6953e1 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -40,10 +40,15 @@ struct fps_info {
 	ktime_t last_timestamp;
 };
 
+struct ltdc_plat_data {
+	int pad_max_freq_hz;	/* max frequency supported by pad */
+};
+
 struct ltdc_device {
 	void __iomem *regs;
 	struct regmap *regmap;
 	struct clk *pixel_clk;	/* lcd pixel clock */
+	struct clk *bus_clk;	/* bus clock */
 	struct mutex err_lock;	/* protecting error_status */
 	struct ltdc_caps caps;
 	u32 irq_status;

-- 
2.25.1

Re: [PATCH v5 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC

[Philippe CORNU]

On 8/22/25 16:34, Raphael Gallais-Pou wrote:
> From: Yannick Fertre <yannick.fertre@foss.st.com>
> 
> STM32MP25 SoC features a new version of the LTDC IP.  Add its compatible
> to the list of device to probe and implement its quirks.
> 
> This hardware supports a pad frequency of 150MHz and a peripheral bus
> clock.
> 
> Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
> Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
> ---
>   drivers/gpu/drm/stm/drv.c  | 12 +++++++++++-
>   drivers/gpu/drm/stm/ltdc.c | 38 +++++++++++++++++++++++++++++++++++---
>   drivers/gpu/drm/stm/ltdc.h |  5 +++++
>   3 files changed, 51 insertions(+), 4 deletions(-)

Hi Raphael,

Acked-by: Philippe Cornu <philippe.cornu@foss.st.com>

Thank you
Philippe :-)