From: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Cc: git@amd.com, michal.simek@amd.com, Frank.Li@nxp.com,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
kees@kernel.org, gustavoars@kernel.org,
jarkko.nikula@linux.intel.com, linux-i3c@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-hardening@vger.kernel.org, radhey.shyam.pandey@amd.com,
srinivas.goud@amd.com, shubhrajyoti.datta@amd.com,
manion05gk@gmail.com
Subject: Re: [PATCH V2 2/2] i3c: master: Add AMD I3C bus controller driver
Date: Mon, 1 Sep 2025 22:12:48 +0200 [thread overview]
Message-ID: <202509012012480348cc7a@mail.local> (raw)
In-Reply-To: <20250829171327.2590730-3-manikanta.guntupalli@amd.com>
On 29/08/2025 22:43:27+0530, Manikanta Guntupalli wrote:
> +static void xi3c_master_reset_fifos(struct xi3c_master *master)
> +{
> + u32 data;
> +
> + /* Reset fifos */
> + data = readl(master->membase + XI3C_RESET_OFFSET);
> + data |= XI3C_FIFOS_RST_MASK;
> + writel(data, master->membase + XI3C_RESET_OFFSET);
> + udelay(10);
As pointed out by checkpatch:
usleep_range is preferred over udelay, I guess it would be fine in this
function.
> + data &= ~XI3C_FIFOS_RST_MASK;
> + writel(data, master->membase + XI3C_RESET_OFFSET);
> + udelay(10);
> +}
> +
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Cc: git@amd.com, michal.simek@amd.com, Frank.Li@nxp.com,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
kees@kernel.org, gustavoars@kernel.org,
jarkko.nikula@linux.intel.com, linux-i3c@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-hardening@vger.kernel.org, radhey.shyam.pandey@amd.com,
srinivas.goud@amd.com, shubhrajyoti.datta@amd.com,
manion05gk@gmail.com
Subject: Re: [PATCH V2 2/2] i3c: master: Add AMD I3C bus controller driver
Date: Mon, 1 Sep 2025 22:12:48 +0200 [thread overview]
Message-ID: <202509012012480348cc7a@mail.local> (raw)
In-Reply-To: <20250829171327.2590730-3-manikanta.guntupalli@amd.com>
On 29/08/2025 22:43:27+0530, Manikanta Guntupalli wrote:
> +static void xi3c_master_reset_fifos(struct xi3c_master *master)
> +{
> + u32 data;
> +
> + /* Reset fifos */
> + data = readl(master->membase + XI3C_RESET_OFFSET);
> + data |= XI3C_FIFOS_RST_MASK;
> + writel(data, master->membase + XI3C_RESET_OFFSET);
> + udelay(10);
As pointed out by checkpatch:
usleep_range is preferred over udelay, I guess it would be fine in this
function.
> + data &= ~XI3C_FIFOS_RST_MASK;
> + writel(data, master->membase + XI3C_RESET_OFFSET);
> + udelay(10);
> +}
> +
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
--
linux-i3c mailing list
linux-i3c@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-i3c
next prev parent reply other threads:[~2025-09-01 20:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-29 17:13 [PATCH V2 0/2] Add AMD I3C master controller driver and bindings Manikanta Guntupalli
2025-08-29 17:13 ` Manikanta Guntupalli
2025-08-29 17:13 ` [PATCH V2 1/2] dt-bindings: i3c: Add AMD I3C master controller support Manikanta Guntupalli
2025-08-29 17:13 ` Manikanta Guntupalli
2025-09-01 5:21 ` Krzysztof Kozlowski
2025-09-01 5:21 ` Krzysztof Kozlowski
2025-09-01 5:22 ` Krzysztof Kozlowski
2025-09-01 5:22 ` Krzysztof Kozlowski
2025-08-29 17:13 ` [PATCH V2 2/2] i3c: master: Add AMD I3C bus controller driver Manikanta Guntupalli
2025-08-29 17:13 ` Manikanta Guntupalli
2025-09-01 20:12 ` Alexandre Belloni [this message]
2025-09-01 20:12 ` Alexandre Belloni
2025-09-02 7:10 ` Guntupalli, Manikanta
2025-09-02 7:10 ` Guntupalli, Manikanta
2025-09-03 14:27 ` Frank Li
2025-09-03 14:27 ` Frank Li
2025-09-04 10:09 ` Guntupalli, Manikanta
2025-09-04 10:09 ` Guntupalli, Manikanta
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