* [PATCH v5 1/7] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports
2025-09-01 12:05 [PATCH v5 0/7] Add support of IRQs to QUICC ENGINE GPIOs Christophe Leroy
@ 2025-09-01 12:05 ` Christophe Leroy
2025-09-01 12:05 ` [PATCH v5 2/7] soc: fsl: qe: Change GPIO driver to a proper platform driver Christophe Leroy
` (5 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Christophe Leroy @ 2025-09-01 12:05 UTC (permalink / raw)
To: Qiang Zhao, Linus Walleij, Bartosz Golaszewski, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Christophe Leroy, linux-kernel, linuxppc-dev, linux-arm-kernel,
linux-gpio, devicetree
The QUICC Engine provides interrupts for a few I/O ports. This is
handled via a separate interrupt ID and managed via a triplet of
dedicated registers hosted by the SoC.
Implement an interrupt driver for it for that those IRQs can then
be linked to the related GPIOs.
The number of ports for which interrupts are supported depends on
the microcontroller:
- mpc8323 has 10 interrupts
- mpc8360 has 28 interrupts
- mpc8568 has 18 interrupts
So add this information as data of the compatible.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
drivers/soc/fsl/qe/Makefile | 2 +-
drivers/soc/fsl/qe/qe_ports_ic.c | 156 +++++++++++++++++++++++++++++++
2 files changed, 157 insertions(+), 1 deletion(-)
create mode 100644 drivers/soc/fsl/qe/qe_ports_ic.c
diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
index ec8506e13113..901a9c40d5eb 100644
--- a/drivers/soc/fsl/qe/Makefile
+++ b/drivers/soc/fsl/qe/Makefile
@@ -11,4 +11,4 @@ obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
obj-$(CONFIG_UCC_FAST) += ucc_fast.o
obj-$(CONFIG_QE_TDM) += qe_tdm.o
obj-$(CONFIG_QE_USB) += usb.o
-obj-$(CONFIG_QE_GPIO) += gpio.o
+obj-$(CONFIG_QE_GPIO) += gpio.o qe_ports_ic.o
diff --git a/drivers/soc/fsl/qe/qe_ports_ic.c b/drivers/soc/fsl/qe/qe_ports_ic.c
new file mode 100644
index 000000000000..9715643d36a6
--- /dev/null
+++ b/drivers/soc/fsl/qe/qe_ports_ic.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * QUICC ENGINE I/O Ports Interrupt Controller
+ *
+ * Copyright (c) 2025 Christophe Leroy CS GROUP France (christophe.leroy@csgroup.eu)
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/platform_device.h>
+
+/* QE IC registers offset */
+#define CEPIER 0x0c
+#define CEPIMR 0x10
+#define CEPICR 0x14
+
+struct qepic_data {
+ void __iomem *reg;
+ struct irq_domain *host;
+};
+
+static void qepic_mask(struct irq_data *d)
+{
+ struct qepic_data *data = irq_data_get_irq_chip_data(d);
+
+ clrbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d)));
+}
+
+static void qepic_unmask(struct irq_data *d)
+{
+ struct qepic_data *data = irq_data_get_irq_chip_data(d);
+
+ setbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d)));
+}
+
+static void qepic_end(struct irq_data *d)
+{
+ struct qepic_data *data = irq_data_get_irq_chip_data(d);
+
+ out_be32(data->reg + CEPIER, 1 << (31 - irqd_to_hwirq(d)));
+}
+
+static int qepic_set_type(struct irq_data *d, unsigned int flow_type)
+{
+ struct qepic_data *data = irq_data_get_irq_chip_data(d);
+ unsigned int vec = (unsigned int)irqd_to_hwirq(d);
+
+ switch (flow_type & IRQ_TYPE_SENSE_MASK) {
+ case IRQ_TYPE_EDGE_FALLING:
+ setbits32(data->reg + CEPICR, 1 << (31 - vec));
+ return 0;
+ case IRQ_TYPE_EDGE_BOTH:
+ case IRQ_TYPE_NONE:
+ clrbits32(data->reg + CEPICR, 1 << (31 - vec));
+ return 0;
+ }
+ return -EINVAL;
+}
+
+static struct irq_chip qepic = {
+ .name = "QEPIC",
+ .irq_mask = qepic_mask,
+ .irq_unmask = qepic_unmask,
+ .irq_eoi = qepic_end,
+ .irq_set_type = qepic_set_type,
+};
+
+static int qepic_get_irq(struct irq_desc *desc)
+{
+ struct qepic_data *data = irq_desc_get_handler_data(desc);
+ u32 event = in_be32(data->reg + CEPIER);
+
+ if (!event)
+ return -1;
+
+ return irq_find_mapping(data->host, 32 - ffs(event));
+}
+
+static void qepic_cascade(struct irq_desc *desc)
+{
+ generic_handle_irq(qepic_get_irq(desc));
+}
+
+static int qepic_host_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw)
+{
+ irq_set_chip_data(virq, h->host_data);
+ irq_set_chip_and_handler(virq, &qepic, handle_fasteoi_irq);
+ return 0;
+}
+
+static const struct irq_domain_ops qepic_host_ops = {
+ .map = qepic_host_map,
+};
+
+static int qepic_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct qepic_data *data;
+ unsigned long nb;
+ int irq;
+
+ nb = (unsigned long)of_device_get_match_data(dev);
+ if (nb < 1 || nb > 32)
+ return -EINVAL;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(data->reg))
+ return PTR_ERR(data->reg);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ data->host = irq_domain_add_linear(dev->of_node, nb, &qepic_host_ops, data);
+ if (!data->host)
+ return -ENODEV;
+
+ irq_set_handler_data(irq, data);
+ irq_set_chained_handler(irq, qepic_cascade);
+
+ return 0;
+}
+
+static const struct of_device_id qepic_match[] = {
+ {
+ .compatible = "fsl,mpc8323-qe-ports-ic",
+ .data = (void *)10,
+ },
+ {
+ .compatible = "fsl,mpc8360-qe-ports-ic",
+ .data = (void *)28,
+ },
+ {
+ .compatible = "fsl,mpc8568-qe-ports-ic",
+ .data = (void *)18,
+ },
+ {},
+};
+
+static struct platform_driver qepic_driver = {
+ .driver = {
+ .name = "qe_ports_ic",
+ .of_match_table = qepic_match,
+ },
+ .probe = qepic_probe,
+};
+
+static int __init qepic_init(void)
+{
+ return platform_driver_register(&qepic_driver);
+}
+arch_initcall(qepic_init);
--
2.49.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v5 2/7] soc: fsl: qe: Change GPIO driver to a proper platform driver
2025-09-01 12:05 [PATCH v5 0/7] Add support of IRQs to QUICC ENGINE GPIOs Christophe Leroy
2025-09-01 12:05 ` [PATCH v5 1/7] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Christophe Leroy
@ 2025-09-01 12:05 ` Christophe Leroy
2025-09-01 12:05 ` [PATCH v5 3/7] soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver Christophe Leroy
` (4 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Christophe Leroy @ 2025-09-01 12:05 UTC (permalink / raw)
To: Qiang Zhao, Linus Walleij, Bartosz Golaszewski, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Christophe Leroy, linux-kernel, linuxppc-dev, linux-arm-kernel,
linux-gpio, devicetree, Bartosz Golaszewski
In order to be able to add interrupts to the GPIOs, first change the
QE GPIO driver to the proper platform driver in order to allow
initialisation to be done in the right order, otherwise the GPIOs
get added before the interrupts are registered.
Remove linux/of.h and linux/property.h which are unused.
And to improve readability and reduce risk of errors, add a macro to
transform a pin number into the mask that matches the associated bit
in registers.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
v5: Added the PIN_MASK() macro
---
drivers/soc/fsl/qe/gpio.c | 98 +++++++++++++++++++++------------------
1 file changed, 53 insertions(+), 45 deletions(-)
diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index 8df1e8fa86a5..04b44fc2bb58 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -12,16 +12,17 @@
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <linux/of.h>
#include <linux/gpio/legacy-of-mm-gpiochip.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/export.h>
-#include <linux/property.h>
+#include <linux/platform_device.h>
#include <soc/fsl/qe/qe.h>
+#define PIN_MASK(gpio) (1UL << (QE_PIO_PINS - 1 - (gpio)))
+
struct qe_gpio_chip {
struct of_mm_gpio_chip mm_gc;
spinlock_t lock;
@@ -52,7 +53,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;
- u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
+ u32 pin_mask = PIN_MASK(gpio);
return !!(ioread32be(®s->cpdata) & pin_mask);
}
@@ -63,7 +64,7 @@ static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;
unsigned long flags;
- u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
+ u32 pin_mask = PIN_MASK(gpio);
spin_lock_irqsave(&qe_gc->lock, flags);
@@ -95,9 +96,9 @@ static int qe_gpio_set_multiple(struct gpio_chip *gc,
break;
if (__test_and_clear_bit(i, mask)) {
if (test_bit(i, bits))
- qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));
+ qe_gc->cpdata |= PIN_MASK(i);
else
- qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));
+ qe_gc->cpdata &= ~PIN_MASK(i);
}
}
@@ -295,45 +296,52 @@ void qe_pin_set_gpio(struct qe_pin *qe_pin)
}
EXPORT_SYMBOL(qe_pin_set_gpio);
-static int __init qe_add_gpiochips(void)
+static int qe_gpio_probe(struct platform_device *ofdev)
{
- struct device_node *np;
-
- for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
- int ret;
- struct qe_gpio_chip *qe_gc;
- struct of_mm_gpio_chip *mm_gc;
- struct gpio_chip *gc;
-
- qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
- if (!qe_gc) {
- ret = -ENOMEM;
- goto err;
- }
+ struct device *dev = &ofdev->dev;
+ struct device_node *np = dev->of_node;
+ struct qe_gpio_chip *qe_gc;
+ struct of_mm_gpio_chip *mm_gc;
+ struct gpio_chip *gc;
- spin_lock_init(&qe_gc->lock);
-
- mm_gc = &qe_gc->mm_gc;
- gc = &mm_gc->gc;
-
- mm_gc->save_regs = qe_gpio_save_regs;
- gc->ngpio = QE_PIO_PINS;
- gc->direction_input = qe_gpio_dir_in;
- gc->direction_output = qe_gpio_dir_out;
- gc->get = qe_gpio_get;
- gc->set = qe_gpio_set;
- gc->set_multiple = qe_gpio_set_multiple;
-
- ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
- if (ret)
- goto err;
- continue;
-err:
- pr_err("%pOF: registration failed with status %d\n",
- np, ret);
- kfree(qe_gc);
- /* try others anyway */
- }
- return 0;
+ qe_gc = devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL);
+ if (!qe_gc)
+ return -ENOMEM;
+
+ spin_lock_init(&qe_gc->lock);
+
+ mm_gc = &qe_gc->mm_gc;
+ gc = &mm_gc->gc;
+
+ mm_gc->save_regs = qe_gpio_save_regs;
+ gc->ngpio = QE_PIO_PINS;
+ gc->direction_input = qe_gpio_dir_in;
+ gc->direction_output = qe_gpio_dir_out;
+ gc->get = qe_gpio_get;
+ gc->set = qe_gpio_set;
+ gc->set_multiple = qe_gpio_set_multiple;
+
+ return of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
+}
+
+static const struct of_device_id qe_gpio_match[] = {
+ {
+ .compatible = "fsl,mpc8323-qe-pario-bank",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, qe_gpio_match);
+
+static struct platform_driver qe_gpio_driver = {
+ .probe = qe_gpio_probe,
+ .driver = {
+ .name = "qe-gpio",
+ .of_match_table = qe_gpio_match,
+ },
+};
+
+static int __init qe_gpio_init(void)
+{
+ return platform_driver_register(&qe_gpio_driver);
}
-arch_initcall(qe_add_gpiochips);
+arch_initcall(qe_gpio_init);
--
2.49.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v5 3/7] soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
2025-09-01 12:05 [PATCH v5 0/7] Add support of IRQs to QUICC ENGINE GPIOs Christophe Leroy
2025-09-01 12:05 ` [PATCH v5 1/7] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Christophe Leroy
2025-09-01 12:05 ` [PATCH v5 2/7] soc: fsl: qe: Change GPIO driver to a proper platform driver Christophe Leroy
@ 2025-09-01 12:05 ` Christophe Leroy
2025-09-02 13:44 ` Bartosz Golaszewski
2025-09-01 12:05 ` [PATCH v5 4/7] soc: fsl: qe: Add support of IRQ in QE GPIO Christophe Leroy
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Christophe Leroy @ 2025-09-01 12:05 UTC (permalink / raw)
To: Qiang Zhao, Linus Walleij, Bartosz Golaszewski, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Christophe Leroy, linux-kernel, linuxppc-dev, linux-arm-kernel,
linux-gpio, devicetree
Remove legacy-of-mm-gpiochip.h header file. The above mentioned
file provides an OF API that's deprecated. There is no agnostic
alternatives to it and we have to open code the logic which was
hidden behind of_mm_gpiochip_add_data(). Note, most of the GPIO
drivers are using their own labeling schemas and resource retrieval
that only a few may gain of the code deduplication, so whenever
alternative is appear we can move drivers again to use that one.
As a side effect this change fixes a potential memory leak on
an error path, if of_mm_gpiochip_add_data() fails.
[Text copied from commit 34064c8267a6 ("powerpc/8xx: Drop
legacy-of-mm-gpiochip.h header")]
Suggested-by: Bartosz Golaszewski <brgl@bgdev.pl>
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/platforms/Kconfig | 1 -
drivers/soc/fsl/qe/gpio.c | 51 ++++++++++++++++++----------------
2 files changed, 27 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index fea3766eac0f..5b689bd3ddf4 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -232,7 +232,6 @@ config QE_GPIO
bool "QE GPIO support"
depends on QUICC_ENGINE
select GPIOLIB
- select OF_GPIO_MM_GPIOCHIP
help
Say Y here if you're going to use hardware that connects to the
QE GPIOs.
diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index 04b44fc2bb58..c54154b404df 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -12,7 +12,6 @@
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <linux/gpio/legacy-of-mm-gpiochip.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
@@ -24,7 +23,8 @@
#define PIN_MASK(gpio) (1UL << (QE_PIO_PINS - 1 - (gpio)))
struct qe_gpio_chip {
- struct of_mm_gpio_chip mm_gc;
+ struct gpio_chip gc;
+ void __iomem *regs;
spinlock_t lock;
/* shadowed data register to clear/set bits safely */
@@ -34,11 +34,9 @@ struct qe_gpio_chip {
struct qe_pio_regs saved_regs;
};
-static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
+static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc)
{
- struct qe_gpio_chip *qe_gc =
- container_of(mm_gc, struct qe_gpio_chip, mm_gc);
- struct qe_pio_regs __iomem *regs = mm_gc->regs;
+ struct qe_pio_regs __iomem *regs = qe_gc->regs;
qe_gc->cpdata = ioread32be(®s->cpdata);
qe_gc->saved_regs.cpdata = qe_gc->cpdata;
@@ -51,8 +49,8 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
- struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
- struct qe_pio_regs __iomem *regs = mm_gc->regs;
+ struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
+ struct qe_pio_regs __iomem *regs = qe_gc->regs;
u32 pin_mask = PIN_MASK(gpio);
return !!(ioread32be(®s->cpdata) & pin_mask);
@@ -60,9 +58,8 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
- struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
- struct qe_pio_regs __iomem *regs = mm_gc->regs;
+ struct qe_pio_regs __iomem *regs = qe_gc->regs;
unsigned long flags;
u32 pin_mask = PIN_MASK(gpio);
@@ -83,9 +80,8 @@ static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
static int qe_gpio_set_multiple(struct gpio_chip *gc,
unsigned long *mask, unsigned long *bits)
{
- struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
- struct qe_pio_regs __iomem *regs = mm_gc->regs;
+ struct qe_pio_regs __iomem *regs = qe_gc->regs;
unsigned long flags;
int i;
@@ -111,13 +107,12 @@ static int qe_gpio_set_multiple(struct gpio_chip *gc,
static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
- struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
unsigned long flags;
spin_lock_irqsave(&qe_gc->lock, flags);
- __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
+ __par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
spin_unlock_irqrestore(&qe_gc->lock, flags);
@@ -126,7 +121,6 @@ static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
- struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
unsigned long flags;
@@ -134,7 +128,7 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
spin_lock_irqsave(&qe_gc->lock, flags);
- __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
+ __par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
spin_unlock_irqrestore(&qe_gc->lock, flags);
@@ -240,7 +234,7 @@ EXPORT_SYMBOL(qe_pin_free);
void qe_pin_set_dedicated(struct qe_pin *qe_pin)
{
struct qe_gpio_chip *qe_gc = qe_pin->controller;
- struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
+ struct qe_pio_regs __iomem *regs = qe_gc->regs;
struct qe_pio_regs *sregs = &qe_gc->saved_regs;
int pin = qe_pin->num;
u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
@@ -269,7 +263,6 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
iowrite32be(qe_gc->cpdata, ®s->cpdata);
qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
-
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
EXPORT_SYMBOL(qe_pin_set_dedicated);
@@ -284,7 +277,7 @@ EXPORT_SYMBOL(qe_pin_set_dedicated);
void qe_pin_set_gpio(struct qe_pin *qe_pin)
{
struct qe_gpio_chip *qe_gc = qe_pin->controller;
- struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
+ struct qe_pio_regs __iomem *regs = qe_gc->regs;
unsigned long flags;
spin_lock_irqsave(&qe_gc->lock, flags);
@@ -301,7 +294,6 @@ static int qe_gpio_probe(struct platform_device *ofdev)
struct device *dev = &ofdev->dev;
struct device_node *np = dev->of_node;
struct qe_gpio_chip *qe_gc;
- struct of_mm_gpio_chip *mm_gc;
struct gpio_chip *gc;
qe_gc = devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL);
@@ -310,18 +302,29 @@ static int qe_gpio_probe(struct platform_device *ofdev)
spin_lock_init(&qe_gc->lock);
- mm_gc = &qe_gc->mm_gc;
- gc = &mm_gc->gc;
+ gc = &qe_gc->gc;
- mm_gc->save_regs = qe_gpio_save_regs;
+ gc->base = -1;
gc->ngpio = QE_PIO_PINS;
gc->direction_input = qe_gpio_dir_in;
gc->direction_output = qe_gpio_dir_out;
gc->get = qe_gpio_get;
gc->set = qe_gpio_set;
gc->set_multiple = qe_gpio_set_multiple;
+ gc->parent = dev;
+ gc->owner = THIS_MODULE;
+
+ gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
+ if (!gc->label)
+ return -ENOMEM;
+
+ qe_gc->regs = devm_of_iomap(dev, np, 0, NULL);
+ if (IS_ERR(qe_gc->regs))
+ return PTR_ERR(qe_gc->regs);
+
+ qe_gpio_save_regs(qe_gc);
- return of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
+ return devm_gpiochip_add_data(dev, gc, qe_gc);
}
static const struct of_device_id qe_gpio_match[] = {
--
2.49.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v5 3/7] soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
2025-09-01 12:05 ` [PATCH v5 3/7] soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver Christophe Leroy
@ 2025-09-02 13:44 ` Bartosz Golaszewski
0 siblings, 0 replies; 15+ messages in thread
From: Bartosz Golaszewski @ 2025-09-02 13:44 UTC (permalink / raw)
To: Christophe Leroy
Cc: linux-kernel, linuxppc-dev, linux-arm-kernel, linux-gpio,
devicetree, Qiang Zhao, Linus Walleij, Bartosz Golaszewski,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
On Mon, 1 Sep 2025 14:05:10 +0200, Christophe Leroy
<christophe.leroy@csgroup.eu> said:
> Remove legacy-of-mm-gpiochip.h header file. The above mentioned
> file provides an OF API that's deprecated. There is no agnostic
> alternatives to it and we have to open code the logic which was
> hidden behind of_mm_gpiochip_add_data(). Note, most of the GPIO
> drivers are using their own labeling schemas and resource retrieval
> that only a few may gain of the code deduplication, so whenever
> alternative is appear we can move drivers again to use that one.
>
> As a side effect this change fixes a potential memory leak on
> an error path, if of_mm_gpiochip_add_data() fails.
>
> [Text copied from commit 34064c8267a6 ("powerpc/8xx: Drop
> legacy-of-mm-gpiochip.h header")]
>
> Suggested-by: Bartosz Golaszewski <brgl@bgdev.pl>
> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 4/7] soc: fsl: qe: Add support of IRQ in QE GPIO
2025-09-01 12:05 [PATCH v5 0/7] Add support of IRQs to QUICC ENGINE GPIOs Christophe Leroy
` (2 preceding siblings ...)
2025-09-01 12:05 ` [PATCH v5 3/7] soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver Christophe Leroy
@ 2025-09-01 12:05 ` Christophe Leroy
2025-09-02 10:50 ` kernel test robot
2025-09-01 12:05 ` [PATCH v5 5/7] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Christophe Leroy
` (2 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Christophe Leroy @ 2025-09-01 12:05 UTC (permalink / raw)
To: Qiang Zhao, Linus Walleij, Bartosz Golaszewski, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Christophe Leroy, linux-kernel, linuxppc-dev, linux-arm-kernel,
linux-gpio, devicetree, Bartosz Golaszewski
In the QE, a few GPIOs have an associated IRQ to notify changes.
Add IRQ support to QE GPIO.
As not all GPIOs have an associated IRQ, the driver needs to know
to which GPIO corresponds each provided IRQ. This is provided via
multiple compatible properties:
compatible = "fsl,mpc8323-qe-pario-bank-a"
compatible = "fsl,mpc8323-qe-pario-bank-b"
compatible = "fsl,mpc8323-qe-pario-bank-c"
compatible = "fsl,mpc8360-qe-pario-bank-a"
compatible = "fsl,mpc8360-qe-pario-bank-b"
compatible = "fsl,mpc8360-qe-pario-bank-c"
compatible = "fsl,mpc8360-qe-pario-bank-d"
compatible = "fsl,mpc8360-qe-pario-bank-e"
compatible = "fsl,mpc8360-qe-pario-bank-f"
compatible = "fsl,mpc8360-qe-pario-bank-g"
compatible = "fsl,mpc8568-qe-pario-bank-a"
compatible = "fsl,mpc8568-qe-pario-bank-b"
compatible = "fsl,mpc8568-qe-pario-bank-c"
compatible = "fsl,mpc8568-qe-pario-bank-d"
compatible = "fsl,mpc8568-qe-pario-bank-e"
compatible = "fsl,mpc8568-qe-pario-bank-f"
When not using IRQ and for banks having no IRQ (like bank D on mpc8323)
the origin compatible = "fsl,mpc8323-qe-pario-bank" is sufficient.
Here is an exemple for port B of mpc8323 which has IRQs for
GPIOs PB7, PB9, PB25 and PB27.
qe_pio_b: gpio-controller@1418 {
compatible = "fsl,mpc8323-qe-pario-bank-b";
reg = <0x1418 0x18>;
interrupts = <4 5 6 7>;
interrupt-parent = <&qepic>;
gpio-controller;
#gpio-cells = <2>;
};
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
v5: Provide the mask via the compatible data instead of adding a property in device tree
---
drivers/soc/fsl/qe/gpio.c | 72 +++++++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index c54154b404df..8632b0d37255 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -12,6 +12,7 @@
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/of_irq.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
@@ -32,6 +33,8 @@ struct qe_gpio_chip {
/* saved_regs used to restore dedicated functions */
struct qe_pio_regs saved_regs;
+
+ int irq[QE_PIO_PINS];
};
static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc)
@@ -135,6 +138,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
return 0;
}
+static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
+
+ return qe_gc->irq[gpio] ? : -ENXIO;
+}
+
struct qe_pin {
/*
* The qe_gpio_chip name is unfortunate, we should change that to
@@ -295,6 +305,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
struct device_node *np = dev->of_node;
struct qe_gpio_chip *qe_gc;
struct gpio_chip *gc;
+ u32 mask;
qe_gc = devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL);
if (!qe_gc)
@@ -302,6 +313,15 @@ static int qe_gpio_probe(struct platform_device *ofdev)
spin_lock_init(&qe_gc->lock);
+ mask = (u32)of_device_get_match_data(dev);
+ if (mask) {
+ int i, j;
+
+ for (i = 0, j = 0; i < ARRAY_SIZE(qe_gc->irq); i++)
+ if (mask & PIN_MASK(i))
+ qe_gc->irq[i] = irq_of_parse_and_map(np, j++);
+ }
+
gc = &qe_gc->gc;
gc->base = -1;
@@ -311,6 +331,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
gc->get = qe_gpio_get;
gc->set = qe_gpio_set;
gc->set_multiple = qe_gpio_set_multiple;
+ gc->to_irq = qe_gpio_to_irq;
gc->parent = dev;
gc->owner = THIS_MODULE;
@@ -330,6 +351,57 @@ static int qe_gpio_probe(struct platform_device *ofdev)
static const struct of_device_id qe_gpio_match[] = {
{
.compatible = "fsl,mpc8323-qe-pario-bank",
+ }, {
+ .compatible = "fsl,mpc8323-qe-pario-bank-a",
+ .data = (void *)(PIN_MASK(8) | PIN_MASK(10) | PIN_MASK(26) | PIN_MASK(28)),
+ }, {
+ .compatible = "fsl,mpc8323-qe-pario-bank-b",
+ .data = (void *)(PIN_MASK(7) | PIN_MASK(9) | PIN_MASK(25) | PIN_MASK(27)),
+ }, {
+ .compatible = "fsl,mpc8323-qe-pario-bank-c",
+ .data = (void *)(PIN_MASK(24) | PIN_MASK(29)),
+ }, {
+ .compatible = "fsl,mpc8360-qe-pario-bank-a",
+ .data = (void *)(PIN_MASK(15) | PIN_MASK(16) | PIN_MASK(29) | PIN_MASK(30)),
+ }, {
+ .compatible = "fsl,mpc8360-qe-pario-bank-b",
+ .data = (void *)(PIN_MASK(3) | PIN_MASK(5) | PIN_MASK(12) | PIN_MASK(13) |
+ PIN_MASK(26) | PIN_MASK(27)),
+ }, {
+ .compatible = "fsl,mpc8360-qe-pario-bank-c",
+ .data = (void *)(PIN_MASK(27) | PIN_MASK(28) | PIN_MASK(29)),
+ }, {
+ .compatible = "fsl,mpc8360-qe-pario-bank-d",
+ .data = (void *)(PIN_MASK(12) | PIN_MASK(13) | PIN_MASK(16) | PIN_MASK(17) |
+ PIN_MASK(26) | PIN_MASK(27)),
+ }, {
+ .compatible = "fsl,mpc8360-qe-pario-bank-e",
+ .data = (void *)(PIN_MASK(12) | PIN_MASK(13) | PIN_MASK(24) | PIN_MASK(25) |
+ PIN_MASK(26) | PIN_MASK(27) | PIN_MASK(31)),
+ }, {
+ .compatible = "fsl,mpc8360-qe-pario-bank-f",
+ .data = (void *)(PIN_MASK(20)),
+ }, {
+ .compatible = "fsl,mpc8360-qe-pario-bank-g",
+ .data = (void *)(PIN_MASK(31)),
+ }, {
+ .compatible = "fsl,mpc8568-qe-pario-bank-a",
+ .data = (void *)(PIN_MASK(22) | PIN_MASK(23)),
+ }, {
+ .compatible = "fsl,mpc8568-qe-pario-bank-b",
+ .data = (void *)(PIN_MASK(12) | PIN_MASK(13) | PIN_MASK(28) | PIN_MASK(29)),
+ }, {
+ .compatible = "fsl,mpc8568-qe-pario-bank-c",
+ .data = (void *)(PIN_MASK(16) | PIN_MASK(17) | PIN_MASK(25) | PIN_MASK(26)),
+ }, {
+ .compatible = "fsl,mpc8568-qe-pario-bank-d",
+ .data = (void *)(PIN_MASK(18) | PIN_MASK(19)),
+ }, {
+ .compatible = "fsl,mpc8568-qe-pario-bank-e",
+ .data = (void *)(PIN_MASK(12) | PIN_MASK(16) | PIN_MASK(30)),
+ }, {
+ .compatible = "fsl,mpc8568-qe-pario-bank-f",
+ .data = (void *)(PIN_MASK(12) | PIN_MASK(16) | PIN_MASK(30)),
},
{},
};
--
2.49.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v5 4/7] soc: fsl: qe: Add support of IRQ in QE GPIO
2025-09-01 12:05 ` [PATCH v5 4/7] soc: fsl: qe: Add support of IRQ in QE GPIO Christophe Leroy
@ 2025-09-02 10:50 ` kernel test robot
2025-09-02 17:28 ` Christophe Leroy
0 siblings, 1 reply; 15+ messages in thread
From: kernel test robot @ 2025-09-02 10:50 UTC (permalink / raw)
To: Christophe Leroy; +Cc: llvm, oe-kbuild-all
Hi Christophe,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on powerpc/next powerpc/fixes linus/master v6.17-rc4]
[cannot apply to next-20250902]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Christophe-Leroy/soc-fsl-qe-Add-an-interrupt-controller-for-QUICC-Engine-Ports/20250901-202447
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/1234b2b7105443654c5f2bb97d25cf16408d6003.1756727747.git.christophe.leroy%40csgroup.eu
patch subject: [PATCH v5 4/7] soc: fsl: qe: Add support of IRQ in QE GPIO
config: powerpc64-randconfig-003-20250902 (https://download.01.org/0day-ci/archive/20250902/202509021830.uakzVIlK-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 2e122990391b2ba062e6308a12cfedf7206270ba)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250902/202509021830.uakzVIlK-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509021830.uakzVIlK-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from <built-in>:3:
In file included from include/linux/compiler_types.h:171:
include/linux/compiler-clang.h:37:9: warning: '__SANITIZE_THREAD__' macro redefined [-Wmacro-redefined]
37 | #define __SANITIZE_THREAD__
| ^
<built-in>:352:9: note: previous definition is here
352 | #define __SANITIZE_THREAD__ 1
| ^
>> drivers/soc/fsl/qe/gpio.c:316:9: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'const void *' [-Wvoid-pointer-to-int-cast]
316 | mask = (u32)of_device_get_match_data(dev);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2 warnings generated.
vim +316 drivers/soc/fsl/qe/gpio.c
301
302 static int qe_gpio_probe(struct platform_device *ofdev)
303 {
304 struct device *dev = &ofdev->dev;
305 struct device_node *np = dev->of_node;
306 struct qe_gpio_chip *qe_gc;
307 struct gpio_chip *gc;
308 u32 mask;
309
310 qe_gc = devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL);
311 if (!qe_gc)
312 return -ENOMEM;
313
314 spin_lock_init(&qe_gc->lock);
315
> 316 mask = (u32)of_device_get_match_data(dev);
317 if (mask) {
318 int i, j;
319
320 for (i = 0, j = 0; i < ARRAY_SIZE(qe_gc->irq); i++)
321 if (mask & PIN_MASK(i))
322 qe_gc->irq[i] = irq_of_parse_and_map(np, j++);
323 }
324
325 gc = &qe_gc->gc;
326
327 gc->base = -1;
328 gc->ngpio = QE_PIO_PINS;
329 gc->direction_input = qe_gpio_dir_in;
330 gc->direction_output = qe_gpio_dir_out;
331 gc->get = qe_gpio_get;
332 gc->set = qe_gpio_set;
333 gc->set_multiple = qe_gpio_set_multiple;
334 gc->to_irq = qe_gpio_to_irq;
335 gc->parent = dev;
336 gc->owner = THIS_MODULE;
337
338 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
339 if (!gc->label)
340 return -ENOMEM;
341
342 qe_gc->regs = devm_of_iomap(dev, np, 0, NULL);
343 if (IS_ERR(qe_gc->regs))
344 return PTR_ERR(qe_gc->regs);
345
346 qe_gpio_save_regs(qe_gc);
347
348 return devm_gpiochip_add_data(dev, gc, qe_gc);
349 }
350
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v5 4/7] soc: fsl: qe: Add support of IRQ in QE GPIO
2025-09-02 10:50 ` kernel test robot
@ 2025-09-02 17:28 ` Christophe Leroy
0 siblings, 0 replies; 15+ messages in thread
From: Christophe Leroy @ 2025-09-02 17:28 UTC (permalink / raw)
To: kernel test robot; +Cc: llvm, oe-kbuild-all
Le 02/09/2025 à 12:50, kernel test robot a écrit :
> Hi Christophe,
>
> kernel test robot noticed the following build warnings:
>
> [auto build test WARNING on robh/for-next]
> [also build test WARNING on powerpc/next powerpc/fixes linus/master v6.17-rc4]
> [cannot apply to next-20250902]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit-scm.com%2Fdocs%2Fgit-format-patch%23_base_tree_information&data=05%7C02%7Cchristophe.leroy%40csgroup.eu%7Ca3ddcbd613fd48271bba08ddea0eb403%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C638924071075803525%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=%2BniURYrufRzhFQ7KXwgpmnJIfeJWcTMavXkEndbtHYA%3D&reserved=0]
>
> url: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fintel-lab-lkp%2Flinux%2Fcommits%2FChristophe-Leroy%2Fsoc-fsl-qe-Add-an-interrupt-controller-for-QUICC-Engine-Ports%2F20250901-202447&data=05%7C02%7Cchristophe.leroy%40csgroup.eu%7Ca3ddcbd613fd48271bba08ddea0eb403%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C638924071075825139%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=v43MiEVTfpflIobzhrSvzs4IZcmfHuSrXyUJHafSLNk%3D&reserved=0
> base: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Frobh%2Flinux.git&data=05%7C02%7Cchristophe.leroy%40csgroup.eu%7Ca3ddcbd613fd48271bba08ddea0eb403%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C638924071075840967%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=g1r1XaGeDG5nZqIU1b61fCZlve9VQaMIliHoufnXFLU%3D&reserved=0 for-next
> patch link: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fr%2F1234b2b7105443654c5f2bb97d25cf16408d6003.1756727747.git.christophe.leroy%2540csgroup.eu&data=05%7C02%7Cchristophe.leroy%40csgroup.eu%7Ca3ddcbd613fd48271bba08ddea0eb403%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C638924071075856717%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=BWYYNgbEu2UZWOS8XRlq%2FdGddmBDeQ%2BjDb%2FIorMXSmc%3D&reserved=0
> patch subject: [PATCH v5 4/7] soc: fsl: qe: Add support of IRQ in QE GPIO
> config: powerpc64-randconfig-003-20250902 (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdownload.01.org%2F0day-ci%2Farchive%2F20250902%2F202509021830.uakzVIlK-lkp%40intel.com%2Fconfig&data=05%7C02%7Cchristophe.leroy%40csgroup.eu%7Ca3ddcbd613fd48271bba08ddea0eb403%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C638924071075872388%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=M6TMS23JmgSVi3aQZDvjZcOn9vX7HyUc8%2BcoLOjfN6E%3D&reserved=0)
> compiler: clang version 22.0.0git (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fllvm%2Fllvm-project&data=05%7C02%7Cchristophe.leroy%40csgroup.eu%7Ca3ddcbd613fd48271bba08ddea0eb403%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C638924071075888080%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=3uIHxd8uhuDUbQRCQbcW%2BFnR1uvJZeN3AQWOR039L7A%3D&reserved=0 2e122990391b2ba062e6308a12cfedf7206270ba)
> reproduce (this is a W=1 build): (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdownload.01.org%2F0day-ci%2Farchive%2F20250902%2F202509021830.uakzVIlK-lkp%40intel.com%2Freproduce&data=05%7C02%7Cchristophe.leroy%40csgroup.eu%7Ca3ddcbd613fd48271bba08ddea0eb403%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C638924071075903628%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=y13g2bKm6FrjWSiErSO83akrf3BclbaIQ4142F9f5Tk%3D&reserved=0)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Foe-kbuild-all%2F202509021830.uakzVIlK-lkp%40intel.com%2F&data=05%7C02%7Cchristophe.leroy%40csgroup.eu%7Ca3ddcbd613fd48271bba08ddea0eb403%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C638924071075921207%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=j%2BMDWBvsHHtgzjiHc83gr3OguP22jVJ41AmVgFtT6eM%3D&reserved=0
>
> All warnings (new ones prefixed by >>):
>
> In file included from <built-in>:3:
> In file included from include/linux/compiler_types.h:171:
> include/linux/compiler-clang.h:37:9: warning: '__SANITIZE_THREAD__' macro redefined [-Wmacro-redefined]
> 37 | #define __SANITIZE_THREAD__
> | ^
> <built-in>:352:9: note: previous definition is here
> 352 | #define __SANITIZE_THREAD__ 1
> | ^
>>> drivers/soc/fsl/qe/gpio.c:316:9: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'const void *' [-Wvoid-pointer-to-int-cast]
> 316 | mask = (u32)of_device_get_match_data(dev);
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 2 warnings generated.
>
Will be fixed with the following change in the patch:
diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index 8632b0d37255..7a23eb220217 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -305,7 +305,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
struct device_node *np = dev->of_node;
struct qe_gpio_chip *qe_gc;
struct gpio_chip *gc;
- u32 mask;
+ unsigned long mask;
qe_gc = devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL);
if (!qe_gc)
@@ -313,7 +313,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
spin_lock_init(&qe_gc->lock);
- mask = (u32)of_device_get_match_data(dev);
+ mask = (unsigned long)of_device_get_match_data(dev);
if (mask) {
int i, j;
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 5/7] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports
2025-09-01 12:05 [PATCH v5 0/7] Add support of IRQs to QUICC ENGINE GPIOs Christophe Leroy
` (3 preceding siblings ...)
2025-09-01 12:05 ` [PATCH v5 4/7] soc: fsl: qe: Add support of IRQ in QE GPIO Christophe Leroy
@ 2025-09-01 12:05 ` Christophe Leroy
2025-09-01 12:05 ` [PATCH v5 6/7] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema Christophe Leroy
2025-09-01 12:05 ` [PATCH v5 7/7] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO Christophe Leroy
6 siblings, 0 replies; 15+ messages in thread
From: Christophe Leroy @ 2025-09-01 12:05 UTC (permalink / raw)
To: Qiang Zhao, Linus Walleij, Bartosz Golaszewski, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Christophe Leroy, linux-kernel, linuxppc-dev, linux-arm-kernel,
linux-gpio, devicetree, Conor Dooley
The QUICC Engine provides interrupts for a few I/O ports. This is
handled via a separate interrupt ID and managed via a triplet of
dedicated registers hosted by the SoC.
Implement an interrupt driver for it for that those IRQs can then
be linked to the related GPIOs.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
new file mode 100644
index 000000000000..a356ad8b13f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale QUICC Engine I/O Ports Interrupt Controller
+
+maintainers:
+ - Christophe Leroy <christophe.leroy@csgroup.eu>
+
+description:
+ Interrupt controller for the QUICC Engine I/O ports found on some Freescale/NXP PowerQUICC and QorIQ SoCs.
+
+properties:
+ compatible:
+ enum:
+ - fsl,mpc8323-qe-ports-ic
+ - fsl,mpc8360-qe-ports-ic
+ - fsl,mpc8568-qe-ports-ic
+
+ reg:
+ maxItems: 1
+ description: Base address and size of the QE I/O Ports Interrupt Controller registers.
+
+ interrupt-controller: true
+
+ '#address-cells':
+ const: 0
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupts:
+ maxItems: 1
+ description: Interrupt line to which the QE I/O Ports controller is connected.
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#address-cells'
+ - '#interrupt-cells'
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@c00 {
+ compatible = "fsl,mpc8323-qe-ports-ic";
+ reg = <0xc00 0x18>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupts = <74 0x8>;
+ interrupt-parent = <&ipic>;
+ };
--
2.49.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v5 6/7] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema
2025-09-01 12:05 [PATCH v5 0/7] Add support of IRQs to QUICC ENGINE GPIOs Christophe Leroy
` (4 preceding siblings ...)
2025-09-01 12:05 ` [PATCH v5 5/7] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Christophe Leroy
@ 2025-09-01 12:05 ` Christophe Leroy
2025-09-02 21:24 ` Rob Herring
2025-09-01 12:05 ` [PATCH v5 7/7] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO Christophe Leroy
6 siblings, 1 reply; 15+ messages in thread
From: Christophe Leroy @ 2025-09-01 12:05 UTC (permalink / raw)
To: Qiang Zhao, Linus Walleij, Bartosz Golaszewski, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Christophe Leroy, linux-kernel, linuxppc-dev, linux-arm-kernel,
linux-gpio, devicetree
Convert QE QPIO devicetree binding to DT schema.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
v5: New
---
.../fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml | 53 +++++++++++++++++++
.../bindings/soc/fsl/cpm_qe/qe/par_io.txt | 26 +--------
2 files changed, 54 insertions(+), 25 deletions(-)
create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml
new file mode 100644
index 000000000000..e6ba319a75c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale QUICC Engine Parallel I/O (QE PARIO) GPIO Bank
+
+maintainers:
+ - Christophe Leroy <christophe.leroy@csgroup.eu>
+
+description:
+ Bindings for the Freescale QUICC Engine Parallel I/O (PARIO) GPIO controller.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,chip-qe-pario-bank
+ - const: fsl,mpc8323-qe-pario-bank
+
+ reg:
+ maxItems: 1
+ description: Offset to the register set and its length.
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ qe_pio_a: gpio-controller@1400 {
+ compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank";
+ reg = <0x1400 0x18>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ qe_pio_e: gpio-controller@1460 {
+ compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank";
+ reg = <0x1460 0x18>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt
index 09b1b05fa677..782699c14567 100644
--- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt
@@ -24,28 +24,4 @@ par_io@1400 {
Note that "par_io" nodes are obsolete, and should not be used for
the new device trees. Instead, each Par I/O bank should be represented
-via its own gpio-controller node:
-
-Required properties:
-- #gpio-cells : should be "2".
-- compatible : should be "fsl,<chip>-qe-pario-bank",
- "fsl,mpc8323-qe-pario-bank".
-- reg : offset to the register set and its length.
-- gpio-controller : node to identify gpio controllers.
-
-Example:
- qe_pio_a: gpio-controller@1400 {
- #gpio-cells = <2>;
- compatible = "fsl,mpc8360-qe-pario-bank",
- "fsl,mpc8323-qe-pario-bank";
- reg = <0x1400 0x18>;
- gpio-controller;
- };
-
- qe_pio_e: gpio-controller@1460 {
- #gpio-cells = <2>;
- compatible = "fsl,mpc8360-qe-pario-bank",
- "fsl,mpc8323-qe-pario-bank";
- reg = <0x1460 0x18>;
- gpio-controller;
- };
+via its own gpio-controller node.
--
2.49.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v5 6/7] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema
2025-09-01 12:05 ` [PATCH v5 6/7] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema Christophe Leroy
@ 2025-09-02 21:24 ` Rob Herring
2025-09-03 4:58 ` Christophe Leroy
0 siblings, 1 reply; 15+ messages in thread
From: Rob Herring @ 2025-09-02 21:24 UTC (permalink / raw)
To: Christophe Leroy
Cc: Qiang Zhao, Linus Walleij, Bartosz Golaszewski,
Krzysztof Kozlowski, Conor Dooley, linux-kernel, linuxppc-dev,
linux-arm-kernel, linux-gpio, devicetree
On Mon, Sep 01, 2025 at 02:05:13PM +0200, Christophe Leroy wrote:
> Convert QE QPIO devicetree binding to DT schema.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> v5: New
> ---
> .../fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml | 53 +++++++++++++++++++
This should move to bindings/gpio/
> .../bindings/soc/fsl/cpm_qe/qe/par_io.txt | 26 +--------
> 2 files changed, 54 insertions(+), 25 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml
> new file mode 100644
> index 000000000000..e6ba319a75c1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale QUICC Engine Parallel I/O (QE PARIO) GPIO Bank
> +
> +maintainers:
> + - Christophe Leroy <christophe.leroy@csgroup.eu>
> +
> +description:
> + Bindings for the Freescale QUICC Engine Parallel I/O (PARIO) GPIO controller.
Just drop if nothing more to say than 'title'.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,chip-qe-pario-bank
> + - const: fsl,mpc8323-qe-pario-bank
> +
> + reg:
> + maxItems: 1
> + description: Offset to the register set and its length.
Drop the description. That's every reg.
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + const: 2
> +
> +required:
> + - compatible
> + - reg
> + - gpio-controller
> + - '#gpio-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + qe_pio_a: gpio-controller@1400 {
Drop unused labels.
> + compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank";
Doesn't match the schema.
> + reg = <0x1400 0x18>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + qe_pio_e: gpio-controller@1460 {
> + compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank";
> + reg = <0x1460 0x18>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v5 6/7] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema
2025-09-02 21:24 ` Rob Herring
@ 2025-09-03 4:58 ` Christophe Leroy
2025-09-09 8:55 ` Christophe Leroy
0 siblings, 1 reply; 15+ messages in thread
From: Christophe Leroy @ 2025-09-03 4:58 UTC (permalink / raw)
To: Rob Herring
Cc: Qiang Zhao, Linus Walleij, Bartosz Golaszewski,
Krzysztof Kozlowski, Conor Dooley, linux-kernel, linuxppc-dev,
linux-arm-kernel, linux-gpio, devicetree
Hi Rob,
Le 02/09/2025 à 23:24, Rob Herring a écrit :
> On Mon, Sep 01, 2025 at 02:05:13PM +0200, Christophe Leroy wrote:
>> Convert QE QPIO devicetree binding to DT schema.
>>
>> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
>> ---
>> v5: New
>> ---
>
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - fsl,chip-qe-pario-bank
>> + - const: fsl,mpc8323-qe-pario-bank
>> +
snip
>
>> + compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank";
>
> Doesn't match the schema.
>
Can you be more explicit ? Is it the 'mpc8360' ? It is the 'chip'.
bindings/soc/fsl/cpm_qe/qe/par_io.txt was saying:
- compatible : should be "fsl,<chip>-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank".
Which I first translated in yaml as :
properties:
compatible:
items:
- enum:
- fsl,<chip>-qe-pario-bank
- const: fsl,mpc8323-qe-pario-bank
But 'make dt_binding_check' complained about the < > around 'chip' so I
removed them.
How should it be described ?
Thanks
Christophe
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v5 6/7] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema
2025-09-03 4:58 ` Christophe Leroy
@ 2025-09-09 8:55 ` Christophe Leroy
0 siblings, 0 replies; 15+ messages in thread
From: Christophe Leroy @ 2025-09-09 8:55 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Qiang Zhao, Linus Walleij, Bartosz Golaszewski, linux-kernel,
linuxppc-dev, linux-arm-kernel, linux-gpio, devicetree
Rob, Conor, Krzysztof,
Can one of you or someone else help me with below comment from Rob ?
Le 03/09/2025 à 06:58, Christophe Leroy a écrit :
> Hi Rob,
>
> Le 02/09/2025 à 23:24, Rob Herring a écrit :
>> On Mon, Sep 01, 2025 at 02:05:13PM +0200, Christophe Leroy wrote:
>>> Convert QE QPIO devicetree binding to DT schema.
>>>
>>> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
>>> ---
>>> v5: New
>>> ---
>>
>>> +
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - fsl,chip-qe-pario-bank
>>> + - const: fsl,mpc8323-qe-pario-bank
>>> +
>
> snip
>
>>
>>> + compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-
>>> pario-bank";
>>
>> Doesn't match the schema.
>>
>
> Can you be more explicit ? Is it the 'mpc8360' ? It is the 'chip'.
>
>
> bindings/soc/fsl/cpm_qe/qe/par_io.txt was saying:
>
> - compatible : should be "fsl,<chip>-qe-pario-bank", "fsl,mpc8323-qe-
> pario-bank".
>
> Which I first translated in yaml as :
>
> properties:
> compatible:
> items:
> - enum:
> - fsl,<chip>-qe-pario-bank
> - const: fsl,mpc8323-qe-pario-bank
>
> But 'make dt_binding_check' complained about the < > around 'chip' so I
> removed them.
>
> How should it be described ?
>
Here is what we have in existing DTS upstream:
arch/powerpc/boot/dts/fsl/mpc8569mds.dts-
compatible = "fsl,mpc8569-qe-pario-bank",
arch/powerpc/boot/dts/fsl/mpc8569mds.dts:
"fsl,mpc8323-qe-pario-bank";
--
arch/powerpc/boot/dts/fsl/mpc8569mds.dts-
compatible = "fsl,mpc8569-qe-pario-bank",
arch/powerpc/boot/dts/fsl/mpc8569mds.dts:
"fsl,mpc8323-qe-pario-bank";
--
arch/powerpc/boot/dts/kmeter1.dts-
compatible = "fsl,mpc8360-qe-pario-bank",
arch/powerpc/boot/dts/kmeter1.dts:
"fsl,mpc8323-qe-pario-bank";
--
arch/powerpc/boot/dts/mpc832x_rdb.dts:
compatible = "fsl,mpc8323-qe-pario-bank";
--
arch/powerpc/boot/dts/mpc836x_rdk.dts- compatible =
"fsl,mpc8360-qe-pario-bank",
arch/powerpc/boot/dts/mpc836x_rdk.dts:
"fsl,mpc8323-qe-pario-bank";
--
arch/powerpc/boot/dts/mpc836x_rdk.dts- compatible =
"fsl,mpc8360-qe-pario-bank",
arch/powerpc/boot/dts/mpc836x_rdk.dts:
"fsl,mpc8323-qe-pario-bank";
If the problem in the DT schema is the fsl,chip-qe-pario-bank, should I
replace it with the two possible compatible we have in existing DTS, ie
"fsl,mpc8569-qe-pario-bank" and "fsl,mpc8360-qe-pario-bank", or should I
just ignore them are they are useless for the drivers, or else ?
Thanks
Christophe
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 7/7] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO
2025-09-01 12:05 [PATCH v5 0/7] Add support of IRQs to QUICC ENGINE GPIOs Christophe Leroy
` (5 preceding siblings ...)
2025-09-01 12:05 ` [PATCH v5 6/7] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema Christophe Leroy
@ 2025-09-01 12:05 ` Christophe Leroy
6 siblings, 0 replies; 15+ messages in thread
From: Christophe Leroy @ 2025-09-01 12:05 UTC (permalink / raw)
To: Qiang Zhao, Linus Walleij, Bartosz Golaszewski, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Christophe Leroy, linux-kernel, linuxppc-dev, linux-arm-kernel,
linux-gpio, devicetree
In the QE, a few GPIOs have an associated IRQ to notify changes.
Add IRQ support to QE GPIO.
As not all GPIOs have an associated IRQ, the driver needs to know
to which GPIO corresponds each provided IRQ. This is provided via
multiple compatible properties:
compatible = "fsl,mpc8323-qe-pario-bank-a"
compatible = "fsl,mpc8323-qe-pario-bank-b"
compatible = "fsl,mpc8323-qe-pario-bank-c"
compatible = "fsl,mpc8360-qe-pario-bank-a"
compatible = "fsl,mpc8360-qe-pario-bank-b"
compatible = "fsl,mpc8360-qe-pario-bank-c"
compatible = "fsl,mpc8360-qe-pario-bank-d"
compatible = "fsl,mpc8360-qe-pario-bank-e"
compatible = "fsl,mpc8360-qe-pario-bank-f"
compatible = "fsl,mpc8360-qe-pario-bank-g"
compatible = "fsl,mpc8568-qe-pario-bank-a"
compatible = "fsl,mpc8568-qe-pario-bank-b"
compatible = "fsl,mpc8568-qe-pario-bank-c"
compatible = "fsl,mpc8568-qe-pario-bank-d"
compatible = "fsl,mpc8568-qe-pario-bank-e"
compatible = "fsl,mpc8568-qe-pario-bank-f"
When not using IRQ and for banks having no IRQ (like bank D on mpc8323)
the origin compatible = "fsl,mpc8323-qe-pario-bank" is still valid.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
v5: Changed to DT schema
---
.../fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml | 27 +++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml
index e6ba319a75c1..80f93914c779 100644
--- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml
@@ -17,6 +17,22 @@ properties:
items:
- enum:
- fsl,chip-qe-pario-bank
+ - fsl,mpc8323-qe-pario-bank-a
+ - fsl,mpc8323-qe-pario-bank-b
+ - fsl,mpc8323-qe-pario-bank-c
+ - fsl,mpc8360-qe-pario-bank-a
+ - fsl,mpc8360-qe-pario-bank-b
+ - fsl,mpc8360-qe-pario-bank-c
+ - fsl,mpc8360-qe-pario-bank-d
+ - fsl,mpc8360-qe-pario-bank-e
+ - fsl,mpc8360-qe-pario-bank-f
+ - fsl,mpc8360-qe-pario-bank-g
+ - fsl,mpc8568-qe-pario-bank-a
+ - fsl,mpc8568-qe-pario-bank-b
+ - fsl,mpc8568-qe-pario-bank-c
+ - fsl,mpc8568-qe-pario-bank-d
+ - fsl,mpc8568-qe-pario-bank-e
+ - fsl,mpc8568-qe-pario-bank-f
- const: fsl,mpc8323-qe-pario-bank
reg:
@@ -28,6 +44,9 @@ properties:
'#gpio-cells':
const: 2
+ interrupts:
+ description: List of interrupts for lines of the port that trigger interrupts on change.
+
required:
- compatible
- reg
@@ -39,15 +58,19 @@ additionalProperties: false
examples:
- |
qe_pio_a: gpio-controller@1400 {
- compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank";
+ compatible = "fsl,mpc8360-qe-pario-bank-a", "fsl,mpc8323-qe-pario-bank";
reg = <0x1400 0x18>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <0 1 2 3>;
+ interrupt-parent = <&qepic>;
};
qe_pio_e: gpio-controller@1460 {
- compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank";
+ compatible = "fsl,mpc8360-qe-pario-bank-e", "fsl,mpc8323-qe-pario-bank";
reg = <0x1460 0x18>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <19 20 21 22 23 24 25>;
+ interrupt-parent = <&qepic>;
};
--
2.49.0
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