* [PATCH v2] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2
@ 2025-09-18 6:28 ` Chaoyi Chen
0 siblings, 0 replies; 8+ messages in thread
From: Chaoyi Chen @ 2025-09-18 6:28 UTC (permalink / raw)
To: Heiko Stuebner, Andy Yan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Quentin Schulz,
Dragan Simic, FUKAUMI Naoki, Jonas Karlman, Peter Robinson,
Chaoyi Chen, Geert Uytterhoeven, Cristian Ciocaltea,
Sebastian Reichel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
The rk3588 evb2 board has a full size DisplayPort connector, enable
for it.
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
---
Changes in v2:
- Link to V1: https://lore.kernel.org/all/20250916080802.125-1-kernel@airkyi.com/
- Fix invalid DP connector type
- Add more comment about dclk_vp2 parent clock
.../boot/dts/rockchip/rk3588-evb2-v10.dts | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
index 91fe810d38d8..60ba6ac55b23 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
@@ -25,6 +25,18 @@ chosen {
stdout-path = "serial2:1500000n8";
};
+ dp-con {
+ compatible = "dp-connector";
+ label = "DP OUT";
+ type = "full-size";
+
+ port {
+ dp_con_in: endpoint {
+ remote-endpoint = <&dp0_out_con>;
+ };
+ };
+ };
+
hdmi-con {
compatible = "hdmi-connector";
type = "a";
@@ -106,6 +118,24 @@ vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
};
};
+&dp0 {
+ pinctrl-0 = <&dp0m0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&dp0_in {
+ dp0_in_vp2: endpoint {
+ remote-endpoint = <&vp2_out_dp0>;
+ };
+};
+
+&dp0_out {
+ dp0_out_con: endpoint {
+ remote-endpoint = <&dp_con_in>;
+ };
+};
+
&gpu {
mali-supply = <&vdd_gpu_s0>;
sram-supply = <&vdd_gpu_mem_s0>;
@@ -916,6 +946,17 @@ &usb_host1_xhci {
};
&vop {
+ /*
+ * If no dedicated PLL was specified, the GPLL would be automatically
+ * assigned as the PLL source for dclk_vop2. As the frequency of GPLL
+ * is 1188 MHz, we can only get typical clock frequencies such as
+ * 74.25MHz, 148.5MHz, 297MHz, 594MHz.
+ *
+ * So here we set the parent clock of VP2 to V0PLL so that we can get
+ * any frequency.
+ */
+ assigned-clocks = <&cru DCLK_VOP2_SRC>;
+ assigned-clock-parents = <&cru PLL_V0PLL>;
status = "okay";
};
@@ -929,3 +970,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
remote-endpoint = <&hdmi0_in_vp0>;
};
};
+
+&vp2 {
+ vp2_out_dp0: endpoint@a {
+ reg = <ROCKCHIP_VOP2_EP_DP0>;
+ remote-endpoint = <&dp0_in_vp2>;
+ };
+};
--
2.49.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2
@ 2025-09-18 6:28 ` Chaoyi Chen
0 siblings, 0 replies; 8+ messages in thread
From: Chaoyi Chen @ 2025-09-18 6:28 UTC (permalink / raw)
To: Heiko Stuebner, Andy Yan
Cc: Rob Herring, Conor Dooley, linux-kernel, Geert Uytterhoeven,
Jonas Karlman, Quentin Schulz, Sebastian Reichel, Chaoyi Chen,
linux-rockchip, devicetree, FUKAUMI Naoki, Peter Robinson,
Krzysztof Kozlowski, Dragan Simic, linux-arm-kernel
From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
The rk3588 evb2 board has a full size DisplayPort connector, enable
for it.
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
---
Changes in v2:
- Link to V1: https://lore.kernel.org/all/20250916080802.125-1-kernel@airkyi.com/
- Fix invalid DP connector type
- Add more comment about dclk_vp2 parent clock
.../boot/dts/rockchip/rk3588-evb2-v10.dts | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
index 91fe810d38d8..60ba6ac55b23 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
@@ -25,6 +25,18 @@ chosen {
stdout-path = "serial2:1500000n8";
};
+ dp-con {
+ compatible = "dp-connector";
+ label = "DP OUT";
+ type = "full-size";
+
+ port {
+ dp_con_in: endpoint {
+ remote-endpoint = <&dp0_out_con>;
+ };
+ };
+ };
+
hdmi-con {
compatible = "hdmi-connector";
type = "a";
@@ -106,6 +118,24 @@ vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
};
};
+&dp0 {
+ pinctrl-0 = <&dp0m0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&dp0_in {
+ dp0_in_vp2: endpoint {
+ remote-endpoint = <&vp2_out_dp0>;
+ };
+};
+
+&dp0_out {
+ dp0_out_con: endpoint {
+ remote-endpoint = <&dp_con_in>;
+ };
+};
+
&gpu {
mali-supply = <&vdd_gpu_s0>;
sram-supply = <&vdd_gpu_mem_s0>;
@@ -916,6 +946,17 @@ &usb_host1_xhci {
};
&vop {
+ /*
+ * If no dedicated PLL was specified, the GPLL would be automatically
+ * assigned as the PLL source for dclk_vop2. As the frequency of GPLL
+ * is 1188 MHz, we can only get typical clock frequencies such as
+ * 74.25MHz, 148.5MHz, 297MHz, 594MHz.
+ *
+ * So here we set the parent clock of VP2 to V0PLL so that we can get
+ * any frequency.
+ */
+ assigned-clocks = <&cru DCLK_VOP2_SRC>;
+ assigned-clock-parents = <&cru PLL_V0PLL>;
status = "okay";
};
@@ -929,3 +970,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
remote-endpoint = <&hdmi0_in_vp0>;
};
};
+
+&vp2 {
+ vp2_out_dp0: endpoint@a {
+ reg = <ROCKCHIP_VOP2_EP_DP0>;
+ remote-endpoint = <&dp0_in_vp2>;
+ };
+};
--
2.49.0
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2
2025-09-18 6:28 ` Chaoyi Chen
@ 2025-09-18 10:39 ` Quentin Schulz
-1 siblings, 0 replies; 8+ messages in thread
From: Quentin Schulz @ 2025-09-18 10:39 UTC (permalink / raw)
To: Chaoyi Chen, Heiko Stuebner, Andy Yan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Dragan Simic,
FUKAUMI Naoki, Jonas Karlman, Peter Robinson, Chaoyi Chen,
Geert Uytterhoeven, Cristian Ciocaltea, Sebastian Reichel,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
Hi Chaoyi Chen,
On 9/18/25 8:28 AM, Chaoyi Chen wrote:
> From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
>
> The rk3588 evb2 board has a full size DisplayPort connector, enable
> for it.
>
> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
> ---
>
> Changes in v2:
>
> - Link to V1: https://lore.kernel.org/all/20250916080802.125-1-kernel@airkyi.com/
> - Fix invalid DP connector type
> - Add more comment about dclk_vp2 parent clock
>
> .../boot/dts/rockchip/rk3588-evb2-v10.dts | 48 +++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
> index 91fe810d38d8..60ba6ac55b23 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
> @@ -25,6 +25,18 @@ chosen {
> stdout-path = "serial2:1500000n8";
> };
>
> + dp-con {
> + compatible = "dp-connector";
> + label = "DP OUT";
> + type = "full-size";
> +
> + port {
> + dp_con_in: endpoint {
> + remote-endpoint = <&dp0_out_con>;
> + };
> + };
> + };
> +
> hdmi-con {
> compatible = "hdmi-connector";
> type = "a";
> @@ -106,6 +118,24 @@ vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
> };
> };
>
> +&dp0 {
> + pinctrl-0 = <&dp0m0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&dp0_in {
> + dp0_in_vp2: endpoint {
> + remote-endpoint = <&vp2_out_dp0>;
> + };
> +};
> +
> +&dp0_out {
> + dp0_out_con: endpoint {
> + remote-endpoint = <&dp_con_in>;
> + };
> +};
> +
> &gpu {
> mali-supply = <&vdd_gpu_s0>;
> sram-supply = <&vdd_gpu_mem_s0>;
> @@ -916,6 +946,17 @@ &usb_host1_xhci {
> };
>
> &vop {
> + /*
> + * If no dedicated PLL was specified, the GPLL would be automatically
> + * assigned as the PLL source for dclk_vop2. As the frequency of GPLL
> + * is 1188 MHz, we can only get typical clock frequencies such as
> + * 74.25MHz, 148.5MHz, 297MHz, 594MHz.
> + *
> + * So here we set the parent clock of VP2 to V0PLL so that we can get
> + * any frequency.
> + */
> + assigned-clocks = <&cru DCLK_VOP2_SRC>;
> + assigned-clock-parents = <&cru PLL_V0PLL>;
Are those board-specific? Considering the VOP and DP/HDMI/...
controllers/PHYs are all internal to the SoC, would it make sense to
have those specified in the SoC DTSI? I'm not familiar with the video
output stack so maybe it doesn't apply here or is a bad idea, so I'm not
actually asking for a change here, just asking a question :)
Cheers,
Quentin
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2
@ 2025-09-18 10:39 ` Quentin Schulz
0 siblings, 0 replies; 8+ messages in thread
From: Quentin Schulz @ 2025-09-18 10:39 UTC (permalink / raw)
To: Chaoyi Chen, Heiko Stuebner, Andy Yan
Cc: Rob Herring, Conor Dooley, Geert Uytterhoeven, Jonas Karlman,
linux-kernel, Sebastian Reichel, Chaoyi Chen, linux-rockchip,
devicetree, FUKAUMI Naoki, Peter Robinson, Krzysztof Kozlowski,
Dragan Simic, linux-arm-kernel
Hi Chaoyi Chen,
On 9/18/25 8:28 AM, Chaoyi Chen wrote:
> From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
>
> The rk3588 evb2 board has a full size DisplayPort connector, enable
> for it.
>
> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
> ---
>
> Changes in v2:
>
> - Link to V1: https://lore.kernel.org/all/20250916080802.125-1-kernel@airkyi.com/
> - Fix invalid DP connector type
> - Add more comment about dclk_vp2 parent clock
>
> .../boot/dts/rockchip/rk3588-evb2-v10.dts | 48 +++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
> index 91fe810d38d8..60ba6ac55b23 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
> @@ -25,6 +25,18 @@ chosen {
> stdout-path = "serial2:1500000n8";
> };
>
> + dp-con {
> + compatible = "dp-connector";
> + label = "DP OUT";
> + type = "full-size";
> +
> + port {
> + dp_con_in: endpoint {
> + remote-endpoint = <&dp0_out_con>;
> + };
> + };
> + };
> +
> hdmi-con {
> compatible = "hdmi-connector";
> type = "a";
> @@ -106,6 +118,24 @@ vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
> };
> };
>
> +&dp0 {
> + pinctrl-0 = <&dp0m0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&dp0_in {
> + dp0_in_vp2: endpoint {
> + remote-endpoint = <&vp2_out_dp0>;
> + };
> +};
> +
> +&dp0_out {
> + dp0_out_con: endpoint {
> + remote-endpoint = <&dp_con_in>;
> + };
> +};
> +
> &gpu {
> mali-supply = <&vdd_gpu_s0>;
> sram-supply = <&vdd_gpu_mem_s0>;
> @@ -916,6 +946,17 @@ &usb_host1_xhci {
> };
>
> &vop {
> + /*
> + * If no dedicated PLL was specified, the GPLL would be automatically
> + * assigned as the PLL source for dclk_vop2. As the frequency of GPLL
> + * is 1188 MHz, we can only get typical clock frequencies such as
> + * 74.25MHz, 148.5MHz, 297MHz, 594MHz.
> + *
> + * So here we set the parent clock of VP2 to V0PLL so that we can get
> + * any frequency.
> + */
> + assigned-clocks = <&cru DCLK_VOP2_SRC>;
> + assigned-clock-parents = <&cru PLL_V0PLL>;
Are those board-specific? Considering the VOP and DP/HDMI/...
controllers/PHYs are all internal to the SoC, would it make sense to
have those specified in the SoC DTSI? I'm not familiar with the video
output stack so maybe it doesn't apply here or is a bad idea, so I'm not
actually asking for a change here, just asking a question :)
Cheers,
Quentin
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2
2025-09-18 10:39 ` Quentin Schulz
@ 2025-09-18 11:28 ` Chaoyi Chen
-1 siblings, 0 replies; 8+ messages in thread
From: Chaoyi Chen @ 2025-09-18 11:28 UTC (permalink / raw)
To: Quentin Schulz, Chaoyi Chen, Heiko Stuebner, Andy Yan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Dragan Simic,
FUKAUMI Naoki, Jonas Karlman, Peter Robinson, Geert Uytterhoeven,
Cristian Ciocaltea, Sebastian Reichel, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Hi Quentin,
On 9/18/2025 6:39 PM, Quentin Schulz wrote:
> Hi Chaoyi Chen,
>
> On 9/18/25 8:28 AM, Chaoyi Chen wrote:
>> From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
>>
>> The rk3588 evb2 board has a full size DisplayPort connector, enable
>> for it.
>>
>> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
>> ---
>>
>> Changes in v2:
>>
>> - Link to V1: https://lore.kernel.org/all/20250916080802.125-1-kernel@airkyi.com/
>> - Fix invalid DP connector type
>> - Add more comment about dclk_vp2 parent clock
>>
>> .../boot/dts/rockchip/rk3588-evb2-v10.dts | 48 +++++++++++++++++++
>> 1 file changed, 48 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
>> index 91fe810d38d8..60ba6ac55b23 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
>> +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
>> @@ -25,6 +25,18 @@ chosen {
>> stdout-path = "serial2:1500000n8";
>> };
>> + dp-con {
>> + compatible = "dp-connector";
>> + label = "DP OUT";
>> + type = "full-size";
>> +
>> + port {
>> + dp_con_in: endpoint {
>> + remote-endpoint = <&dp0_out_con>;
>> + };
>> + };
>> + };
>> +
>> hdmi-con {
>> compatible = "hdmi-connector";
>> type = "a";
>> @@ -106,6 +118,24 @@ vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
>> };
>> };
>> +&dp0 {
>> + pinctrl-0 = <&dp0m0_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +};
>> +
>> +&dp0_in {
>> + dp0_in_vp2: endpoint {
>> + remote-endpoint = <&vp2_out_dp0>;
>> + };
>> +};
>> +
>> +&dp0_out {
>> + dp0_out_con: endpoint {
>> + remote-endpoint = <&dp_con_in>;
>> + };
>> +};
>> +
>> &gpu {
>> mali-supply = <&vdd_gpu_s0>;
>> sram-supply = <&vdd_gpu_mem_s0>;
>> @@ -916,6 +946,17 @@ &usb_host1_xhci {
>> };
>> &vop {
>> + /*
>> + * If no dedicated PLL was specified, the GPLL would be automatically
>> + * assigned as the PLL source for dclk_vop2. As the frequency of GPLL
>> + * is 1188 MHz, we can only get typical clock frequencies such as
>> + * 74.25MHz, 148.5MHz, 297MHz, 594MHz.
>> + *
>> + * So here we set the parent clock of VP2 to V0PLL so that we can get
>> + * any frequency.
>> + */
>> + assigned-clocks = <&cru DCLK_VOP2_SRC>;
>> + assigned-clock-parents = <&cru PLL_V0PLL>;
>
> Are those board-specific? Considering the VOP and DP/HDMI/... controllers/PHYs are all internal to the SoC, would it make sense to have those specified in the SoC DTSI? I'm not familiar with the video output stack so maybe it doesn't apply here or is a bad idea, so I'm not actually asking for a change here, just asking a question :)
Yep, they are board-specific. Because the V0PLL may be used for non-display applications.
>
> Cheers,
> Quentin
>
>
--
Best,
Chaoyi
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2
@ 2025-09-18 11:28 ` Chaoyi Chen
0 siblings, 0 replies; 8+ messages in thread
From: Chaoyi Chen @ 2025-09-18 11:28 UTC (permalink / raw)
To: Quentin Schulz, Chaoyi Chen, Heiko Stuebner, Andy Yan
Cc: Rob Herring, Conor Dooley, Geert Uytterhoeven, Jonas Karlman,
Sebastian Reichel, linux-kernel, linux-rockchip, devicetree,
FUKAUMI Naoki, Peter Robinson, Krzysztof Kozlowski, Dragan Simic,
linux-arm-kernel
Hi Quentin,
On 9/18/2025 6:39 PM, Quentin Schulz wrote:
> Hi Chaoyi Chen,
>
> On 9/18/25 8:28 AM, Chaoyi Chen wrote:
>> From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
>>
>> The rk3588 evb2 board has a full size DisplayPort connector, enable
>> for it.
>>
>> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
>> ---
>>
>> Changes in v2:
>>
>> - Link to V1: https://lore.kernel.org/all/20250916080802.125-1-kernel@airkyi.com/
>> - Fix invalid DP connector type
>> - Add more comment about dclk_vp2 parent clock
>>
>> .../boot/dts/rockchip/rk3588-evb2-v10.dts | 48 +++++++++++++++++++
>> 1 file changed, 48 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
>> index 91fe810d38d8..60ba6ac55b23 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
>> +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
>> @@ -25,6 +25,18 @@ chosen {
>> stdout-path = "serial2:1500000n8";
>> };
>> + dp-con {
>> + compatible = "dp-connector";
>> + label = "DP OUT";
>> + type = "full-size";
>> +
>> + port {
>> + dp_con_in: endpoint {
>> + remote-endpoint = <&dp0_out_con>;
>> + };
>> + };
>> + };
>> +
>> hdmi-con {
>> compatible = "hdmi-connector";
>> type = "a";
>> @@ -106,6 +118,24 @@ vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
>> };
>> };
>> +&dp0 {
>> + pinctrl-0 = <&dp0m0_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +};
>> +
>> +&dp0_in {
>> + dp0_in_vp2: endpoint {
>> + remote-endpoint = <&vp2_out_dp0>;
>> + };
>> +};
>> +
>> +&dp0_out {
>> + dp0_out_con: endpoint {
>> + remote-endpoint = <&dp_con_in>;
>> + };
>> +};
>> +
>> &gpu {
>> mali-supply = <&vdd_gpu_s0>;
>> sram-supply = <&vdd_gpu_mem_s0>;
>> @@ -916,6 +946,17 @@ &usb_host1_xhci {
>> };
>> &vop {
>> + /*
>> + * If no dedicated PLL was specified, the GPLL would be automatically
>> + * assigned as the PLL source for dclk_vop2. As the frequency of GPLL
>> + * is 1188 MHz, we can only get typical clock frequencies such as
>> + * 74.25MHz, 148.5MHz, 297MHz, 594MHz.
>> + *
>> + * So here we set the parent clock of VP2 to V0PLL so that we can get
>> + * any frequency.
>> + */
>> + assigned-clocks = <&cru DCLK_VOP2_SRC>;
>> + assigned-clock-parents = <&cru PLL_V0PLL>;
>
> Are those board-specific? Considering the VOP and DP/HDMI/... controllers/PHYs are all internal to the SoC, would it make sense to have those specified in the SoC DTSI? I'm not familiar with the video output stack so maybe it doesn't apply here or is a bad idea, so I'm not actually asking for a change here, just asking a question :)
Yep, they are board-specific. Because the V0PLL may be used for non-display applications.
>
> Cheers,
> Quentin
>
>
--
Best,
Chaoyi
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2
2025-09-18 6:28 ` Chaoyi Chen
@ 2025-10-14 18:06 ` Heiko Stuebner
-1 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2025-10-14 18:06 UTC (permalink / raw)
To: Andy Yan, Chaoyi Chen
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Quentin Schulz, Dragan Simic, FUKAUMI Naoki, Jonas Karlman,
Peter Robinson, Chaoyi Chen, Geert Uytterhoeven,
Cristian Ciocaltea, Sebastian Reichel, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
On Thu, 18 Sep 2025 14:28:25 +0800, Chaoyi Chen wrote:
> The rk3588 evb2 board has a full size DisplayPort connector, enable
> for it.
>
>
Applied, thanks!
[1/1] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2
commit: 134fae98cfbabb7e90b1b2d957fb374408061034
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2
@ 2025-10-14 18:06 ` Heiko Stuebner
0 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2025-10-14 18:06 UTC (permalink / raw)
To: Andy Yan, Chaoyi Chen
Cc: Rob Herring, Conor Dooley, linux-kernel, Heiko Stuebner,
Geert Uytterhoeven, Jonas Karlman, Quentin Schulz,
Sebastian Reichel, Chaoyi Chen, linux-rockchip, devicetree,
FUKAUMI Naoki, Peter Robinson, Krzysztof Kozlowski, Dragan Simic,
linux-arm-kernel
On Thu, 18 Sep 2025 14:28:25 +0800, Chaoyi Chen wrote:
> The rk3588 evb2 board has a full size DisplayPort connector, enable
> for it.
>
>
Applied, thanks!
[1/1] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2
commit: 134fae98cfbabb7e90b1b2d957fb374408061034
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-10-14 18:07 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-18 6:28 [PATCH v2] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2 Chaoyi Chen
2025-09-18 6:28 ` Chaoyi Chen
2025-09-18 10:39 ` Quentin Schulz
2025-09-18 10:39 ` Quentin Schulz
2025-09-18 11:28 ` Chaoyi Chen
2025-09-18 11:28 ` Chaoyi Chen
2025-10-14 18:06 ` Heiko Stuebner
2025-10-14 18:06 ` Heiko Stuebner
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