* [PATCH v4 5/5] arm64: dts: renesas: R8A78000: Add initial Ironhide support
2025-09-17 5:29 [PATCH v4 0/5] arm64: add R8A78000 support Kuninori Morimoto
@ 2025-09-17 5:31 ` Kuninori Morimoto
2025-09-17 14:58 ` Geert Uytterhoeven
0 siblings, 1 reply; 3+ messages in thread
From: Kuninori Morimoto @ 2025-09-17 5:31 UTC (permalink / raw)
To: Liang, Kan, Adrian Hunter, Alexander Shishkin,
Arnaldo Carvalho de Melo, Catalin Marinas, Conor Dooley,
Douglas Anderson, Geert Uytterhoeven, Ian Rogers, Ingo Molnar,
James Clark, Jiri Olsa, John Garry, Krzysztof Kozlowski, Leo Yan,
Lorenzo Pieralisi, Mark Rutland, Mike Leach, Namhyung Kim,
Oliver Upton, Peter Zijlstra, Rob Herring, Shameer Kolothum,
Will Deacon, devicetree, linux-arm-kernel, linux-perf-users,
linux-renesas-soc, Marc Zyngier
From: Hai Pham <hai.pham.ud@renesas.com>
Add the initial support for Renesas X5H Ironhide board.
Note: It is using "maxcpus" in bootargs to limit number of CPU, because
SMP support is now under development. This limitation will be removed
in the future.
[Kuninori: tidyup for upstreaming]
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
arch/arm64/boot/dts/renesas/Makefile | 2 +
.../boot/dts/renesas/r8a78000-ironhide.dts | 92 +++++++++++++++++++
2 files changed, 94 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index ccdf7aaeca13e..dde046a3f25c8 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -136,6 +136,8 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
r8a779m5-salvator-xs-panel-aa104xd12-dtbs := r8a779m5-salvator-xs.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs-panel-aa104xd12.dtb
+dtb-$(CONFIG_ARCH_R8A78000) += r8a78000-ironhide.dtb
+
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
new file mode 100644
index 0000000000000..29b7180cabbcd
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the Ironhide board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a78000.dtsi"
+
+/ {
+ model = "Renesas Ironhide board based on r8a78000";
+ compatible = "renesas,ironhide", "renesas,r8a78000";
+
+ aliases {
+ serial0 = &hscif0;
+ };
+
+ chosen {
+ /*
+ * REMOVE-ME
+ *
+ * It works 1 CPU core only for now. This limitation will be
+ * removed in future.
+ */
+ bootargs = "maxcpus=1";
+ stdout-path = "serial0:1843200n8";
+ };
+
+ memory@60600000 {
+ device_type = "memory";
+ /* first 518MiB is reserved for other purposes. */
+ reg = <0x0 0x60600000 0x0 0x5fa00000>;
+ };
+
+ memory@1080000000 {
+ device_type = "memory";
+ reg = <0x10 0x80000000 0x0 0x80000000>;
+ };
+
+ memory@1200000000 {
+ device_type = "memory";
+ reg = <0x12 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1400000000 {
+ device_type = "memory";
+ reg = <0x14 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1600000000 {
+ device_type = "memory";
+ reg = <0x16 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1800000000 {
+ device_type = "memory";
+ reg = <0x18 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1a00000000 {
+ device_type = "memory";
+ reg = <0x1a 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1c00000000 {
+ device_type = "memory";
+ reg = <0x1c 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1e00000000 {
+ device_type = "memory";
+ reg = <0x1e 0x00000000 0x1 0x00000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <16666600>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&hscif0 {
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <26000000>;
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v4 5/5] arm64: dts: renesas: R8A78000: Add initial Ironhide support
2025-09-17 5:31 ` [PATCH v4 5/5] arm64: dts: renesas: R8A78000: Add initial Ironhide support Kuninori Morimoto
@ 2025-09-17 14:58 ` Geert Uytterhoeven
0 siblings, 0 replies; 3+ messages in thread
From: Geert Uytterhoeven @ 2025-09-17 14:58 UTC (permalink / raw)
To: Kuninori Morimoto
Cc: Liang, Kan, Adrian Hunter, Alexander Shishkin,
Arnaldo Carvalho de Melo, Catalin Marinas, Conor Dooley,
Douglas Anderson, Ian Rogers, Ingo Molnar, James Clark, Jiri Olsa,
John Garry, Krzysztof Kozlowski, Leo Yan, Lorenzo Pieralisi,
Mark Rutland, Mike Leach, Namhyung Kim, Oliver Upton,
Peter Zijlstra, Rob Herring, Shameer Kolothum, Will Deacon,
devicetree, linux-arm-kernel, linux-perf-users, linux-renesas-soc,
Marc Zyngier
Hi Morimoto-san,
On Wed, 17 Sept 2025 at 07:31, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Hai Pham <hai.pham.ud@renesas.com>
>
> Add the initial support for Renesas X5H Ironhide board.
>
> Note: It is using "maxcpus" in bootargs to limit number of CPU, because
> SMP support is now under development. This limitation will be removed
> in the future.
>
> [Kuninori: tidyup for upstreaming]
>
> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
> Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
> Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for the update!
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the Ironhide board
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +#include "r8a78000.dtsi"
> +
> +/ {
> + model = "Renesas Ironhide board based on r8a78000";
> + compatible = "renesas,ironhide", "renesas,r8a78000";
> +
> + aliases {
> + serial0 = &hscif0;
> + };
> +
> + chosen {
> + /*
> + * REMOVE-ME
> + *
> + * It works 1 CPU core only for now. This limitation will be
> + * removed in future.
> + */
> + bootargs = "maxcpus=1";
I still don't fully understand why this is needed: without that line,
Ironhide boots fine, and only a single CPU is enabled.
None of the cpu node have an enable-method, so Linux does not try to
enable secondary CPUs anyway. Even with the enable-method re-added
(like in your v2), Linux cannot enable secondary CPUs, as there is no
PSCI node.
What am I missing?
> + stdout-path = "serial0:1843200n8";
> + };
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v4 5/5] arm64: dts: renesas: R8A78000: Add initial Ironhide support
@ 2025-09-20 2:19 kernel test robot
0 siblings, 0 replies; 3+ messages in thread
From: kernel test robot @ 2025-09-20 2:19 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
::::::
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <875xdhabml.wl-kuninori.morimoto.gx@renesas.com>
References: <875xdhabml.wl-kuninori.morimoto.gx@renesas.com>
TO: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Hi Kuninori,
kernel test robot noticed the following build warnings:
[auto build test WARNING on arm64/for-next/core]
[also build test WARNING on geert-renesas-devel/next linus/master v6.17-rc6]
[cannot apply to acme/perf/core next-20250919]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Kuninori-Morimoto/arm64-cputype-Add-Cortex-A725AE-definitions/20250917-173332
base: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
patch link: https://lore.kernel.org/r/875xdhabml.wl-kuninori.morimoto.gx%40renesas.com
patch subject: [PATCH v4 5/5] arm64: dts: renesas: R8A78000: Add initial Ironhide support
:::::: branch date: 3 days ago
:::::: commit date: 3 days ago
config: arm64-randconfig-051-20250920 (https://download.01.org/0day-ci/archive/20250920/202509201014.po1DWWws-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 7c861bcedf61607b6c087380ac711eb7ff918ca6)
dtschema version: 2025.9.dev1+g4b28bc79f
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250920/202509201014.po1DWWws-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202509201014.po1DWWws-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
arch/arm64/boot/dts/renesas/r8a78000.dtsi:649.9-657.5: Warning (simple_bus_reg): /soc/timer: missing or empty reg/ranges property
>> arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: /: failed to match any schema with compatible: ['renesas,ironhide', 'renesas,r8a78000']
>> arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: /: failed to match any schema with compatible: ['renesas,ironhide', 'renesas,r8a78000']
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: /cpus/cpu@0: failed to match any schema with compatible: ['arm,cortex-a720ae']
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: cache-controller (cache): 'cache-unified' is a required property
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: /cpus/cpu@100: failed to match any schema with compatible: ['arm,cortex-a720ae']
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: cache-controller (cache): 'cache-unified' is a required property
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: /cpus/cpu@200: failed to match any schema with compatible: ['arm,cortex-a720ae']
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: cache-controller (cache): 'cache-unified' is a required property
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: /cpus/cpu@300: failed to match any schema with compatible: ['arm,cortex-a720ae']
--
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: /cpus/cpu@70100: failed to match any schema with compatible: ['arm,cortex-a720ae']
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: cache-controller (cache): 'cache-unified' is a required property
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: /cpus/cpu@70200: failed to match any schema with compatible: ['arm,cortex-a720ae']
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: cache-controller (cache): 'cache-unified' is a required property
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: /cpus/cpu@70300: failed to match any schema with compatible: ['arm,cortex-a720ae']
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: cache-controller (cache): 'cache-unified' is a required property
from schema $id: http://devicetree.org/schemas/cache.yaml#
>> arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: soc (simple-bus): timer: 'ranges' is a required property
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dtb: serial@c0700000 (renesas,scif-r8a78000): compatible: 'oneOf' conditional failed, one must be fixed:
['renesas,scif-r8a78000', 'renesas,scif'] is too long
['renesas,scif-r8a78000', 'renesas,scif'] is too short
'renesas,scif-r8a78000' is not one of ['renesas,scif-r7s72100']
'renesas,scif-r8a78000' is not one of ['renesas,scif-r7s9210']
'renesas,scif-r8a78000' is not one of ['renesas,scif-r8a7778', 'renesas,scif-r8a7779']
'renesas,scif-r8a78000' is not one of ['renesas,scif-r8a7742', 'renesas,scif-r8a7743', 'renesas,scif-r8a7744', 'renesas,scif-r8a7745', 'renesas,scif-r8a77470', 'renesas,scif-r8a7790', 'renesas,scif-r8a7791', 'renesas,scif-r8a7792', 'renesas,scif-r8a7793', 'renesas,scif-r8a7794']
'renesas,scif-r8a78000' is not one of ['renesas,scif-r8a774a1', 'renesas,scif-r8a774a3', 'renesas,scif-r8a774b1', 'renesas,scif-r8a774c0', 'renesas,scif-r8a774e1', 'renesas,scif-r8a7795', 'renesas,scif-r8a7796', 'renesas,scif-r8a77961', 'renesas,scif-r8a77965', 'renesas,scif-r8a77970', 'renesas,scif-r8a77980', 'renesas,scif-r8a77990', 'renesas,scif-r8a77995']
'renesas,scif-r8a78000' is not one of ['renesas,scif-r8a779a0', 'renesas,scif-r8a779f0', 'renesas,scif-r8a779g0', 'renesas,scif-r8a779h0']
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-09-17 5:29 [PATCH v4 0/5] arm64: add R8A78000 support Kuninori Morimoto
2025-09-17 5:31 ` [PATCH v4 5/5] arm64: dts: renesas: R8A78000: Add initial Ironhide support Kuninori Morimoto
2025-09-17 14:58 ` Geert Uytterhoeven
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