Re: [PATCH 6/9] drm/rcar-du: dsi: Respect DSI mode flags

[Laurent Pinchart <laurent.pinchart@ideasonboard.com>]

Hi Marek,

Thank you for the patch.

On Mon, Sep 22, 2025 at 08:55:02PM +0200, Marek Vasut wrote:
> Cache DSI mode flags in new mode_flags member of struct rcar_mipi_dsi .
> Configure TXVMSETR register based on the content of DSI mode flags in
> case the controller operates in video mode.
> 
> Rename TXVMSETR_H..BPEN_EN to TXVMSETR_H..BPEN and drop TXVMSETR_H..BPEN_DIS
> which resolves to 0. Update TXVMSETR_VSEN in the same manner. Replace
> TXVMSETR_SYNSEQ_PULSES with a code comment next to TXVMSETR_SYNSEQ_EVENTS
> because TXVMSETR_SYNSEQ_PULSES resolves to 0.
> 
> Do not convert bits and bitfields to BIT() and GENMASK() yet, to be
> consisten with the current style. Conversion to BIT() and GENMASK()
> macros is done at the very end of this series in the last two patches.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

> ---
> Cc: David Airlie <airlied@gmail.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Simona Vetter <simona@ffwll.ch>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
>  .../gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c    | 18 +++++++++++++++---
>  .../drm/renesas/rcar-du/rcar_mipi_dsi_regs.h   | 15 +++++----------
>  2 files changed, 20 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
> index 1591837ff472c..36bd9de61ce05 100644
> --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
> @@ -71,6 +71,7 @@ struct rcar_mipi_dsi {
>  	} clocks;
>  
>  	enum mipi_dsi_pixel_format format;
> +	unsigned long mode_flags;
>  	unsigned int num_data_lanes;
>  	unsigned int lanes;
>  };
> @@ -473,9 +474,19 @@ static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi,
>  	}
>  
>  	/* Configuration for Blanking sequence and Input Pixel */
> -	setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN
> -	     | TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES
> -	     | TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
> +	setr = TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
> +
> +	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
> +		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
> +			setr |= TXVMSETR_SYNSEQ_EVENTS;
> +		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP))
> +			setr |= TXVMSETR_HFPBPEN;
> +		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP))
> +			setr |= TXVMSETR_HBPBPEN;
> +		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA))
> +			setr |= TXVMSETR_HSABPEN;
> +	}
> +
>  	rcar_mipi_dsi_write(dsi, TXVMSETR, setr);
>  
>  	/* Configuration for Video Parameters */
> @@ -916,6 +927,7 @@ static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host,
>  
>  	dsi->lanes = device->lanes;
>  	dsi->format = device->format;
> +	dsi->mode_flags = device->mode_flags;
>  
>  	dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
>  						  1, 0);
> diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
> index 1a8d377ea85fc..99a88ea35aacd 100644
> --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
> @@ -140,18 +140,13 @@
>   * Video Mode Register
>   */
>  #define TXVMSETR			0x180
> -#define TXVMSETR_SYNSEQ_PULSES		(0 << 16)
> -#define TXVMSETR_SYNSEQ_EVENTS		(1 << 16)
> +#define TXVMSETR_SYNSEQ_EVENTS		(1 << 16) /* 0:Pulses 1:Events */
>  #define TXVMSETR_VSTPM			(1 << 15)
>  #define TXVMSETR_PIXWDTH		(1 << 8)
> -#define TXVMSETR_VSEN_EN		(1 << 4)
> -#define TXVMSETR_VSEN_DIS		(0 << 4)
> -#define TXVMSETR_HFPBPEN_EN		(1 << 2)
> -#define TXVMSETR_HFPBPEN_DIS		(0 << 2)
> -#define TXVMSETR_HBPBPEN_EN		(1 << 1)
> -#define TXVMSETR_HBPBPEN_DIS		(0 << 1)
> -#define TXVMSETR_HSABPEN_EN		(1 << 0)
> -#define TXVMSETR_HSABPEN_DIS		(0 << 0)
> +#define TXVMSETR_VSEN			(1 << 4)
> +#define TXVMSETR_HFPBPEN		(1 << 2)
> +#define TXVMSETR_HBPBPEN		(1 << 1)
> +#define TXVMSETR_HSABPEN		(1 << 0)
>  
>  #define TXVMCR				0x190
>  #define TXVMCR_VFCLR			(1 << 12)

-- 
Regards,

Laurent Pinchart