Re: [PATCH 1/2] x86/amd_node: Fix AMD root device caching

[Yazen Ghannam <yazen.ghannam@amd.com>]

On Tue, Sep 30, 2025 at 01:07:47PM -0500, Mario Limonciello (AMD) (kernel.org) wrote:
> 
> 
> On 9/30/2025 11:45 AM, Yazen Ghannam wrote:
> > Recent AMD node rework removed the "search and count" method of caching
> > AMD root devices. This depended on the value from a Data Fabric register
> > that was expected to hold the PCI bus of one of the root devices
> > attached to that fabric.
> > 
> > However, this expectation is incorrect. The register, when read from PCI
> > config space, returns the bitwise-OR of the buses of all attached root
> > devices.
> > 
> > This behavior is benign on AMD reference design boards, since the bus
> > numbers are aligned. This results in a bitwise-OR value matching one of
> > the buses. For example, 0x00 | 0x40 | 0xA0 | 0xE0 = 0xE0.
> > 
> > This behavior breaks on boards where the bus numbers are not exactly
> > aligned. For example, 0x00 | 0x07 | 0xE0 | 0x15 = 0x1F.
> > 
> > The bus numbering style in the reference boards is not a requirement.
> > The numbering found in other boards is not incorrect. Therefore, the
> > root device caching method needs to be adjusted.
> > 
> > Go back to the "search and count" method used before the recent rework.
> > Search for root devices using PCI class code rather than fixed PCI IDs.
> > 
> > This keeps the goal of the rework (remove dependency on PCI IDs) while
> > being able to support various board designs.
> > 
> > Fixes: 40a5f6ffdfc8 ("x86/amd_nb: Simplify root device search")
> 
> Was this a publicly reported failure?
> 
> If so is there a link to LKML or a Bugzilla with the details of the failure
> you can include here?
> 

No, it was reported off-list.

Thanks,
Yazen