Re: [PATCH 1/2] x86/amd_node: Fix AMD root device caching

[Yazen Ghannam <yazen.ghannam@amd.com>]

On Tue, Oct 21, 2025 at 02:29:09PM +0200, Borislav Petkov wrote:
> On Tue, Sep 30, 2025 at 04:45:45PM +0000, Yazen Ghannam wrote:
> > Recent AMD node rework removed the "search and count" method of caching
> > AMD root devices. This depended on the value from a Data Fabric register
> > that was expected to hold the PCI bus of one of the root devices
> > attached to that fabric.
> > 
> > However, this expectation is incorrect. The register, when read from PCI
> > config space, returns the bitwise-OR of the buses of all attached root
> > devices.
> > 
> > This behavior is benign on AMD reference design boards, since the bus
> > numbers are aligned. This results in a bitwise-OR value matching one of
> > the buses. For example, 0x00 | 0x40 | 0xA0 | 0xE0 = 0xE0.
> > 
> > This behavior breaks on boards where the bus numbers are not exactly
> > aligned. For example, 0x00 | 0x07 | 0xE0 | 0x15 = 0x1F.
> 
> Do I see it correctly that one of the root device's PCI bus is always 0x0 so
> you can simply read that one and you can keep the current code?
> 

It's correct that one of the root devices will be on bus 0x0. But that
device will be part of AMD node 0. So we still need to pick a root
device for the other, if any, AMD nodes in the system.

For example, a system with 2 AMD nodes could have this:
Node 0 : 0x00 0x07 0x0e 0x15
Node 1 : 0x1c 0x23 0x2a 0x31

Thanks,
Yazen