[PATCH v6] ASoC: wm8978: add missing BCLK divider setup

[PATCH v6] ASoC: wm8978: add missing BCLK divider setup

[Brian Sune]

In previous WM8978 codec driver versions, wm8978_set_dai_clkdiv
might not have been called for BCLK, leaving the bit clock
divider unconfigured. This could cause incorrect or unstable audio
clocks depending on sample rate and word length.

This patch adds a check in wm8978_hw_params: if the BCLK divider
has not been set via wm8978_set_dai_clkdiv, it is dynamically
calculated and configured at runtime.
This ensures that BCLK is always correctly set, whether the
machine driver configures it explicitly or not.

Whatever relieved from hell~

Signed-off-by: Brian Sune <briansune@gmail.com>
---
 sound/soc/codecs/wm8978.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c
index 8c45ba6fc4c3..23e6b874180b 100644
--- a/sound/soc/codecs/wm8978.c
+++ b/sound/soc/codecs/wm8978.c
@@ -99,6 +99,7 @@ struct wm8978_priv {
 	unsigned int f_mclk;
 	unsigned int f_256fs;
 	unsigned int f_opclk;
+	bool bclk_set;
 	int mclk_idx;
 	enum wm8978_sysclk_src sysclk;
 };
@@ -590,6 +591,7 @@ static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 	case WM8978_BCLKDIV:
 		if (div & ~0x1c)
 			return -EINVAL;
+		wm8978->bclk_set = true;
 		snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x1c, div);
 		break;
 	default:
@@ -717,6 +719,11 @@ static int wm8978_hw_params(struct snd_pcm_substream *substream,
 			    struct snd_pcm_hw_params *params,
 			    struct snd_soc_dai *dai)
 {
+	unsigned int bclk, bclkdiv = 0;
+	unsigned int target_bclk = params_rate(params) * params_width(params) * 2;
+	/* WM8978 supports divisors */
+	static const int bclk_divs[] = {1, 2, 4, 8, 16, 32};
+
 	struct snd_soc_component *component = dai->component;
 	struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
 	/* Word length mask = 0x60 */
@@ -820,6 +827,24 @@ static int wm8978_hw_params(struct snd_pcm_substream *substream,
 	/* MCLK divisor mask = 0xe0 */
 	snd_soc_component_update_bits(component, WM8978_CLOCKING, 0xe0, best << 5);
 
+	if (!wm8978->bclk_set) {
+		for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
+			bclk = wm8978->f_256fs / bclk_divs[i];
+
+			if (bclk < target_bclk)
+				break;
+
+			bclkdiv = i;
+		}
+
+		dev_dbg(component->dev, "%s: fs=%u width=%u -> target BCLK=%u, using div #%u\n",
+			__func__, params_rate(params), params_width(params), target_bclk,
+			bclk_divs[bclkdiv]);
+
+		/* BCLKDIV divisor mask = 0x1c */
+		snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x1c, bclkdiv << 2);
+	}
+
 	snd_soc_component_write(component, WM8978_AUDIO_INTERFACE, iface_ctl);
 	snd_soc_component_write(component, WM8978_ADDITIONAL_CONTROL, add_ctl);
 
-- 
2.47.1.windows.1

Re: [PATCH v6] ASoC: wm8978: add missing BCLK divider setup

[Charles Keepax]

On Thu, Oct 09, 2025 at 04:52:07AM +0800, Brian Sune wrote:
> In previous WM8978 codec driver versions, wm8978_set_dai_clkdiv
> might not have been called for BCLK, leaving the bit clock
> divider unconfigured. This could cause incorrect or unstable audio
> clocks depending on sample rate and word length.
> 
> This patch adds a check in wm8978_hw_params: if the BCLK divider
> has not been set via wm8978_set_dai_clkdiv, it is dynamically
> calculated and configured at runtime.
> This ensures that BCLK is always correctly set, whether the
> machine driver configures it explicitly or not.
> 
> Whatever relieved from hell~
> 
> Signed-off-by: Brian Sune <briansune@gmail.com>
> ---

Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>

Thanks,
Charles

Re: [PATCH v6] ASoC: wm8978: add missing BCLK divider setup

[Sune Brian]

Charles Keepax <ckeepax@opensource.cirrus.com> 於 2025年10月9日 週四 下午5:18寫道：

> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
>
> Thanks,
> Charles

Any documentations are required?
i.e. .rst file or similar?

Brian

Re: [PATCH v6] ASoC: wm8978: add missing BCLK divider setup

[Charles Keepax]

On Thu, Oct 09, 2025 at 11:02:57PM +0800, Sune Brian wrote:
> Charles Keepax <ckeepax@opensource.cirrus.com> 於 2025年10月9日 週四 下午5:18寫道：
> 
> > Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
> >
> > Thanks,
> > Charles
> 
> Any documentations are required?
> i.e. .rst file or similar?

No, no need here really. The codec itself doesn't have any docs
at the moment and its too specific for the more general docs. And
besides the change is mostly just bringing things more inline
with other similar devices.

Thanks,
Charles

Re: [PATCH v6] ASoC: wm8978: add missing BCLK divider setup

[Mark Brown]

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On Thu, Oct 09, 2025 at 11:02:57PM +0800, Sune Brian wrote:

> Any documentations are required?
> i.e. .rst file or similar?

No.

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Re: [PATCH v6] ASoC: wm8978: add missing BCLK divider setup

[Sune Brian]

Mark Brown <broonie@kernel.org> 於 2025年10月9日 週四 下午11:49寫道：

> No.

Routine confirmation.
As such, case closed on this patch.

Brian