From: Conor Dooley <conor@kernel.org>
To: Yunhui Cui <cuiyunhui@bytedance.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, rostedt@goodmis.org,
mhiramat@kernel.org, mark.rutland@arm.com, peterz@infradead.org,
jpoimboe@kernel.org, jbaron@akamai.com, ardb@kernel.org,
willy@infradead.org, guoren@kernel.org, ziy@nvidia.com,
akpm@linux-foundation.org, bjorn@rivosinc.com,
ajones@ventanamicro.com, parri.andrea@gmail.com,
cleger@rivosinc.com, yongxuan.wang@sifive.com,
inochiama@gmail.com, samuel.holland@sifive.com,
charlie@rivosinc.com, conor.dooley@microchip.com,
yikming2222@gmail.com, andybnac@gmail.com, yury.norov@gmail.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-trace-kernel@vger.kernel.org
Subject: Re: [PATCH RFC] riscv: add support for Ziccid
Date: Thu, 9 Oct 2025 17:53:14 +0100 [thread overview]
Message-ID: <20251009-secluded-writing-adefb1f71a72@spud> (raw)
In-Reply-To: <20251009134514.8549-1-cuiyunhui@bytedance.com>
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On Thu, Oct 09, 2025 at 09:45:14PM +0800, Yunhui Cui wrote:
> The Ziccid extension provides hardware synchronization between
> Dcache and Icache. With this hardware support, there's no longer
> a need to trigger remote hart execution of fence.i via IPI.
>
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
Actual correctness aside, in an RFC should you really state why this is
an RFC and not just a v1 patch. You're missing a dt-binding change
that's required for new extensions, that you'll need for v2.
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 67b59699357da..2da82aa2dbf0a 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -540,6 +540,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
> + __RISCV_ISA_EXT_DATA(ziccid, RISCV_ISA_EXT_ZICCID),
> };
The comment about this structure reads:
/*
* The canonical order of ISA extension names in the ISA string is defined in
* chapter 27 of the unprivileged specification.
*
* Ordinarily, for in-kernel data structures, this order is unimportant but
* isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
*
* The specification uses vague wording, such as should, when it comes to
* ordering, so for our purposes the following rules apply:
*
* 1. All multi-letter extensions must be separated from other extensions by an
* underscore.
*
* 2. Additional standard extensions (starting with 'Z') must be sorted after
* single-letter extensions and before any higher-privileged extensions.
*
* 3. The first letter following the 'Z' conventionally indicates the most
* closely related alphabetical extension category, IMAFDQLCBKJTPVH.
* If multiple 'Z' extensions are named, they must be ordered first by
* category, then alphabetically within a category.
*
* 3. Standard supervisor-level extensions (starting with 'S') must be listed
* after standard unprivileged extensions. If multiple supervisor-level
* extensions are listed, they must be ordered alphabetically.
*
* 4. Standard machine-level extensions (starting with 'Zxm') must be listed
* after any lower-privileged, standard extensions. If multiple
* machine-level extensions are listed, they must be ordered
* alphabetically.
*
* 5. Non-standard extensions (starting with 'X') must be listed after all
* standard extensions. If multiple non-standard extensions are listed, they
* must be ordered alphabetically.
*
* An example string following the order is:
* rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
*
* New entries to this struct should follow the ordering rules described above.
*/
Cheers,
Conor.
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Yunhui Cui <cuiyunhui@bytedance.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, rostedt@goodmis.org,
mhiramat@kernel.org, mark.rutland@arm.com, peterz@infradead.org,
jpoimboe@kernel.org, jbaron@akamai.com, ardb@kernel.org,
willy@infradead.org, guoren@kernel.org, ziy@nvidia.com,
akpm@linux-foundation.org, bjorn@rivosinc.com,
ajones@ventanamicro.com, parri.andrea@gmail.com,
cleger@rivosinc.com, yongxuan.wang@sifive.com,
inochiama@gmail.com, samuel.holland@sifive.com,
charlie@rivosinc.com, conor.dooley@microchip.com,
yikming2222@gmail.com, andybnac@gmail.com, yury.norov@gmail.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-trace-kernel@vger.kernel.org
Subject: Re: [PATCH RFC] riscv: add support for Ziccid
Date: Thu, 9 Oct 2025 17:53:14 +0100 [thread overview]
Message-ID: <20251009-secluded-writing-adefb1f71a72@spud> (raw)
In-Reply-To: <20251009134514.8549-1-cuiyunhui@bytedance.com>
[-- Attachment #1: Type: text/plain, Size: 2943 bytes --]
On Thu, Oct 09, 2025 at 09:45:14PM +0800, Yunhui Cui wrote:
> The Ziccid extension provides hardware synchronization between
> Dcache and Icache. With this hardware support, there's no longer
> a need to trigger remote hart execution of fence.i via IPI.
>
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
Actual correctness aside, in an RFC should you really state why this is
an RFC and not just a v1 patch. You're missing a dt-binding change
that's required for new extensions, that you'll need for v2.
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 67b59699357da..2da82aa2dbf0a 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -540,6 +540,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
> + __RISCV_ISA_EXT_DATA(ziccid, RISCV_ISA_EXT_ZICCID),
> };
The comment about this structure reads:
/*
* The canonical order of ISA extension names in the ISA string is defined in
* chapter 27 of the unprivileged specification.
*
* Ordinarily, for in-kernel data structures, this order is unimportant but
* isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
*
* The specification uses vague wording, such as should, when it comes to
* ordering, so for our purposes the following rules apply:
*
* 1. All multi-letter extensions must be separated from other extensions by an
* underscore.
*
* 2. Additional standard extensions (starting with 'Z') must be sorted after
* single-letter extensions and before any higher-privileged extensions.
*
* 3. The first letter following the 'Z' conventionally indicates the most
* closely related alphabetical extension category, IMAFDQLCBKJTPVH.
* If multiple 'Z' extensions are named, they must be ordered first by
* category, then alphabetically within a category.
*
* 3. Standard supervisor-level extensions (starting with 'S') must be listed
* after standard unprivileged extensions. If multiple supervisor-level
* extensions are listed, they must be ordered alphabetically.
*
* 4. Standard machine-level extensions (starting with 'Zxm') must be listed
* after any lower-privileged, standard extensions. If multiple
* machine-level extensions are listed, they must be ordered
* alphabetically.
*
* 5. Non-standard extensions (starting with 'X') must be listed after all
* standard extensions. If multiple non-standard extensions are listed, they
* must be ordered alphabetically.
*
* An example string following the order is:
* rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
*
* New entries to this struct should follow the ordering rules described above.
*/
Cheers,
Conor.
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next prev parent reply other threads:[~2025-10-09 16:53 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-09 13:45 [PATCH RFC] riscv: add support for Ziccid Yunhui Cui
2025-10-09 13:45 ` Yunhui Cui
2025-10-09 16:45 ` Yao Zi
2025-10-09 16:45 ` Yao Zi
2025-10-16 9:24 ` [External] " yunhui cui
2025-10-16 9:24 ` yunhui cui
2025-10-09 16:53 ` Conor Dooley [this message]
2025-10-09 16:53 ` Conor Dooley
2025-10-10 17:48 ` Yury Norov
2025-10-10 17:48 ` Yury Norov
2025-10-12 11:23 ` Guo Ren
2025-10-12 11:23 ` Guo Ren
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