From: Xu Lu <luxu.kernel@bytedance.com>
To: corbet@lwn.net, paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, will@kernel.org,
peterz@infradead.org, boqun.feng@gmail.com, mark.rutland@arm.com,
anup@brainfault.org, atish.patra@linux.dev, pbonzini@redhat.com,
shuah@kernel.org, parri.andrea@gmail.com,
ajones@ventanamicro.com, brs@rivosinc.com, guoren@kernel.org
Cc: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org, apw@canonical.com,
joe@perches.com, lukas.bulwahn@gmail.com,
Xu Lu <luxu.kernel@bytedance.com>
Subject: [PATCH v4 00/10] riscv: Add Zalasr ISA extension support
Date: Mon, 20 Oct 2025 12:20:46 +0800 [thread overview]
Message-ID: <20251020042056.30283-1-luxu.kernel@bytedance.com> (raw)
This patch adds support for the Zalasr ISA extension, which supplies the
real load acquire/store release instructions.
The specification can be found here:
https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc
This patch seires has been tested with ltp on Qemu with Brensan's zalasr
support patch[1].
Some false positive spacing error happens during patch checking. Thus I
CCed maintainers of checkpatch.pl as well.
[1] https://lore.kernel.org/all/CAGPSXwJEdtqW=nx71oufZp64nK6tK=0rytVEcz4F-gfvCOXk2w@mail.gmail.com/
v4:
- Apply acquire/release semantics to arch_atomic operations. Thanks
to Andrea.
v3:
- Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations
so as to ensure FENCE.TSO ordering between operations which precede the
UNLOCK+LOCK sequence and operations which follow the sequence. Thanks
to Andrea.
- Support hwprobe of Zalasr.
- Allow Zalasr extensions for Guest/VM.
v2:
- Adjust the order of Zalasr and Zalrsc in dt-bindings. Thanks to
Conor.
Xu Lu (10):
riscv: Add ISA extension parsing for Zalasr
dt-bindings: riscv: Add Zalasr ISA extension description
riscv: hwprobe: Export Zalasr extension
riscv: Introduce Zalasr instructions
riscv: Apply Zalasr to smp_load_acquire/smp_store_release
riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg
operations
riscv: Apply acquire/release semantics to arch_atomic operations
riscv: Remove arch specific __atomic_acquire/release_fence
RISC-V: KVM: Allow Zalasr extensions for Guest/VM
RISC-V: KVM: selftests: Add Zalasr extensions to get-reg-list test
Documentation/arch/riscv/hwprobe.rst | 5 +-
.../devicetree/bindings/riscv/extensions.yaml | 5 +
arch/riscv/include/asm/atomic.h | 70 ++++++++-
arch/riscv/include/asm/barrier.h | 91 +++++++++--
arch/riscv/include/asm/cmpxchg.h | 144 +++++++++---------
arch/riscv/include/asm/fence.h | 4 -
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/insn-def.h | 79 ++++++++++
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
arch/riscv/kernel/sys_hwprobe.c | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 +
.../selftests/kvm/riscv/get-reg-list.c | 4 +
14 files changed, 314 insertions(+), 95 deletions(-)
--
2.20.1
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Xu Lu <luxu.kernel@bytedance.com>
To: corbet@lwn.net, paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, will@kernel.org,
peterz@infradead.org, boqun.feng@gmail.com, mark.rutland@arm.com,
anup@brainfault.org, atish.patra@linux.dev, pbonzini@redhat.com,
shuah@kernel.org, parri.andrea@gmail.com,
ajones@ventanamicro.com, brs@rivosinc.com, guoren@kernel.org
Cc: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org, apw@canonical.com,
joe@perches.com, lukas.bulwahn@gmail.com,
Xu Lu <luxu.kernel@bytedance.com>
Subject: [PATCH v4 00/10] riscv: Add Zalasr ISA extension support
Date: Mon, 20 Oct 2025 12:20:46 +0800 [thread overview]
Message-ID: <20251020042056.30283-1-luxu.kernel@bytedance.com> (raw)
This patch adds support for the Zalasr ISA extension, which supplies the
real load acquire/store release instructions.
The specification can be found here:
https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc
This patch seires has been tested with ltp on Qemu with Brensan's zalasr
support patch[1].
Some false positive spacing error happens during patch checking. Thus I
CCed maintainers of checkpatch.pl as well.
[1] https://lore.kernel.org/all/CAGPSXwJEdtqW=nx71oufZp64nK6tK=0rytVEcz4F-gfvCOXk2w@mail.gmail.com/
v4:
- Apply acquire/release semantics to arch_atomic operations. Thanks
to Andrea.
v3:
- Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations
so as to ensure FENCE.TSO ordering between operations which precede the
UNLOCK+LOCK sequence and operations which follow the sequence. Thanks
to Andrea.
- Support hwprobe of Zalasr.
- Allow Zalasr extensions for Guest/VM.
v2:
- Adjust the order of Zalasr and Zalrsc in dt-bindings. Thanks to
Conor.
Xu Lu (10):
riscv: Add ISA extension parsing for Zalasr
dt-bindings: riscv: Add Zalasr ISA extension description
riscv: hwprobe: Export Zalasr extension
riscv: Introduce Zalasr instructions
riscv: Apply Zalasr to smp_load_acquire/smp_store_release
riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg
operations
riscv: Apply acquire/release semantics to arch_atomic operations
riscv: Remove arch specific __atomic_acquire/release_fence
RISC-V: KVM: Allow Zalasr extensions for Guest/VM
RISC-V: KVM: selftests: Add Zalasr extensions to get-reg-list test
Documentation/arch/riscv/hwprobe.rst | 5 +-
.../devicetree/bindings/riscv/extensions.yaml | 5 +
arch/riscv/include/asm/atomic.h | 70 ++++++++-
arch/riscv/include/asm/barrier.h | 91 +++++++++--
arch/riscv/include/asm/cmpxchg.h | 144 +++++++++---------
arch/riscv/include/asm/fence.h | 4 -
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/insn-def.h | 79 ++++++++++
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
arch/riscv/kernel/sys_hwprobe.c | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 +
.../selftests/kvm/riscv/get-reg-list.c | 4 +
14 files changed, 314 insertions(+), 95 deletions(-)
--
2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Xu Lu <luxu.kernel@bytedance.com>
To: corbet@lwn.net, paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, will@kernel.org,
peterz@infradead.org, boqun.feng@gmail.com, mark.rutland@arm.com,
anup@brainfault.org, atish.patra@linux.dev, pbonzini@redhat.com,
shuah@kernel.org, parri.andrea@gmail.com,
ajones@ventanamicro.com, brs@rivosinc.com, guoren@kernel.org
Cc: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org, apw@canonical.com,
joe@perches.com, lukas.bulwahn@gmail.com,
Xu Lu <luxu.kernel@bytedance.com>
Subject: [PATCH v4 00/10] riscv: Add Zalasr ISA extension support
Date: Mon, 20 Oct 2025 12:20:46 +0800 [thread overview]
Message-ID: <20251020042056.30283-1-luxu.kernel@bytedance.com> (raw)
This patch adds support for the Zalasr ISA extension, which supplies the
real load acquire/store release instructions.
The specification can be found here:
https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc
This patch seires has been tested with ltp on Qemu with Brensan's zalasr
support patch[1].
Some false positive spacing error happens during patch checking. Thus I
CCed maintainers of checkpatch.pl as well.
[1] https://lore.kernel.org/all/CAGPSXwJEdtqW=nx71oufZp64nK6tK=0rytVEcz4F-gfvCOXk2w@mail.gmail.com/
v4:
- Apply acquire/release semantics to arch_atomic operations. Thanks
to Andrea.
v3:
- Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations
so as to ensure FENCE.TSO ordering between operations which precede the
UNLOCK+LOCK sequence and operations which follow the sequence. Thanks
to Andrea.
- Support hwprobe of Zalasr.
- Allow Zalasr extensions for Guest/VM.
v2:
- Adjust the order of Zalasr and Zalrsc in dt-bindings. Thanks to
Conor.
Xu Lu (10):
riscv: Add ISA extension parsing for Zalasr
dt-bindings: riscv: Add Zalasr ISA extension description
riscv: hwprobe: Export Zalasr extension
riscv: Introduce Zalasr instructions
riscv: Apply Zalasr to smp_load_acquire/smp_store_release
riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg
operations
riscv: Apply acquire/release semantics to arch_atomic operations
riscv: Remove arch specific __atomic_acquire/release_fence
RISC-V: KVM: Allow Zalasr extensions for Guest/VM
RISC-V: KVM: selftests: Add Zalasr extensions to get-reg-list test
Documentation/arch/riscv/hwprobe.rst | 5 +-
.../devicetree/bindings/riscv/extensions.yaml | 5 +
arch/riscv/include/asm/atomic.h | 70 ++++++++-
arch/riscv/include/asm/barrier.h | 91 +++++++++--
arch/riscv/include/asm/cmpxchg.h | 144 +++++++++---------
arch/riscv/include/asm/fence.h | 4 -
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/insn-def.h | 79 ++++++++++
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
arch/riscv/kernel/sys_hwprobe.c | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 +
.../selftests/kvm/riscv/get-reg-list.c | 4 +
14 files changed, 314 insertions(+), 95 deletions(-)
--
2.20.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2025-10-20 4:21 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-20 4:20 Xu Lu [this message]
2025-10-20 4:20 ` [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
2025-10-20 4:20 ` Xu Lu
2025-10-20 4:20 ` [PATCH v4 01/10] riscv: Add ISA extension parsing for Zalasr Xu Lu
2025-10-20 4:20 ` Xu Lu
2025-10-20 4:20 ` Xu Lu
2025-10-20 4:20 ` [PATCH v4 02/10] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
2025-10-20 4:20 ` Xu Lu
2025-10-20 4:20 ` Xu Lu
2025-10-20 17:21 ` Conor Dooley
2025-10-20 17:21 ` Conor Dooley
2025-10-20 17:21 ` Conor Dooley
2025-10-20 4:20 ` [PATCH v4 03/10] riscv: hwprobe: Export Zalasr extension Xu Lu
2025-10-20 4:20 ` Xu Lu
2025-10-20 4:20 ` Xu Lu
2025-10-20 13:46 ` Guo Ren
2025-10-20 13:46 ` Guo Ren
2025-10-20 13:46 ` Guo Ren
2025-10-20 4:20 ` [PATCH v4 04/10] riscv: Introduce Zalasr instructions Xu Lu
2025-10-20 4:20 ` Xu Lu
2025-10-20 4:20 ` Xu Lu
2025-10-20 13:34 ` Guo Ren
2025-10-20 13:34 ` Guo Ren
2025-10-20 13:34 ` Guo Ren
2025-10-20 4:34 ` [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
2025-10-20 4:34 ` Xu Lu
2025-10-20 4:34 ` Xu Lu
2025-10-24 21:47 ` Andrea Parri
2025-10-24 21:47 ` Andrea Parri
2025-10-24 21:47 ` Andrea Parri
2025-11-19 12:30 ` patchwork-bot+linux-riscv
2025-11-19 12:30 ` patchwork-bot+linux-riscv
2025-11-19 12:30 ` patchwork-bot+linux-riscv
2025-11-19 15:42 ` Paul Walmsley
2025-11-19 15:42 ` Paul Walmsley
2025-11-19 15:42 ` Paul Walmsley
2025-11-19 15:57 ` 路旭
2025-11-19 15:57 ` 路旭
2025-11-19 15:57 ` 路旭
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