All of lore.kernel.org
 help / color / mirror / Atom feed
From: Rob Herring <robh@kernel.org>
To: Ryan Chen <ryan_chen@aspeedtech.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
	Andrew Jeffery <andrew@codeconstruct.com.au>,
	jk@codeconstruct.com.au, Kevin Chen <kevin_chen@aspeedtech.com>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-aspeed@lists.ozlabs.org
Subject: Re: [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700: Add support for INTC hierarchy
Date: Wed, 22 Oct 2025 08:51:01 -0500	[thread overview]
Message-ID: <20251022135101.GA3349934-robh@kernel.org> (raw)
In-Reply-To: <20251022065507.1152071-2-ryan_chen@aspeedtech.com>

On Wed, Oct 22, 2025 at 02:55:05PM +0800, Ryan Chen wrote:
> AST2700 contains two-level interrupt controllers (INTC0 and INTC1),
> each with its own register space and handling different sets of
> peripherals.

This is a mess!

How does this relate to the existing "aspeed,ast2700-intc-ic"? Its 
schema has a block diagram of connections which I can understand. This 
does not.

The use of child nodes here is questionable. A variable number of 
interrupt banks is not a reason to have child nodes. I'm only guessing 
that's what's happening here because you haven't explained it.

> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  .../aspeed,ast2700-intc0.yaml                 | 97 +++++++++++++++++++
>  .../aspeed,ast2700-intc1.yaml                 | 94 ++++++++++++++++++
>  2 files changed, 191 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
> new file mode 100644
> index 000000000000..93a5b142b0a2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
> @@ -0,0 +1,97 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc0.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +maintainers:
> +  - Ryan Chen <ryan_chen@aspeedtech.com>
> +
> +title: ASPEED AST2700 Interrupt Controller 0
> +
> +description:
> +  This interrupt controller hardware is first level interrupt controller that
> +  is hooked to the GIC interrupt controller. It's useful to combine multiple
> +  interrupt sources into 1 interrupt to GIC interrupt controller.
> +
> +properties:
> +  compatible:
> +    const: aspeed,ast2700-intc0
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#address-cells':
> +    const: 1
> +
> +  '#size-cells':
> +    const: 1
> +
> +  ranges: true
> +
> +patternProperties:
> +  "^interrupt-controller@":
> +    type: object
> +    description: A child interrupt controller node
> +    additionalProperties: false
> +
> +    properties:
> +      compatible:
> +        enum:
> +          - aspeed,ast2700-intc0-ic
> +
> +      reg:
> +        maxItems: 1
> +
> +      '#interrupt-cells':
> +        const: 1
> +
> +      interrupt-controller: true
> +
> +      interrupts:
> +        minItems: 1
> +        maxItems: 10

What are the 10 different interrupts? You have to define what each one 
is.

> +
> +    required:
> +      - compatible
> +      - reg
> +      - interrupt-controller
> +      - '#interrupt-cells'
> +      - interrupts
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#address-cells'
> +  - '#size-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    intc0: interrupt-controller@12100000 {

This node is not an interrupt-controller.

> +        compatible = "aspeed,ast2700-intc0";
> +        reg = <0x12100000 0x4000>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges = <0x0 0x12100000 0x4000>;
> +
> +        intc0_11: interrupt-controller@1b00 {
> +            #interrupt-cells = <1>;
> +            interrupt-controller;
> +            compatible = "aspeed,ast2700-intc0-ic";
> +            reg = <0x1b00 0x10>;
> +            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
> +        };
> +    };
> \ No newline at end of file

Fix.

> diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml
> new file mode 100644
> index 000000000000..2f807d074211
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc1.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +maintainers:
> +  - Ryan Chen <ryan_chen@aspeedtech.com>
> +
> +title: ASPEED AST2700 Interrupt Controller 1
> +
> +description:
> +  This interrupt controller hardware is second level interrupt controller that
> +  is hooked to a parent interrupt controller. It's useful to combine multiple
> +  interrupt sources into 1 interrupt to parent interrupt controller.
> +
> +properties:
> +  compatible:
> +    const: aspeed,ast2700-intc1
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#address-cells':
> +    const: 1
> +
> +  '#size-cells':
> +    const: 1
> +
> +  ranges: true
> +
> +patternProperties:
> +  "^interrupt-controller@":
> +    type: object
> +    description: A child interrupt controller node
> +    additionalProperties: false
> +
> +    properties:
> +      compatible:
> +        enum:
> +          - aspeed,ast2700-intc1-ic
> +
> +      reg:
> +        maxItems: 1
> +
> +      '#interrupt-cells':
> +        const: 1
> +
> +      interrupt-controller: true
> +
> +      interrupts-extended:
> +        minItems: 1
> +        maxItems: 1
> +
> +    required:
> +      - compatible
> +      - reg
> +      - interrupt-controller
> +      - '#interrupt-cells'
> +      - interrupts-extended
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#address-cells'
> +  - '#size-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    intc1: interrupt-controller@14c18000 {
> +        compatible = "aspeed,ast2700-intc1";
> +        reg = <0x14c18000 0x400>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges = <0x0 0x14c18000 0x400>;
> +
> +        intc1_0: interrupt-controller@100 {
> +            compatible = "aspeed,ast2700-intc1-ic";
> +            reg = <0x100 0x10>;
> +            #interrupt-cells = <1>;
> +            interrupt-controller;
> +            interrupts-extended = <&intc0_11 0>;
> +        };
> +
> +        intc1_1: interrupt-controller@110 {
> +            compatible = "aspeed,ast2700-intc1-ic";
> +            reg = <0x110 0x10>;
> +            #interrupt-cells = <1>;
> +            interrupt-controller;
> +            interrupts-extended = <&intc0_11 1>;
> +        };
> +    };
> \ No newline at end of file
> -- 
> 2.34.1
> 


  parent reply	other threads:[~2025-10-22 13:51 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-22  6:55 [PATCH v5 0/3] AST2700 interrupt controller hierarchy support Ryan Chen
2025-10-22  6:55 ` [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700: Add support for INTC hierarchy Ryan Chen
2025-10-22  8:29   ` Rob Herring (Arm)
2025-10-22 13:51   ` Rob Herring [this message]
2025-10-23  6:57     ` Ryan Chen
2025-10-24 23:11       ` Rob Herring
2025-10-26  3:57         ` Ryan Chen
2025-10-22  6:55 ` [PATCH v5 2/3] Irqchip/ast2700-intc: add debugfs support for routing/protection display Ryan Chen
2025-10-22 16:37   ` Thomas Gleixner
2025-10-23  8:20     ` Ryan Chen
2025-10-22  6:55 ` [PATCH v5 3/3] irqchip: aspeed: add compatible strings for ast2700-intc0-ic and ast2700-intc1-ic Ryan Chen
2025-10-22 16:51   ` Thomas Gleixner
2025-10-23  8:29     ` Ryan Chen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20251022135101.GA3349934-robh@kernel.org \
    --to=robh@kernel.org \
    --cc=andrew@codeconstruct.com.au \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=jk@codeconstruct.com.au \
    --cc=joel@jms.id.au \
    --cc=kevin_chen@aspeedtech.com \
    --cc=krzk+dt@kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-aspeed@lists.ozlabs.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=ryan_chen@aspeedtech.com \
    --cc=tglx@linutronix.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.