Re: [PATCH v3 01/24] dt-bindings: phy: Add mediatek,mt8196-ufsphy variant

From: Conor Dooley <conor@kernel.org>
To: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Cc: Alim Akhtar <alim.akhtar@samsung.com>,
	Avri Altman <avri.altman@wdc.com>,
	Bart Van Assche <bvanassche@acm.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Chunfeng Yun <chunfeng.yun@mediatek.com>,
	Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Peter Wang <peter.wang@mediatek.com>,
	Stanley Jhu <chu.stanley@gmail.com>,
	"James E.J. Bottomley" <James.Bottomley@hansenpartnership.com>,
	"Martin K. Petersen" <martin.petersen@oracle.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Mark Brown <broonie@kernel.org>,
	Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>,
	kernel@collabora.com, linux-scsi@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org,
	linux-phy@lists.infradead.org
Subject: Re: [PATCH v3 01/24] dt-bindings: phy: Add mediatek,mt8196-ufsphy variant
Date: Fri, 24 Oct 2025 18:09:00 +0100	[thread overview]
Message-ID: <20251024-spilt-deviate-e3f6bfd3642c@spud> (raw)
In-Reply-To: <20251023-mt8196-ufs-v3-1-0f04b4a795ff@collabora.com>

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On Thu, Oct 23, 2025 at 09:49:19PM +0200, Nicolas Frattaroli wrote:
> The MediaTek MT8196 SoC includes an M-PHY compatible with the already
> existing mt8183 binding.
> 
> However, one omission from the original binding was that all of these
> variants may have an optional reset.
> 
> Add the new compatible, and also the resets property, with an example.
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

> ---
>  .../devicetree/bindings/phy/mediatek,ufs-phy.yaml        | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
> index 3e62b5d4da61..f414aaa18997 100644
> --- a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
> @@ -26,6 +26,7 @@ properties:
>        - items:
>            - enum:
>                - mediatek,mt8195-ufsphy
> +              - mediatek,mt8196-ufsphy
>            - const: mediatek,mt8183-ufsphy
>        - const: mediatek,mt8183-ufsphy
>  
> @@ -42,6 +43,10 @@ properties:
>        - const: unipro
>        - const: mp
>  
> +  resets:
> +    items:
> +      - description: Optional UFS M-PHY reset.
> +
>    "#phy-cells":
>      const: 0
>  
> @@ -65,5 +70,16 @@ examples:
>          clock-names = "unipro", "mp";
>          #phy-cells = <0>;
>      };
> +  - |
> +    #include <dt-bindings/reset/mediatek,mt8196-resets.h>
> +    ufs-phy@16800000 {
> +        compatible = "mediatek,mt8196-ufsphy", "mediatek,mt8183-ufsphy";
> +        reg = <0x16800000 0x10000>;
> +        clocks = <&ufs_ao_clk 3>,
> +                 <&ufs_ao_clk 5>;
> +        clock-names = "unipro", "mp";
> +        resets = <&ufs_ao_clk MT8196_UFSAO_RST0_UFS_MPHY>;
> +        #phy-cells = <0>;
> +    };
>  
>  ...
> 
> -- 
> 2.51.1.dirty
> 

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