[PATCH 00/19] Add RZ/G3E RSCI support

[PATCH 00/19] Add RZ/G3E RSCI support

[Biju Das]

Add RZ/G3E RSCI support for FIFO and non-FIFO mode. RSCI IP found on
RZ/G3E SoC is similar to one on RZ/T2H, but has 32-stage fifo. RZ/G3E has
5 module clocks compared to 2 on RZ/T2H, and it has multiple resets.
Add support for hardware flow control.

Biju Das (19):
  clk: renesas: r9a09g047: Add RSCI clocks/resets
  dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"
  dt-bindings: serial: renesas,rsci: Document RZ/G3E support
  serial: sh-sci: Fix deadlock during RSCI FIFO overrun error
  serial: rsci: Drop rsci_clear_CFC()
  serial: sh-sci: Drop extra line
  serial: rsci: Drop unused macro DCR
  serial: rsci: Drop unused TDR register
  serial: sh-sci: Use devm_reset_control_array_get_exclusive()
  serial: sh-sci: Add RSCI_PORT_{SCI,SCIF} port IDs
  serial: sh-sci: Add sci_is_rsci_type()
  serial: sh-sci: Add support for RZ/G3E RSCI clks
  serial: sh-sci: Make sci_scbrr_calc() public
  serial: sh-sci: Add finish_console_write() callback
  serial: sh-sci: Add support for RZ/G3E RSCI SCIF
  serial: sh-sci: Add support for RZ/G3E RSCI SCI
  arm64: dts: renesas: r9a09g047: Add RSCI nodes
  arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS
  arm64: dts: renesas: renesas-smarc2: Enable rsci{2,4,9} nodes

 .../bindings/serial/renesas,rsci.yaml         |  84 +++-
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 190 ++++++++
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   |  46 ++
 .../boot/dts/renesas/renesas-smarc2.dtsi      |  18 +-
 drivers/clk/renesas/r9a09g047-cpg.c           | 126 ++++++
 drivers/tty/serial/rsci.c                     | 413 +++++++++++++++---
 drivers/tty/serial/rsci.h                     |   2 +
 drivers/tty/serial/sh-sci-common.h            |  10 +
 drivers/tty/serial/sh-sci.c                   |  65 ++-
 9 files changed, 869 insertions(+), 85 deletions(-)

-- 
2.43.0

[PATCH 01/19] clk: renesas: r9a09g047: Add RSCI clocks/resets

[Biju Das]

Add RSCI clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g047-cpg.c | 126 ++++++++++++++++++++++++++++
 1 file changed, 126 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 68f8b08bd16f..feb49caa9257 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -44,6 +44,9 @@ enum clk_ids {
 	CLK_PLLCLN_DIV8,
 	CLK_PLLCLN_DIV16,
 	CLK_PLLCLN_DIV20,
+	CLK_PLLCLN_DIV64,
+	CLK_PLLCLN_DIV256,
+	CLK_PLLCLN_DIV1024,
 	CLK_PLLDTY_ACPU,
 	CLK_PLLDTY_ACPU_DIV2,
 	CLK_PLLDTY_ACPU_DIV4,
@@ -142,6 +145,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
 	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
 	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
 	DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
+	DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),
+	DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),
+	DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),
 
 	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
 	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
@@ -218,6 +224,106 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
 						BUS_MSTOP(5, BIT(13))),
 	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,
 						BUS_MSTOP(5, BIT(13))),
+	DEF_MOD("rsci0_pclk",			CLK_PLLCM33_DIV16, 5, 13, 2, 29,
+						BUS_MSTOP(11, BIT(3))),
+	DEF_MOD("rsci0_tclk",			CLK_PLLCM33_DIV16, 5, 14, 2, 30,
+						BUS_MSTOP(11, BIT(3))),
+	DEF_MOD("rsci0_ps_ps3_n",		CLK_PLLCLN_DIV1024, 5, 15, 2, 31,
+						BUS_MSTOP(11, BIT(3))),
+	DEF_MOD("rsci0_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 0, 3, 0,
+						BUS_MSTOP(11, BIT(3))),
+	DEF_MOD("rsci0_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 1, 3, 1,
+						BUS_MSTOP(11, BIT(3))),
+	DEF_MOD("rsci1_pclk",			CLK_PLLCM33_DIV16, 6, 2, 3, 2,
+						BUS_MSTOP(11, BIT(4))),
+	DEF_MOD("rsci1_tclk",			CLK_PLLCM33_DIV16, 6, 3, 3, 3,
+						BUS_MSTOP(11, BIT(4))),
+	DEF_MOD("rsci1_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 4, 3, 4,
+						BUS_MSTOP(11, BIT(4))),
+	DEF_MOD("rsci1_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 5, 3, 5,
+						BUS_MSTOP(11, BIT(4))),
+	DEF_MOD("rsci1_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 6, 3, 6,
+						BUS_MSTOP(11, BIT(4))),
+	DEF_MOD("rsci2_pclk",			CLK_PLLCM33_DIV16, 6, 7, 3, 7,
+						BUS_MSTOP(11, BIT(5))),
+	DEF_MOD("rsci2_tclk",			CLK_PLLCM33_DIV16, 6, 8, 3, 8,
+						BUS_MSTOP(11, BIT(5))),
+	DEF_MOD("rsci2_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 9, 3, 9,
+						BUS_MSTOP(11, BIT(5))),
+	DEF_MOD("rsci2_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 10, 3, 10,
+						BUS_MSTOP(11, BIT(5))),
+	DEF_MOD("rsci2_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 11, 3, 11,
+						BUS_MSTOP(11, BIT(5))),
+	DEF_MOD("rsci3_pclk",			CLK_PLLCM33_DIV16, 6, 12, 3, 12,
+						BUS_MSTOP(11, BIT(6))),
+	DEF_MOD("rsci3_tclk",			CLK_PLLCM33_DIV16, 6, 13, 3, 13,
+						BUS_MSTOP(11, BIT(6))),
+	DEF_MOD("rsci3_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 14, 3, 14,
+						BUS_MSTOP(11, BIT(6))),
+	DEF_MOD("rsci3_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 15, 3, 15,
+						BUS_MSTOP(11, BIT(6))),
+	DEF_MOD("rsci3_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 0, 3, 16,
+						BUS_MSTOP(11, BIT(6))),
+	DEF_MOD("rsci4_pclk",			CLK_PLLCM33_DIV16, 7, 1, 3, 17,
+						BUS_MSTOP(11, BIT(7))),
+	DEF_MOD("rsci4_tclk",			CLK_PLLCM33_DIV16, 7, 2, 3, 18,
+						BUS_MSTOP(11, BIT(7))),
+	DEF_MOD("rsci4_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 3, 3, 19,
+						BUS_MSTOP(11, BIT(7))),
+	DEF_MOD("rsci4_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 4, 3, 20,
+						BUS_MSTOP(11, BIT(7))),
+	DEF_MOD("rsci4_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 5, 3, 21,
+						BUS_MSTOP(11, BIT(7))),
+	DEF_MOD("rsci5_pclk",			CLK_PLLCM33_DIV16, 7, 6, 3, 22,
+						BUS_MSTOP(11, BIT(8))),
+	DEF_MOD("rsci5_tclk",			CLK_PLLCM33_DIV16, 7, 7, 3, 23,
+						BUS_MSTOP(11, BIT(8))),
+	DEF_MOD("rsci5_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 8, 3, 24,
+						BUS_MSTOP(11, BIT(8))),
+	DEF_MOD("rsci5_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 9, 3, 25,
+						BUS_MSTOP(11, BIT(8))),
+	DEF_MOD("rsci5_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 10, 3, 26,
+						BUS_MSTOP(11, BIT(8))),
+	DEF_MOD("rsci6_pclk",			CLK_PLLCM33_DIV16, 7, 11, 3, 27,
+						BUS_MSTOP(11, BIT(9))),
+	DEF_MOD("rsci6_tclk",			CLK_PLLCM33_DIV16, 7, 12, 3, 28,
+						BUS_MSTOP(11, BIT(9))),
+	DEF_MOD("rsci6_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 13, 3, 29,
+						BUS_MSTOP(11, BIT(9))),
+	DEF_MOD("rsci6_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 14, 3, 30,
+						BUS_MSTOP(11, BIT(9))),
+	DEF_MOD("rsci6_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 15, 3, 31,
+						BUS_MSTOP(11, BIT(9))),
+	DEF_MOD("rsci7_pclk",			CLK_PLLCM33_DIV16, 8, 0, 4, 0,
+						BUS_MSTOP(11, BIT(10))),
+	DEF_MOD("rsci7_tclk",			CLK_PLLCM33_DIV16, 8, 1, 4, 1,
+						BUS_MSTOP(11, BIT(10))),
+	DEF_MOD("rsci7_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 2, 4, 2,
+						BUS_MSTOP(11, BIT(10))),
+	DEF_MOD("rsci7_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 3, 4, 3,
+						BUS_MSTOP(11, BIT(10))),
+	DEF_MOD("rsci7_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 4, 4, 4,
+						BUS_MSTOP(11, BIT(10))),
+	DEF_MOD("rsci8_pclk",			CLK_PLLCM33_DIV16, 8, 5, 4, 5,
+						BUS_MSTOP(11, BIT(11))),
+	DEF_MOD("rsci8_tclk",			CLK_PLLCM33_DIV16, 8, 6, 4, 6,
+						BUS_MSTOP(11, BIT(11))),
+	DEF_MOD("rsci8_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 7, 4, 7,
+						BUS_MSTOP(11, BIT(11))),
+	DEF_MOD("rsci8_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 8, 4, 8,
+						BUS_MSTOP(11, BIT(11))),
+	DEF_MOD("rsci8_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 9, 4, 9,
+						BUS_MSTOP(11, BIT(11))),
+	DEF_MOD("rsci9_pclk",			CLK_PLLCM33_DIV16, 8, 10, 4, 10,
+						BUS_MSTOP(11, BIT(12))),
+	DEF_MOD("rsci9_tclk",			CLK_PLLCM33_DIV16, 8, 11, 4, 11,
+						BUS_MSTOP(11, BIT(12))),
+	DEF_MOD("rsci9_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 12, 4, 12,
+						BUS_MSTOP(11, BIT(12))),
+	DEF_MOD("rsci9_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 13, 4, 13,
+						BUS_MSTOP(11, BIT(12))),
+	DEF_MOD("rsci9_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 14, 4, 14,
+						BUS_MSTOP(11, BIT(12))),
 	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,
 						BUS_MSTOP(3, BIT(14))),
 	DEF_MOD("i3c_0_pclkrw",			CLK_PLLCLN_DIV16, 9, 0, 4, 16,
@@ -351,6 +457,26 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
 	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
 	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
 	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
+	DEF_RST(8, 1, 3, 18),		/* RSCI0_PRESETN */
+	DEF_RST(8, 2, 3, 19),		/* RSCI0_TRESETN */
+	DEF_RST(8, 3, 3, 20),		/* RSCI1_PRESETN */
+	DEF_RST(8, 4, 3, 21),		/* RSCI1_TRESETN */
+	DEF_RST(8, 5, 3, 22),		/* RSCI2_PRESETN */
+	DEF_RST(8, 6, 3, 23),		/* RSCI2_TRESETN */
+	DEF_RST(8, 7, 3, 24),		/* RSCI3_PRESETN */
+	DEF_RST(8, 8, 3, 25),		/* RSCI3_TRESETN */
+	DEF_RST(8, 9, 3, 26),		/* RSCI4_PRESETN */
+	DEF_RST(8, 10, 3, 27),		/* RSCI4_TRESETN */
+	DEF_RST(8, 11, 3, 28),		/* RSCI5_PRESETN */
+	DEF_RST(8, 12, 3, 29),		/* RSCI5_TRESETN */
+	DEF_RST(8, 13, 3, 30),		/* RSCI6_PRESETN */
+	DEF_RST(8, 14, 3, 31),		/* RSCI6_TRESETN */
+	DEF_RST(8, 15, 4, 0),		/* RSCI7_PRESETN */
+	DEF_RST(9, 0, 4, 1),		/* RSCI7_TRESETN */
+	DEF_RST(9, 1, 4, 2),		/* RSCI8_PRESETN */
+	DEF_RST(9, 2, 4, 3),		/* RSCI8_TRESETN */
+	DEF_RST(9, 3, 4, 4),		/* RSCI9_PRESETN */
+	DEF_RST(9, 4, 4, 5),		/* RSCI9_TRESETN */
 	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
 	DEF_RST(9, 6, 4, 7),		/* I3C_0_PRESETN */
 	DEF_RST(9, 7, 4, 8),		/* I3C_0_TRESETN */
-- 
2.43.0

[PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"

[Biju Das]

Drop "uart-has-rtscts: false" from binding as the IP support hardware
flow control.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/serial/renesas,rsci.yaml | 2 --
 1 file changed, 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
index f50d8e02f476..6b1f827a335b 100644
--- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
@@ -54,8 +54,6 @@ properties:
   power-domains:
     maxItems: 1
 
-  uart-has-rtscts: false
-
 required:
   - compatible
   - reg
-- 
2.43.0

[PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Biju Das]

Add documentation for the serial communication interface (RSCI) found on
the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
has 6 clocks compared to 3 on RZ/T2H, and it has multiple resets.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/serial/renesas,rsci.yaml         | 82 ++++++++++++++++---
 1 file changed, 71 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
index 6b1f827a335b..7cf6348e2b5b 100644
--- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
@@ -10,17 +10,16 @@ maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 
-allOf:
-  - $ref: serial.yaml#
-
 properties:
   compatible:
     oneOf:
-      - items:
-          - const: renesas,r9a09g087-rsci # RZ/N2H
-          - const: renesas,r9a09g077-rsci # RZ/T2H
+      - enum:
+          - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
+          - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
+          - renesas,r9a09g077-rsci # RZ/T2H
 
       - items:
+          - const: renesas,r9a09g087-rsci # RZ/N2H
           - const: renesas,r9a09g077-rsci # RZ/T2H
 
   reg:
@@ -42,14 +41,40 @@ properties:
 
   clocks:
     minItems: 2
-    maxItems: 3
+    maxItems: 6
 
   clock-names:
-    minItems: 2
+    oneOf:
+      - items:
+          - const: operation
+          - const: bus
+      - items:
+          - const: operation
+          - const: bus
+          - const: sck # optional external clock input
+      - items:
+          - const: bus
+          - const: tclk
+          - const: tclk_div64
+          - const: tclk_div16
+          - const: tclk_div4
+      - items:
+          - const: bus
+          - const: tclk
+          - const: tclk_div64
+          - const: tclk_div16
+          - const: tclk_div4
+          - const: sck # optional external clock input
+
+  resets:
+    items:
+      - description: Input for resetting the APB clock
+      - description: Input for resetting TCLK
+
+  reset-names:
     items:
-      - const: operation
-      - const: bus
-      - const: sck # optional external clock input
+      - const: presetn
+      - const: tresetn
 
   power-domains:
     maxItems: 1
@@ -62,6 +87,41 @@ required:
   - clock-names
   - power-domains
 
+allOf:
+  - $ref: serial.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g077-rsci
+    then:
+      properties:
+        clocks:
+          maxItems: 3
+
+        clock-names:
+          maxItems: 3
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a09g047-rsci
+              - renesas,r9a09g047-rscif
+    then:
+      properties:
+        clocks:
+          minItems: 5
+
+        clock-names:
+          minItems: 5
+
+      required:
+        - resets
+        - reset-names
+
 unevaluatedProperties: false
 
 examples:
-- 
2.43.0

[PATCH 04/19] serial: sh-sci: Fix deadlock during RSCI FIFO overrun error

[Biju Das]

On RSCI IP, a deadlock occurs during a FIFO overrun error, as it uses a
different register to clear the FIFO overrun error status.

Cc: stable@kernel.org
Fixes: 0666e3fe95ab ("serial: sh-sci: Add support for RZ/T2H SCI")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/rsci.c          | 1 +
 drivers/tty/serial/sh-sci-common.h | 1 +
 drivers/tty/serial/sh-sci.c        | 8 ++++++--
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
index b3c48dc1e07d..3e1f4b3c4e59 100644
--- a/drivers/tty/serial/rsci.c
+++ b/drivers/tty/serial/rsci.c
@@ -414,6 +414,7 @@ static const struct sci_port_params_bits rsci_port_param_bits = {
 	.rxtx_enable = CCR0_RE | CCR0_TE,
 	.te_clear = CCR0_TE | CCR0_TEIE,
 	.poll_sent_bits = CSR_TDRE | CSR_TEND,
+	.overrun_clr = CFCLR_ORERC,
 };
 
 static const struct sci_port_params rsci_port_params = {
diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h
index e3c028df14f1..bcdb41ddc15d 100644
--- a/drivers/tty/serial/sh-sci-common.h
+++ b/drivers/tty/serial/sh-sci-common.h
@@ -51,6 +51,7 @@ struct sci_port_params_bits {
 	unsigned int rxtx_enable;
 	unsigned int te_clear;
 	unsigned int poll_sent_bits;
+	unsigned int overrun_clr;
 };
 
 struct sci_common_regs {
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 62bb62b82cbe..b33894d0273b 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1024,8 +1024,12 @@ static int sci_handle_fifo_overrun(struct uart_port *port)
 
 	status = s->ops->read_reg(port, s->params->overrun_reg);
 	if (status & s->params->overrun_mask) {
-		status &= ~s->params->overrun_mask;
-		s->ops->write_reg(port, s->params->overrun_reg, status);
+		if (s->type == SCI_PORT_RSCI) {
+			s->ops->clear_SCxSR(port, s->params->param_bits->overrun_clr);
+		} else {
+			status &= ~s->params->overrun_mask;
+			s->ops->write_reg(port, s->params->overrun_reg, status);
+		}
 
 		port->icount.overrun++;
 
-- 
2.43.0

[PATCH 05/19] serial: rsci: Drop rsci_clear_CFC()

[Biju Das]

Drop rsci_clear_CFC() by reusing rsci_clear_SCxSR() as the contents of
both functions are the same.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/rsci.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
index 3e1f4b3c4e59..504361ed5ecc 100644
--- a/drivers/tty/serial/rsci.c
+++ b/drivers/tty/serial/rsci.c
@@ -199,11 +199,6 @@ static unsigned int rsci_get_mctrl(struct uart_port *port)
 	return 0;
 }
 
-static void rsci_clear_CFC(struct uart_port *port, unsigned int mask)
-{
-	rsci_serial_out(port, CFCLR, mask);
-}
-
 static void rsci_start_tx(struct uart_port *port)
 {
 	struct sci_port *sp = to_sci_port(port);
@@ -275,7 +270,7 @@ static void rsci_transmit_chars(struct uart_port *port)
 			break;
 		}
 
-		rsci_clear_CFC(port, CFCLR_TDREC);
+		rsci_clear_SCxSR(port, CFCLR_TDREC);
 		rsci_serial_out(port, TDR, c);
 
 		port->icount.tx++;
-- 
2.43.0

[PATCH 06/19] serial: sh-sci: Drop extra line

[Biju Das]

Shorten the number lines in sci_init_clocks() by fitting the error
message within an 80-character length limit.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/sh-sci.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index b33894d0273b..699c39b81c4b 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3009,8 +3009,7 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
 
 		if (!clk && sci_port->type == SCI_PORT_RSCI &&
 		    (i == SCI_FCK || i == SCI_BRG_INT)) {
-			return dev_err_probe(dev, -ENODEV,
-					     "failed to get %s\n",
+			return dev_err_probe(dev, -ENODEV, "failed to get %s\n",
 					     name);
 		}
 
-- 
2.43.0

[PATCH 07/19] serial: rsci: Drop unused macro DCR

[Biju Das]

Drop unused macro DCR and its bit definition.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/rsci.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
index 504361ed5ecc..470b5701cd67 100644
--- a/drivers/tty/serial/rsci.c
+++ b/drivers/tty/serial/rsci.c
@@ -24,7 +24,6 @@ MODULE_IMPORT_NS("SH_SCI");
 #define CCR3	0x14
 #define CCR4	0x18
 #define FCR	0x24
-#define DCR	0x30
 #define CSR	0x48
 #define FRSR	0x50
 #define FTSR	0x54
@@ -119,8 +118,6 @@ MODULE_IMPORT_NS("SH_SCI");
 /* FFCLR (FIFO Flag CLear Register) */
 #define FFCLR_DRC		BIT(0)	/* DR Clear */
 
-#define DCR_DEPOL		BIT(0)
-
 static u32 rsci_serial_in(struct uart_port *p, int offset)
 {
 	return readl(p->membase + offset);
-- 
2.43.0

[PATCH 08/19] serial: rsci: Drop unused TDR register

[Biju Das]

Drop the unused TDR register-related macros.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/rsci.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
index 470b5701cd67..ade5ee479e99 100644
--- a/drivers/tty/serial/rsci.c
+++ b/drivers/tty/serial/rsci.c
@@ -35,12 +35,6 @@ MODULE_IMPORT_NS("SH_SCI");
 #define RDR_FPER		BIT(11) /* FIFO Parity Error */
 #define RDR_RDAT_MSK		GENMASK(8, 0)
 
-/* TDR (Transmit Data Register) */
-#define TDR_MPBT		BIT(9)	/* Multiprocessor Transfer */
-#define TDR_TDAT_9BIT_LSHIFT	0
-#define TDR_TDAT_9BIT_VAL	0x1FF
-#define TDR_TDAT_9BIT_MSK	(TDR_TDAT_9BIT_VAL << TDR_TDAT_9BIT_LSHIFT)
-
 /* CCR0 (Common Control Register 0) */
 #define CCR0_SSE		BIT(24)	/* SSn# Pin Function Enable */
 #define CCR0_TEIE		BIT(21)	/* Transmit End Interrupt Enable */
-- 
2.43.0

[PATCH 09/19] serial: sh-sci: Use devm_reset_control_array_get_exclusive()

[Biju Das]

Replace devm_*_get_exclusive()->devm_*_array_get_exclusive() to support
existing SoCs along with RZ/G3E as RZ/G3E has 2 resets.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/sh-sci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 699c39b81c4b..4bcd886de75d 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3537,7 +3537,7 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
 
 	data = of_device_get_match_data(&pdev->dev);
 
-	rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+	rstc = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
 	if (IS_ERR(rstc))
 		return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
 					     "failed to get reset ctrl\n"));
-- 
2.43.0

[PATCH 10/19] serial: sh-sci: Add RSCI_PORT_{SCI,SCIF} port IDs

[Biju Das]

RZ/G3E RSCI tx/rx supports both FIFO and non-FIFO mode. It has 32-stage
FIFO. Add RSCI_PORT_SCI port ID for non-FIFO mode and RSCI_PORT_SCIF port
ID for FIFO mode. Update the rx_trigger for both these modes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/sh-sci-common.h | 2 ++
 drivers/tty/serial/sh-sci.c        | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h
index bcdb41ddc15d..ef1d94ae8b5c 100644
--- a/drivers/tty/serial/sh-sci-common.h
+++ b/drivers/tty/serial/sh-sci-common.h
@@ -8,6 +8,8 @@
 /* Private port IDs */
 enum SCI_PORT_TYPE {
 	SCI_PORT_RSCI = BIT(7) | 0,
+	RSCI_PORT_SCI = BIT(7) | 1,
+	RSCI_PORT_SCIF = BIT(7) | 2,
 };
 
 enum SCI_CLKS {
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 4bcd886de75d..77ccf5677561 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3153,6 +3153,9 @@ static int sci_init_single(struct platform_device *dev,
 	case SCI_PORT_RSCI:
 		sci_port->rx_trigger = 15;
 		break;
+	case RSCI_PORT_SCIF:
+		sci_port->rx_trigger = 32;
+		break;
 	default:
 		sci_port->rx_trigger = 1;
 		break;
-- 
2.43.0

[PATCH 11/19] serial: sh-sci: Add sci_is_rsci_type()

[Biju Das]

Add sci_is_rsci_type() for RSCI port type. This will simplify the code
when the support added for RSCI_PORT_{SCI,SCIF} private PORT type.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/sh-sci.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 77ccf5677561..5f5913410df9 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1008,6 +1008,11 @@ static int sci_handle_errors(struct uart_port *port)
 	return copied;
 }
 
+static bool sci_is_rsci_type(u8 type)
+{
+	return (type == SCI_PORT_RSCI || type == RSCI_PORT_SCI || type == RSCI_PORT_SCIF);
+}
+
 static int sci_handle_fifo_overrun(struct uart_port *port)
 {
 	struct tty_port *tport = &port->state->port;
@@ -1016,7 +1021,7 @@ static int sci_handle_fifo_overrun(struct uart_port *port)
 	int copied = 0;
 	u32 status;
 
-	if (s->type != SCI_PORT_RSCI) {
+	if (!sci_is_rsci_type(s->type)) {
 		reg = sci_getreg(port, s->params->overrun_reg);
 		if (!reg->size)
 			return 0;
@@ -1024,7 +1029,7 @@ static int sci_handle_fifo_overrun(struct uart_port *port)
 
 	status = s->ops->read_reg(port, s->params->overrun_reg);
 	if (status & s->params->overrun_mask) {
-		if (s->type == SCI_PORT_RSCI) {
+		if (sci_is_rsci_type(s->type)) {
 			s->ops->clear_SCxSR(port, s->params->param_bits->overrun_clr);
 		} else {
 			status &= ~s->params->overrun_mask;
@@ -1837,7 +1842,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
 	unsigned long flags;
 	u32 ctrl;
 
-	if (s->type != PORT_SCI && s->type != SCI_PORT_RSCI)
+	if (s->type != PORT_SCI && !sci_is_rsci_type(s->type))
 		return sci_tx_interrupt(irq, ptr);
 
 	uart_port_lock_irqsave(port, &flags);
@@ -3116,7 +3121,7 @@ static int sci_init_single(struct platform_device *dev,
 	 * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so
 	 * shuffle the interrupts.
 	 */
-	if (p->type == PORT_SCI || p->type == SCI_PORT_RSCI)
+	if (p->type == PORT_SCI || sci_is_rsci_type(p->type))
 		swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
 
 	/* The SCI generates several interrupts. They can be muxed together or
-- 
2.43.0

[PATCH 12/19] serial: sh-sci: Add support for RZ/G3E RSCI clks

[Biju Das]

RZ/G3E RSCI has 5 module clocks. Add support for these clocks.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/sh-sci-common.h |  3 +++
 drivers/tty/serial/sh-sci.c        | 14 ++++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h
index ef1d94ae8b5c..f730ff9add60 100644
--- a/drivers/tty/serial/sh-sci-common.h
+++ b/drivers/tty/serial/sh-sci-common.h
@@ -17,6 +17,9 @@ enum SCI_CLKS {
 	SCI_SCK,		/* Optional External Clock */
 	SCI_BRG_INT,		/* Optional BRG Internal Clock Source */
 	SCI_SCIF_CLK,		/* Optional BRG External Clock Source */
+	SCI_FCK_DIV64,		/* Optional Functional Clock frequency-divided by 64 */
+	SCI_FCK_DIV16,		/* Optional Functional Clock frequency-divided by 16 */
+	SCI_FCK_DIV4,		/* Optional Functional Clock frequency-divided by 4 */
 	SCI_NUM_CLKS
 };
 
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 5f5913410df9..d45bdda2b6c1 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2994,6 +2994,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
 		[SCI_SCK] = "sck",
 		[SCI_BRG_INT] = "brg_int",
 		[SCI_SCIF_CLK] = "scif_clk",
+		[SCI_FCK_DIV64] = "tclk_div64",
+		[SCI_FCK_DIV16] = "tclk_div16",
+		[SCI_FCK_DIV4] = "tclk_div4",
 	};
 	struct clk *clk;
 	unsigned int i;
@@ -3003,6 +3006,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
 	} else if (sci_port->type == SCI_PORT_RSCI) {
 		clk_names[SCI_FCK] = "operation";
 		clk_names[SCI_BRG_INT] = "bus";
+	} else if (sci_port->type == RSCI_PORT_SCI || sci_port->type == RSCI_PORT_SCIF) {
+		clk_names[SCI_FCK] = "tclk";
+		clk_names[SCI_BRG_INT] = "bus";
 	}
 
 	for (i = 0; i < SCI_NUM_CLKS; i++) {
@@ -3018,6 +3024,14 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
 					     name);
 		}
 
+		if (!clk && (sci_port->type == RSCI_PORT_SCI ||
+			     sci_port->type == RSCI_PORT_SCIF) &&
+		    (i == SCI_FCK || i == SCI_BRG_INT || i == SCI_FCK_DIV64 ||
+		     i == SCI_FCK_DIV16 || i == SCI_FCK_DIV4)) {
+			return dev_err_probe(dev, -ENODEV, "failed to get %s\n",
+					     name);
+		}
+
 		if (!clk && i == SCI_FCK) {
 			/*
 			 * Not all SH platforms declare a clock lookup entry
-- 
2.43.0

[PATCH 13/19] serial: sh-sci: Make sci_scbrr_calc() public

[Biju Das]

Make the function sci_scbrr_calc() public for code reuse to support RZ/G3E
RSCI IP.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/sh-sci-common.h | 3 +++
 drivers/tty/serial/sh-sci.c        | 6 +++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h
index f730ff9add60..a3f4a76cdecb 100644
--- a/drivers/tty/serial/sh-sci-common.h
+++ b/drivers/tty/serial/sh-sci-common.h
@@ -171,6 +171,9 @@ void sci_port_enable(struct sci_port *sci_port);
 int sci_startup(struct uart_port *port);
 void sci_shutdown(struct uart_port *port);
 
+int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr,
+		   unsigned int *srr, unsigned int *cks);
+
 #define min_sr(_port)		ffs((_port)->sampling_rate_mask)
 #define max_sr(_port)		fls((_port)->sampling_rate_mask)
 
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index d45bdda2b6c1..e478286229f6 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2395,9 +2395,8 @@ static int sci_brg_calc(struct sci_port *s, unsigned int bps,
 }
 
 /* calculate sample rate, BRR, and clock select */
-static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
-		   unsigned int *brr, unsigned int *srr,
-		   unsigned int *cks)
+int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr,
+		   unsigned int *srr, unsigned int *cks)
 {
 	unsigned long freq = s->clk_rates[SCI_FCK];
 	unsigned int sr, br, prediv, scrate, c;
@@ -2461,6 +2460,7 @@ static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
 		min_err, *brr, *srr + 1, *cks);
 	return min_err;
 }
+EXPORT_SYMBOL_NS_GPL(sci_scbrr_calc, "SH_SCI");
 
 static void sci_reset(struct uart_port *port)
 {
-- 
2.43.0

[PATCH 14/19] serial: sh-sci: Add finish_console_write() callback

[Biju Das]

Add finish_console_write() callback as RZ/G3E RSCI IP needs special
handling compared to other SoCs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/sh-sci-common.h | 1 +
 drivers/tty/serial/sh-sci.c        | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h
index a3f4a76cdecb..2e97aad390d9 100644
--- a/drivers/tty/serial/sh-sci-common.h
+++ b/drivers/tty/serial/sh-sci-common.h
@@ -95,6 +95,7 @@ struct sci_port_ops {
 	void (*shutdown_complete)(struct uart_port *port);
 
 	void (*prepare_console_write)(struct uart_port *port, u32 ctrl);
+	void (*finish_console_write)(struct uart_port *port, u32 ctrl);
 	void (*console_save)(struct uart_port *port);
 	void (*console_restore)(struct uart_port *port);
 	size_t (*suspend_regs_size)(void);
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index e478286229f6..7d1c8338f36c 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3265,7 +3265,10 @@ static void serial_console_write(struct console *co, const char *s,
 		cpu_relax();
 
 	/* restore the SCSCR */
-	sci_port->ops->write_reg(port, regs->control, ctrl);
+	if (sci_port->ops->finish_console_write)
+		sci_port->ops->finish_console_write(port, ctrl);
+	else
+		sci_port->ops->write_reg(port, regs->control, ctrl);
 
 	if (locked)
 		uart_port_unlock_irqrestore(port, flags);
-- 
2.43.0

[PATCH 15/19] serial: sh-sci: Add support for RZ/G3E RSCI SCIF

[Biju Das]

Add support for RZ/G3E RSCI SCIF(a.k.a FIFO mode). RSCI IP found on the
RZ/G3E SoC is similar to RZ/T2H, but it has a 32-stage FIFO. it has 5
module clocks instead of 2 on T2H and has multiple resets. Add support
for hardware flow control.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/rsci.c   | 279 ++++++++++++++++++++++++++++++++++--
 drivers/tty/serial/rsci.h   |   1 +
 drivers/tty/serial/sh-sci.c |   9 +-
 3 files changed, 279 insertions(+), 10 deletions(-)

diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
index ade5ee479e99..4c74251dc171 100644
--- a/drivers/tty/serial/rsci.c
+++ b/drivers/tty/serial/rsci.c
@@ -11,6 +11,8 @@
 #include <linux/serial_core.h>
 #include <linux/serial_sci.h>
 #include <linux/tty_flip.h>
+
+#include "serial_mctrl_gpio.h"
 #include "rsci.h"
 
 MODULE_IMPORT_NS("SH_SCI");
@@ -59,6 +61,41 @@ MODULE_IMPORT_NS("SH_SCI");
 #define CCR1_CTSPEN		BIT(1)	/* CTS External Pin Enable */
 #define CCR1_CTSE		BIT(0)	/* CTS Enable */
 
+/* CCR2 (Common Control Register 2) */
+#define CCR2_INIT			0xFF000004
+#define CCR2_CKS_TCLK			(0)	/* TCLK clock */
+#define CCR2_CKS_TCLK_DIV4		BIT(20)	/* TCLK/4 clock */
+#define CCR2_CKS_TCLK_DIV16		BIT(21)	/* TCLK16 clock */
+#define CCR2_CKS_TCLK_DIV64		(BIT(21) | BIT(20)) /* TCLK/64 clock */
+#define CCR2_BRME			BIT(16)	/* Bitrate Modulation Enable */
+#define CCR2_ABCSE			BIT(6)	/* Asynchronous Mode Extended Base Clock Select */
+#define CCR2_ABCS			BIT(5)	/* Asynchronous Mode Base Clock Select */
+#define CCR2_BGDM			BIT(4)	/* Baud Rate Generator Double-Speed Mode Select */
+
+/* CCR3 (Common Control Register 3) */
+#define CCR3_INIT			0x1203
+#define CCR3_BLK			BIT(29)	/* Block Transfer Mode */
+#define CCR3_GM				BIT(28)	/* GSM Mode */
+#define CCR3_CKE1			BIT(25)	/* Clock Enable 1 */
+#define CCR3_CKE0			BIT(24)	/* Clock Enable 0 */
+#define CCR3_DEN			BIT(21)	/* Driver Enabled */
+#define CCR3_FM				BIT(20)	/* FIFO Mode Select */
+#define CCR3_MP				BIT(19)	/* Multi-Processor Mode */
+#define CCR3_MOD_ASYNC			0	/* Asynchronous mode (Multi-processor mode) */
+#define CCR3_MOD_IRDA			BIT(16)	/* Smart card interface mode */
+#define CCR3_MOD_CLK_SYNC		BIT(17)	/* Clock synchronous mode */
+#define CCR3_MOD_SPI			(BIT(17) | BIT(16)) /* Simple SPI mode */
+#define CCR3_MOD_I2C			BIT(18)	/* Simple I2C mode */
+#define CCR3_RXDESEL			BIT(15)	/* Asynchronous Start Bit Edge Detection Select */
+#define CCR3_STP			BIT(14)	/* Stop bit Length */
+#define CCR3_SINV			BIT(13)	/* Transmitted/Received Data Invert */
+#define CCR3_LSBF			BIT(12)	/* LSB First select */
+#define CCR3_CHR1			BIT(9)	/* Character Length */
+#define CCR3_CHR0			BIT(8)	/* Character Length */
+#define CCR3_BPEN			BIT(7)	/* Synchronizer Bypass Enable */
+#define CCR3_CPOL			BIT(1)	/* Clock Polarity Select */
+#define CCR3_CPHA			BIT(0)	/* Clock Phase Select */
+
 /* FCR (FIFO Control Register) */
 #define FCR_RFRST		BIT(23)	/* Receive FIFO Data Register Reset */
 #define FCR_TFRST		BIT(15)	/* Transmit FIFO Data Register Reset */
@@ -142,21 +179,162 @@ static void rsci_start_rx(struct uart_port *port)
 	rsci_serial_out(port, CCR0, ctrl);
 }
 
+static void rsci_enable_ms(struct uart_port *port)
+{
+	mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
+}
+
+static void rsci_init_pins(struct uart_port *port, unsigned int cflag)
+{
+	struct sci_port *s = to_sci_port(port);
+
+	/*
+	 * Use port-specific handler if provided.
+	 */
+	if (s->cfg->ops && s->cfg->ops->init_pins) {
+		s->cfg->ops->init_pins(port, cflag);
+		return;
+	}
+
+	if (!s->has_rtscts)
+		return;
+
+	if (s->autorts)
+		rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) |
+				CCR1_CTSE | CCR1_CTSPEN);
+}
+
+static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig)
+{
+	unsigned int bits;
+
+	if (rx_trig >= port->fifosize)
+		rx_trig = port->fifosize - 1;
+	else if (rx_trig < 1)
+		rx_trig = 1;
+
+	bits = rx_trig << 16;
+	rsci_serial_out(port, FCR, (rsci_serial_in(port, FCR) & ~FCR_RTRG4_0) | bits);
+
+	return rx_trig;
+}
+
 static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
 			     const struct ktermios *old)
 {
+	unsigned int ccr2_val = CCR2_INIT, ccr3_val = CCR3_INIT;
+	unsigned int ccr0_val = 0, ccr1_val = 0, ccr4_val = 0;
+	unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
 	struct sci_port *s = to_sci_port(port);
+	unsigned int brr = 255, cks = 0;
+	int min_err = INT_MAX, err;
+	unsigned long max_freq = 0;
+	unsigned int baud, i;
 	unsigned long flags;
+	unsigned int ctrl;
+	int best_clk = -1;
+
+	if ((termios->c_cflag & CSIZE) == CS7) {
+		ccr3_val |= CCR3_CHR0;
+	} else {
+		termios->c_cflag &= ~CSIZE;
+		termios->c_cflag |= CS8;
+	}
+	if (termios->c_cflag & PARENB)
+		ccr1_val |= CCR1_PE;
+	if (termios->c_cflag & PARODD)
+		ccr1_val |= (CCR1_PE | CCR1_PM);
+	if (termios->c_cflag & CSTOPB)
+		ccr3_val |= CCR3_STP;
+
+	/* Enable noise filter function */
+	ccr1_val |= CCR1_NFEN;
+
+	/*
+	 * earlyprintk comes here early on with port->uartclk set to zero.
+	 * the clock framework is not up and running at this point so here
+	 * we assume that 115200 is the maximum baud rate. please note that
+	 * the baud rate is not programmed during earlyprintk - it is assumed
+	 * that the previous boot loader has enabled required clocks and
+	 * setup the baud rate generator hardware for us already.
+	 */
+	if (!port->uartclk) {
+		baud = uart_get_baud_rate(port, termios, old, 0, 115200);
+		goto done;
+	}
+
+	for (i = 0; i < SCI_NUM_CLKS; i++)
+		max_freq = max(max_freq, s->clk_rates[i]);
+
+	baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
+	if (!baud)
+		goto done;
+
+	/* Divided Functional Clock using standard Bit Rate Register */
+	err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
+	if (abs(err) < abs(min_err)) {
+		best_clk = SCI_FCK;
+		ccr0_val = 0;
+		min_err = err;
+		brr = brr1;
+		cks = cks1;
+	}
+
+done:
+	if (best_clk >= 0)
+		dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
+			s->clks[best_clk], baud, min_err);
 
 	sci_port_enable(s);
 	uart_port_lock_irqsave(port, &flags);
 
-	/* For now, only RX enabling is supported */
-	if (termios->c_cflag & CREAD)
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	rsci_serial_out(port, CCR0, ccr0_val);
+
+	ccr3_val |= CCR3_FM;
+
+	rsci_serial_out(port, CCR3, ccr3_val);
+
+	ccr2_val |= (cks << 20) | (brr << 8);
+	rsci_serial_out(port, CCR2, ccr2_val);
+
+	rsci_serial_out(port, CCR1, ccr1_val);
+
+	rsci_serial_out(port, CCR4, ccr4_val);
+
+	ctrl = rsci_serial_in(port, FCR);
+
+	ctrl |= (FCR_RFRST | FCR_TFRST);
+	rsci_serial_out(port, FCR, ctrl);
+
+	if (s->rx_trigger > 1)
+		rsci_scif_set_rtrg(port, s->rx_trigger);
+
+	port->status &= ~UPSTAT_AUTOCTS;
+	s->autorts = false;
+
+	if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) {
+		port->status |= UPSTAT_AUTOCTS;
+		s->autorts = true;
+	}
+
+	rsci_init_pins(port, termios->c_cflag);
+	rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG);
+
+	rsci_serial_out(port, FFCLR, FFCLR_DRC);
+
+	ccr0_val |= CCR0_RE;
+	rsci_serial_out(port, CCR0, ccr0_val);
+
+	if ((termios->c_cflag & CREAD) != 0)
 		rsci_start_rx(port);
 
 	uart_port_unlock_irqrestore(port, flags);
 	sci_port_disable(s);
+
+	if (UART_ENABLE_MS(port, termios->c_cflag))
+		rsci_enable_ms(port);
 }
 
 static int rsci_txfill(struct uart_port *port)
@@ -181,13 +359,32 @@ static unsigned int rsci_tx_empty(struct uart_port *port)
 
 static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl)
 {
-	/* Not supported yet */
+	if (mctrl & TIOCM_LOOP) {
+		/* Standard loopback mode */
+		rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP);
+	}
 }
 
 static unsigned int rsci_get_mctrl(struct uart_port *port)
 {
-	/* Not supported yet */
-	return 0;
+	struct sci_port *s = to_sci_port(port);
+	struct mctrl_gpios *gpios = s->gpios;
+	unsigned int mctrl = 0;
+
+	mctrl_gpio_get(gpios, &mctrl);
+
+	/*
+	 * CTS/RTS is handled in hardware when supported, while nothing
+	 * else is wired up.
+	 */
+	if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))
+		mctrl |= TIOCM_CTS;
+	if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
+		mctrl |= TIOCM_DSR;
+	if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
+		mctrl |= TIOCM_CAR;
+
+	return mctrl;
 }
 
 static void rsci_start_tx(struct uart_port *port)
@@ -346,6 +543,28 @@ static void rsci_receive_chars(struct uart_port *port)
 	}
 }
 
+static void rsci_break_ctl(struct uart_port *port, int break_state)
+{
+	unsigned short ccr0_val, ccr1_val;
+	unsigned long flags;
+
+	uart_port_lock_irqsave(port, &flags);
+	ccr1_val = rsci_serial_in(port, CCR1);
+	ccr0_val = rsci_serial_in(port, CCR0);
+
+	if (break_state == -1) {
+		ccr1_val = (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT;
+		ccr0_val &= ~CCR0_TE;
+	} else {
+		ccr1_val = (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO;
+		ccr0_val |= CCR0_TE;
+	}
+
+	rsci_serial_out(port, CCR1, ccr1_val);
+	rsci_serial_out(port, CCR0, ccr0_val);
+	uart_port_unlock_irqrestore(port, flags);
+}
+
 static void rsci_poll_put_char(struct uart_port *port, unsigned char c)
 {
 	u32 status;
@@ -367,14 +586,30 @@ static void rsci_poll_put_char(struct uart_port *port, unsigned char c)
 static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl)
 {
 	struct sci_port *s = to_sci_port(port);
-	u32 ctrl_temp =
-		s->params->param_bits->rxtx_enable | CCR0_TIE |
-		s->hscif_tot;
+	u32 ctrl_temp = s->params->param_bits->rxtx_enable;
+
+	if (s->type == SCI_PORT_RSCI)
+		ctrl_temp |= CCR0_TIE | s->hscif_tot;
+
 	rsci_serial_out(port, CCR0, ctrl_temp);
 }
 
+static void rsci_finish_console_write(struct uart_port *port, u32 ctrl)
+{
+	rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE);
+	cpu_relax();
+	rsci_serial_out(port, CCR0, ctrl);
+}
+
 static const char *rsci_type(struct uart_port *port)
 {
+	struct sci_port *s = to_sci_port(port);
+
+	switch (s->type) {
+	case RSCI_PORT_SCIF:
+		return "scif";
+	}
+
 	return "rsci";
 }
 
@@ -414,6 +649,17 @@ static const struct sci_port_params rsci_port_params = {
 	.common_regs = &rsci_common_regs,
 };
 
+static const struct sci_port_params rsci_rzg3e_scif_port_params = {
+	.fifosize = 32,
+	.overrun_reg = CSR,
+	.overrun_mask = CSR_ORER,
+	.sampling_rate_mask = SCI_SR(32),
+	.error_mask = RSCI_DEFAULT_ERROR_MASK,
+	.error_clear = RSCI_ERROR_CLEAR,
+	.param_bits = &rsci_port_param_bits,
+	.common_regs = &rsci_common_regs,
+};
+
 static const struct uart_ops rsci_uart_ops = {
 	.tx_empty	= rsci_tx_empty,
 	.set_mctrl	= rsci_set_mctrl,
@@ -421,6 +667,8 @@ static const struct uart_ops rsci_uart_ops = {
 	.start_tx	= rsci_start_tx,
 	.stop_tx	= rsci_stop_tx,
 	.stop_rx	= rsci_stop_rx,
+	.enable_ms	= rsci_enable_ms,
+	.break_ctl	= rsci_break_ctl,
 	.startup	= sci_startup,
 	.shutdown	= sci_shutdown,
 	.set_termios	= rsci_set_termios,
@@ -440,6 +688,7 @@ static const struct sci_port_ops rsci_port_ops = {
 	.receive_chars		= rsci_receive_chars,
 	.poll_put_char		= rsci_poll_put_char,
 	.prepare_console_write	= rsci_prepare_console_write,
+	.finish_console_write	= rsci_finish_console_write,
 	.suspend_regs_size	= rsci_suspend_regs_size,
 	.shutdown_complete	= rsci_shutdown_complete,
 };
@@ -451,6 +700,13 @@ struct sci_of_data of_sci_rsci_data = {
 	.params = &rsci_port_params,
 };
 
+struct sci_of_data of_rsci_scif_data = {
+	.type = RSCI_PORT_SCIF,
+	.ops = &rsci_port_ops,
+	.uart_ops = &rsci_uart_ops,
+	.params = &rsci_rzg3e_scif_port_params,
+};
+
 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
 
 static int __init rsci_early_console_setup(struct earlycon_device *device,
@@ -459,6 +715,13 @@ static int __init rsci_early_console_setup(struct earlycon_device *device,
 	return scix_early_console_setup(device, &of_sci_rsci_data);
 }
 
+static int __init rsci_rzg3e_scif_early_console_setup(struct earlycon_device *device,
+						      const char *opt)
+{
+	return scix_early_console_setup(device, &of_rsci_scif_data);
+}
+
+OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rscif", rsci_rzg3e_scif_early_console_setup);
 OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_setup);
 
 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h
index 2af3f28b465a..ba255f58c088 100644
--- a/drivers/tty/serial/rsci.h
+++ b/drivers/tty/serial/rsci.h
@@ -6,5 +6,6 @@
 #include "sh-sci-common.h"
 
 extern struct sci_of_data of_sci_rsci_data;
+extern struct sci_of_data of_rsci_scif_data;
 
 #endif /* __RSCI_H__ */
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 7d1c8338f36c..379528c6725a 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3403,7 +3403,7 @@ static void sci_remove(struct platform_device *dev)
 	if (s->port.fifosize > 1)
 		device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
 	if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF ||
-	    type == SCI_PORT_RSCI)
+	    type == SCI_PORT_RSCI || type == RSCI_PORT_SCIF)
 		device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
 }
 
@@ -3498,6 +3498,10 @@ static const struct of_device_id of_sci_match[] __maybe_unused = {
 		.data = &of_sci_scif_rzv2h,
 	},
 #ifdef CONFIG_SERIAL_RSCI
+	{
+		.compatible = "renesas,r9a09g047-rscif",
+		.data = &of_rsci_scif_data,
+	},
 	{
 		.compatible = "renesas,r9a09g077-rsci",
 		.data = &of_sci_rsci_data,
@@ -3765,7 +3769,8 @@ static int sci_probe(struct platform_device *dev)
 			return ret;
 	}
 	if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB ||
-	    sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) {
+	    sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI ||
+	    sp->type == RSCI_PORT_SCIF) {
 		ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
 		if (ret) {
 			if (sp->port.fifosize > 1) {
-- 
2.43.0

[PATCH 16/19] serial: sh-sci: Add support for RZ/G3E RSCI SCI

[Biju Das]

Add support for RZ/G3E RSCI SCI(a.k.a non FIFO mode).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/tty/serial/rsci.c   | 137 ++++++++++++++++++++++++++----------
 drivers/tty/serial/rsci.h   |   1 +
 drivers/tty/serial/sh-sci.c |   4 ++
 3 files changed, 103 insertions(+), 39 deletions(-)

diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
index 4c74251dc171..5901f9e55101 100644
--- a/drivers/tty/serial/rsci.c
+++ b/drivers/tty/serial/rsci.c
@@ -161,8 +161,12 @@ static void rsci_serial_out(struct uart_port *p, int offset, int value)
 
 static void rsci_clear_DRxC(struct uart_port *port)
 {
+	struct sci_port *s = to_sci_port(port);
+
 	rsci_serial_out(port, CFCLR, CFCLR_RDRFC);
-	rsci_serial_out(port, FFCLR, FFCLR_DRC);
+
+	if (s->type != RSCI_PORT_SCI)
+		rsci_serial_out(port, FFCLR, FFCLR_DRC);
 }
 
 static void rsci_clear_SCxSR(struct uart_port *port, unsigned int mask)
@@ -231,7 +235,6 @@ static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
 	unsigned long max_freq = 0;
 	unsigned int baud, i;
 	unsigned long flags;
-	unsigned int ctrl;
 	int best_clk = -1;
 
 	if ((termios->c_cflag & CSIZE) == CS7) {
@@ -292,7 +295,10 @@ static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	rsci_serial_out(port, CCR0, ccr0_val);
 
-	ccr3_val |= CCR3_FM;
+	if (s->type == RSCI_PORT_SCI)
+		ccr3_val |= CCR3_RXDESEL;
+	else
+		ccr3_val |= CCR3_FM;
 
 	rsci_serial_out(port, CCR3, ccr3_val);
 
@@ -303,13 +309,15 @@ static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	rsci_serial_out(port, CCR4, ccr4_val);
 
-	ctrl = rsci_serial_in(port, FCR);
+	if (s->type != RSCI_PORT_SCI) {
+		unsigned int ctrl = rsci_serial_in(port, FCR);
 
-	ctrl |= (FCR_RFRST | FCR_TFRST);
-	rsci_serial_out(port, FCR, ctrl);
+		ctrl |= (FCR_RFRST | FCR_TFRST);
+		rsci_serial_out(port, FCR, ctrl);
 
-	if (s->rx_trigger > 1)
-		rsci_scif_set_rtrg(port, s->rx_trigger);
+		if (s->rx_trigger > 1)
+			rsci_scif_set_rtrg(port, s->rx_trigger);
+	}
 
 	port->status &= ~UPSTAT_AUTOCTS;
 	s->autorts = false;
@@ -322,7 +330,8 @@ static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
 	rsci_init_pins(port, termios->c_cflag);
 	rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG);
 
-	rsci_serial_out(port, FFCLR, FFCLR_DRC);
+	if (s->type != RSCI_PORT_SCI)
+		rsci_serial_out(port, FFCLR, FFCLR_DRC);
 
 	ccr0_val |= CCR0_RE;
 	rsci_serial_out(port, CCR0, ccr0_val);
@@ -339,12 +348,23 @@ static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
 
 static int rsci_txfill(struct uart_port *port)
 {
-	return rsci_serial_in(port, FTSR);
+	struct sci_port *s = to_sci_port(port);
+
+	if (s->type == RSCI_PORT_SCI)
+		return !(rsci_serial_in(port, CSR) & CSR_TDRE);
+	else
+		return rsci_serial_in(port, FTSR);
 }
 
 static int rsci_rxfill(struct uart_port *port)
 {
-	u32 val = rsci_serial_in(port, FRSR);
+	struct sci_port *s = to_sci_port(port);
+	u32 val;
+
+	if (s->type == RSCI_PORT_SCI)
+		return (rsci_serial_in(port, CSR) & CSR_RDRF) != 0;
+
+	val = rsci_serial_in(port, FRSR);
 
 	return FIELD_GET(FRSR_R5_0, val);
 }
@@ -359,7 +379,9 @@ static unsigned int rsci_tx_empty(struct uart_port *port)
 
 static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl)
 {
-	if (mctrl & TIOCM_LOOP) {
+	struct sci_port *s = to_sci_port(port);
+
+	if ((mctrl & TIOCM_LOOP) && s->type != RSCI_PORT_SCI) {
 		/* Standard loopback mode */
 		rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP);
 	}
@@ -478,12 +500,13 @@ static void rsci_transmit_chars(struct uart_port *port)
 static void rsci_receive_chars(struct uart_port *port)
 {
 	struct tty_port *tport = &port->state->port;
+	struct sci_port *s = to_sci_port(port);
 	u32 rdat, status, frsr_status = 0;
 	int i, count, copied = 0;
 	unsigned char flag;
 
 	status = rsci_serial_in(port, CSR);
-	frsr_status = rsci_serial_in(port, FRSR);
+	frsr_status = (s->type == RSCI_PORT_SCI) ? 0 : rsci_serial_in(port, FRSR);
 
 	if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR))
 		return;
@@ -496,33 +519,42 @@ static void rsci_receive_chars(struct uart_port *port)
 		if (count == 0)
 			break;
 
-		for (i = 0; i < count; i++) {
-			char c;
-
-			rdat = rsci_serial_in(port, RDR);
-			/* 9-bits data is not supported yet */
-			c = rdat & RDR_RDAT_MSK;
-
-			if (uart_handle_sysrq_char(port, c)) {
-				count--;
-				i--;
-				continue;
-			}
-
-			/* Store data and status.
-			 * Non FIFO mode is not supported
-			 */
-			if (rdat & RDR_FFER) {
-				flag = TTY_FRAME;
-				port->icount.frame++;
-			} else if (rdat & RDR_FPER) {
-				flag = TTY_PARITY;
-				port->icount.parity++;
-			} else {
-				flag = TTY_NORMAL;
+		if (s->type == RSCI_PORT_SCI) {
+			char c = rsci_serial_in(port, RDR) & RDR_RDAT_MSK;
+
+			if (uart_handle_sysrq_char(port, c))
+				count = 0;
+			else
+				tty_insert_flip_char(tport, c, TTY_NORMAL);
+		} else {
+			for (i = 0; i < count; i++) {
+				char c;
+
+				rdat = rsci_serial_in(port, RDR);
+				/* 9-bits data is not supported yet */
+				c = rdat & RDR_RDAT_MSK;
+
+				if (uart_handle_sysrq_char(port, c)) {
+					count--;
+					i--;
+					continue;
+				}
+
+				/* Store data and status.
+				 * Non FIFO mode is not supported
+				 */
+				if (rdat & RDR_FFER) {
+					flag = TTY_FRAME;
+					port->icount.frame++;
+				} else if (rdat & RDR_FPER) {
+					flag = TTY_PARITY;
+					port->icount.parity++;
+				} else {
+					flag = TTY_NORMAL;
+				}
+
+				tty_insert_flip_char(tport, c, flag);
 			}
-
-			tty_insert_flip_char(tport, c, flag);
 		}
 
 		rsci_serial_in(port, CSR); /* dummy read */
@@ -606,6 +638,8 @@ static const char *rsci_type(struct uart_port *port)
 	struct sci_port *s = to_sci_port(port);
 
 	switch (s->type) {
+	case RSCI_PORT_SCI:
+		return "sci";
 	case RSCI_PORT_SCIF:
 		return "scif";
 	}
@@ -649,6 +683,17 @@ static const struct sci_port_params rsci_port_params = {
 	.common_regs = &rsci_common_regs,
 };
 
+static const struct sci_port_params rsci_rzg3e_sci_port_params = {
+	.fifosize = 1,
+	.overrun_reg = CSR,
+	.overrun_mask = CSR_ORER,
+	.sampling_rate_mask = SCI_SR(32),
+	.error_mask = RSCI_DEFAULT_ERROR_MASK,
+	.error_clear = RSCI_ERROR_CLEAR,
+	.param_bits = &rsci_port_param_bits,
+	.common_regs = &rsci_common_regs,
+};
+
 static const struct sci_port_params rsci_rzg3e_scif_port_params = {
 	.fifosize = 32,
 	.overrun_reg = CSR,
@@ -700,6 +745,13 @@ struct sci_of_data of_sci_rsci_data = {
 	.params = &rsci_port_params,
 };
 
+struct sci_of_data of_rsci_sci_data = {
+	.type = RSCI_PORT_SCI,
+	.ops = &rsci_port_ops,
+	.uart_ops = &rsci_uart_ops,
+	.params = &rsci_rzg3e_sci_port_params,
+};
+
 struct sci_of_data of_rsci_scif_data = {
 	.type = RSCI_PORT_SCIF,
 	.ops = &rsci_port_ops,
@@ -715,12 +767,19 @@ static int __init rsci_early_console_setup(struct earlycon_device *device,
 	return scix_early_console_setup(device, &of_sci_rsci_data);
 }
 
+static int __init rsci_rzg3e_sci_early_console_setup(struct earlycon_device *device,
+						     const char *opt)
+{
+	return scix_early_console_setup(device, &of_rsci_sci_data);
+}
+
 static int __init rsci_rzg3e_scif_early_console_setup(struct earlycon_device *device,
 						      const char *opt)
 {
 	return scix_early_console_setup(device, &of_rsci_scif_data);
 }
 
+OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_sci_early_console_setup);
 OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rscif", rsci_rzg3e_scif_early_console_setup);
 OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_setup);
 
diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h
index ba255f58c088..df7a7edad7d4 100644
--- a/drivers/tty/serial/rsci.h
+++ b/drivers/tty/serial/rsci.h
@@ -6,6 +6,7 @@
 #include "sh-sci-common.h"
 
 extern struct sci_of_data of_sci_rsci_data;
+extern struct sci_of_data of_rsci_sci_data;
 extern struct sci_of_data of_rsci_scif_data;
 
 #endif /* __RSCI_H__ */
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 379528c6725a..43c3e90f0a53 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3498,6 +3498,10 @@ static const struct of_device_id of_sci_match[] __maybe_unused = {
 		.data = &of_sci_scif_rzv2h,
 	},
 #ifdef CONFIG_SERIAL_RSCI
+	{
+		.compatible = "renesas,r9a09g047-rsci",
+		.data = &of_rsci_sci_data,
+	},
 	{
 		.compatible = "renesas,r9a09g047-rscif",
 		.data = &of_rsci_scif_data,
-- 
2.43.0

[PATCH 17/19] arm64: dts: renesas: r9a09g047: Add RSCI nodes

[Biju Das]

Add RSCI nodes to RZ/G3E ("R9A09G047") SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 190 +++++++++++++++++++++
 1 file changed, 190 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 7a469de3bb62..2cc950d99bd3 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -823,6 +823,196 @@ i2c8: i2c@11c01000 {
 			status = "disabled";
 		};
 
+		rsci0: serial@12800c00 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12800c00 0 0x400>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 93>, <&cpg CPG_MOD 94>,
+				 <&cpg CPG_MOD 95>, <&cpg CPG_MOD 96>,
+				 <&cpg CPG_MOD 97>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 129>, <&cpg 130>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci1: serial@12801000 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12801000 0 0x400>;
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 98>, <&cpg CPG_MOD 99>,
+				 <&cpg CPG_MOD 100>, <&cpg CPG_MOD 101>,
+				 <&cpg CPG_MOD 102>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 131>, <&cpg 132>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci2: serial@12801400 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12801400 0 0x400>;
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 104>,
+				 <&cpg CPG_MOD 105>, <&cpg CPG_MOD 106>,
+				 <&cpg CPG_MOD 107>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 133>, <&cpg 134>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci3: serial@12801800 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12801800 0 0x400>;
+			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 108>, <&cpg CPG_MOD 109>,
+				 <&cpg CPG_MOD 110>, <&cpg CPG_MOD 111>,
+				 <&cpg CPG_MOD 112>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 135>, <&cpg 136>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci4: serial@12801c00 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12801c00 0 0x400>;
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 113>, <&cpg CPG_MOD 114>,
+				 <&cpg CPG_MOD 115>, <&cpg CPG_MOD 116>,
+				 <&cpg CPG_MOD 117>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 137>, <&cpg 138>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci5: serial@12802000 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12802000 0 0x400>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 118>, <&cpg CPG_MOD 119>,
+				 <&cpg CPG_MOD 120>, <&cpg CPG_MOD 121>,
+				 <&cpg CPG_MOD 122>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 139>, <&cpg 140>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci6: serial@12802400 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12802400 0 0x400>;
+			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 123>, <&cpg CPG_MOD 124>,
+				 <&cpg CPG_MOD 125>, <&cpg CPG_MOD 126>,
+				 <&cpg CPG_MOD 127>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 141>, <&cpg 142>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci7: serial@12802800 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12802800 0 0x400>;
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 128>, <&cpg CPG_MOD 129>,
+				 <&cpg CPG_MOD 130>, <&cpg CPG_MOD 131>,
+				 <&cpg CPG_MOD 132>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 143>, <&cpg 144>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci8: serial@12802c00 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12802c00 0 0x400>;
+			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 133>, <&cpg CPG_MOD 134>,
+				 <&cpg CPG_MOD 135>, <&cpg CPG_MOD 136>,
+				 <&cpg CPG_MOD 137>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 145>, <&cpg 146>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci9: serial@12803000 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12803000 0 0x400>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 138>, <&cpg CPG_MOD 139>,
+				 <&cpg CPG_MOD 140>, <&cpg CPG_MOD 141>,
+				 <&cpg CPG_MOD 142>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 147>, <&cpg 148>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
 		gpu: gpu@14850000 {
 			compatible = "renesas,r9a09g047-mali",
 				     "arm,mali-bifrost";
-- 
2.43.0

[PATCH 18/19] arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS

[Biju Das]

SMARC2 board dtsi is common for multiple SoCs. So Move aliases
to board DTS as SoC may have different IPs for a given alias.
eg: RZ/G3S does not have RSCI interface.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 6 ++++++
 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi    | 6 ------
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 08e814c03fa8..12cd488f5dfa 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -36,6 +36,12 @@ / {
 	compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
 		     "renesas,r9a09g047e57", "renesas,r9a09g047";
 
+	aliases {
+		i2c0 = &i2c0;
+		serial3 = &scif0;
+		mmc1 = &sdhi1;
+	};
+
 	vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
 		compatible = "regulator-gpio";
 		regulator-name = "SD1_PVDD";
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index 58561da3007a..a296c2c1c7ab 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -37,12 +37,6 @@ chosen {
 		stdout-path = "serial3:115200n8";
 	};
 
-	aliases {
-		i2c0 = &i2c0;
-		serial3 = &scif0;
-		mmc1 = &sdhi1;
-	};
-
 	can_transceiver0: can-phy0 {
 		compatible = "ti,tcan1042";
 		#phy-cells = <0>;
-- 
2.43.0

[PATCH 19/19] arm64: dts: renesas: renesas-smarc2: Enable rsci{2,4,9} nodes

[Biju Das]

Enable device rsci{2,4,9} nodes for the RZ SMARC Carrier-II Board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   | 40 +++++++++++++++++++
 .../boot/dts/renesas/renesas-smarc2.dtsi      | 12 ++++++
 2 files changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 12cd488f5dfa..301eb6d47861 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -38,6 +38,9 @@ / {
 
 	aliases {
 		i2c0 = &i2c0;
+		serial0 = &rsci4;
+		serial1 = &rsci9;
+		serial2 = &rsci2;
 		serial3 = &scif0;
 		mmc1 = &sdhi1;
 	};
@@ -141,6 +144,26 @@ nmi_pins: nmi {
 		input-schmitt-enable;
 	};
 
+	rsci2_pins: rsci2 {
+		pinmux = <RZG3E_PORT_PINMUX(1, 1, 1)>, /* SER2_TX */
+			 <RZG3E_PORT_PINMUX(1, 0, 1)>, /* SER2_RX */
+			 <RZG3E_PORT_PINMUX(1, 2, 6)>, /* SER2_CTS# */
+			 <RZG3E_PORT_PINMUX(1, 3, 1)>; /* SER2_RTS# */
+		bias-pull-up;
+	};
+
+	rsci4_pins: rsci4 {
+		pinmux = <RZG3E_PORT_PINMUX(7, 7, 5)>, /* SER0_TX */
+			 <RZG3E_PORT_PINMUX(7, 6, 5)>; /* SER0_RX */
+		bias-pull-up;
+	};
+
+	rsci9_pins: rsci9 {
+		pinmux = <RZG3E_PORT_PINMUX(8, 3, 5)>, /* SER1_TX */
+			 <RZG3E_PORT_PINMUX(8, 2, 5)>; /* SER1_RX */
+		bias-pull-up;
+	};
+
 	scif_pins: scif {
 		pins = "SCIF_TXD", "SCIF_RXD";
 		renesas,output-impedance = <1>;
@@ -172,6 +195,23 @@ sd1-data {
 	};
 };
 
+&rsci2 {
+	pinctrl-0 = <&rsci2_pins>;
+	pinctrl-names = "default";
+
+	uart-has-rtscts;
+};
+
+&rsci4 {
+	pinctrl-0 = <&rsci4_pins>;
+	pinctrl-names = "default";
+};
+
+&rsci9 {
+	pinctrl-0 = <&rsci9_pins>;
+	pinctrl-names = "default";
+};
+
 &scif0 {
 	pinctrl-0 = <&scif_pins>;
 	pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index a296c2c1c7ab..305215cdaeb3 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -89,6 +89,18 @@ &i2c0 {
 	clock-frequency = <400000>;
 };
 
+&rsci2 {
+	status = "okay";
+};
+
+&rsci4 {
+	status = "okay";
+};
+
+&rsci9 {
+	status = "okay";
+};
+
 &scif0 {
 	status = "okay";
 };
-- 
2.43.0

Re: [PATCH 04/19] serial: sh-sci: Fix deadlock during RSCI FIFO overrun error

[Greg Kroah-Hartman]

On Mon, Oct 27, 2025 at 03:45:51PM +0000, Biju Das wrote:
> On RSCI IP, a deadlock occurs during a FIFO overrun error, as it uses a
> different register to clear the FIFO overrun error status.
> 
> Cc: stable@kernel.org
> Fixes: 0666e3fe95ab ("serial: sh-sci: Add support for RZ/T2H SCI")
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Why is patch 4/19 the only one marked for stable backports?  That feels
really wrong as that will not show up until after 6.19-rc1 is out, AND
the dependant patches will also not be backported.

Please split up patch series to have "things that must be merged now"
separate from "these are for the next -rc1 release"

thanks,

greg k-h

Re: [PATCH 00/19] Add RZ/G3E RSCI support

[Greg Kroah-Hartman]

On Mon, Oct 27, 2025 at 03:45:47PM +0000, Biju Das wrote:
> Add RZ/G3E RSCI support for FIFO and non-FIFO mode. RSCI IP found on
> RZ/G3E SoC is similar to one on RZ/T2H, but has 32-stage fifo. RZ/G3E has
> 5 module clocks compared to 2 on RZ/T2H, and it has multiple resets.
> Add support for hardware flow control.
> 
> Biju Das (19):
>   clk: renesas: r9a09g047: Add RSCI clocks/resets

Why is a clk patch part of a serial series?  How are we supposed to
merge this thing?

thanks,

greg k-h

RE: [PATCH 04/19] serial: sh-sci: Fix deadlock during RSCI FIFO overrun error

[Biju Das]

Hi Greg,

Thanks for the feedback.

> -----Original Message-----
> From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Sent: 28 October 2025 08:41
> Subject: Re: [PATCH 04/19] serial: sh-sci: Fix deadlock during RSCI FIFO overrun error
> 
> On Mon, Oct 27, 2025 at 03:45:51PM +0000, Biju Das wrote:
> > On RSCI IP, a deadlock occurs during a FIFO overrun error, as it uses
> > a different register to clear the FIFO overrun error status.
> >
> > Cc: stable@kernel.org
> > Fixes: 0666e3fe95ab ("serial: sh-sci: Add support for RZ/T2H SCI")
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Why is patch 4/19 the only one marked for stable backports?  That feels really wrong as that will not
> show up until after 6.19-rc1 is out, AND the dependant patches will also not be backported.
> 

My bad, I will send this patch as a separate one.

> Please split up patch series to have "things that must be merged now"
> separate from "these are for the next -rc1 release"

OK. Will separate this in next version.

Cheers,
Biju

RE: [PATCH 00/19] Add RZ/G3E RSCI support

[Biju Das]

Hi Greg,

Thanks for the feedback.

> -----Original Message-----
> From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Sent: 28 October 2025 08:42
> Subject: Re: [PATCH 00/19] Add RZ/G3E RSCI support
> 
> On Mon, Oct 27, 2025 at 03:45:47PM +0000, Biju Das wrote:
> > Add RZ/G3E RSCI support for FIFO and non-FIFO mode. RSCI IP found on
> > RZ/G3E SoC is similar to one on RZ/T2H, but has 32-stage fifo. RZ/G3E
> > has
> > 5 module clocks compared to 2 on RZ/T2H, and it has multiple resets.
> > Add support for hardware flow control.
> >
> > Biju Das (19):
> >   clk: renesas: r9a09g047: Add RSCI clocks/resets
> 
> Why is a clk patch part of a serial series?  How are we supposed to merge this thing?

OK, will split the series into clock, driver fix, dt-binding fix , 
dt-binding + driver patches for the next and dts patches.

Cheers,
Biju

Re: [PATCH 06/19] serial: sh-sci: Drop extra line

[Hugo Villeneuve]

Hi Biju,

On Mon, 27 Oct 2025 15:45:53 +0000
Biju Das <biju.das.jz@bp.renesas.com> wrote:

> Shorten the number lines in sci_init_clocks() by fitting the error
> message within an 80-character length limit.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  drivers/tty/serial/sh-sci.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index b33894d0273b..699c39b81c4b 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -3009,8 +3009,7 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
>  
>  		if (!clk && sci_port->type == SCI_PORT_RSCI &&
>  		    (i == SCI_FCK || i == SCI_BRG_INT)) {
> -			return dev_err_probe(dev, -ENODEV,
> -					     "failed to get %s\n",
> +			return dev_err_probe(dev, -ENODEV, "failed to get %s\n",
>  					     name);

You can even put it all on one line with the now 100 columns limit.

>  		}
>  
> -- 
> 2.43.0
> 
> 

-- 
Hugo Villeneuve

Re: [PATCH 12/19] serial: sh-sci: Add support for RZ/G3E RSCI clks

[Hugo Villeneuve]

Hi Biju,

On Mon, 27 Oct 2025 15:45:59 +0000
Biju Das <biju.das.jz@bp.renesas.com> wrote:

> RZ/G3E RSCI has 5 module clocks. Add support for these clocks.

In "[PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E
support", you mention that "...RZ/G3E has 6 clocks...", and here 5?

 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  drivers/tty/serial/sh-sci-common.h |  3 +++
>  drivers/tty/serial/sh-sci.c        | 14 ++++++++++++++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h
> index ef1d94ae8b5c..f730ff9add60 100644
> --- a/drivers/tty/serial/sh-sci-common.h
> +++ b/drivers/tty/serial/sh-sci-common.h
> @@ -17,6 +17,9 @@ enum SCI_CLKS {
>  	SCI_SCK,		/* Optional External Clock */
>  	SCI_BRG_INT,		/* Optional BRG Internal Clock Source */
>  	SCI_SCIF_CLK,		/* Optional BRG External Clock Source */
> +	SCI_FCK_DIV64,		/* Optional Functional Clock frequency-divided by 64 */
> +	SCI_FCK_DIV16,		/* Optional Functional Clock frequency-divided by 16 */
> +	SCI_FCK_DIV4,		/* Optional Functional Clock frequency-divided by 4 */

I see 6 clocks here?

>  	SCI_NUM_CLKS
>  };
>  
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 5f5913410df9..d45bdda2b6c1 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -2994,6 +2994,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
>  		[SCI_SCK] = "sck",
>  		[SCI_BRG_INT] = "brg_int",
>  		[SCI_SCIF_CLK] = "scif_clk",
> +		[SCI_FCK_DIV64] = "tclk_div64",
> +		[SCI_FCK_DIV16] = "tclk_div16",
> +		[SCI_FCK_DIV4] = "tclk_div4",
>  	};
>  	struct clk *clk;
>  	unsigned int i;
> @@ -3003,6 +3006,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
>  	} else if (sci_port->type == SCI_PORT_RSCI) {
>  		clk_names[SCI_FCK] = "operation";
>  		clk_names[SCI_BRG_INT] = "bus";
> +	} else if (sci_port->type == RSCI_PORT_SCI || sci_port->type == RSCI_PORT_SCIF) {
> +		clk_names[SCI_FCK] = "tclk";
> +		clk_names[SCI_BRG_INT] = "bus";
>  	}
>  
>  	for (i = 0; i < SCI_NUM_CLKS; i++) {
> @@ -3018,6 +3024,14 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
>  					     name);
>  		}
>  
> +		if (!clk && (sci_port->type == RSCI_PORT_SCI ||
> +			     sci_port->type == RSCI_PORT_SCIF) &&
> +		    (i == SCI_FCK || i == SCI_BRG_INT || i == SCI_FCK_DIV64 ||
> +		     i == SCI_FCK_DIV16 || i == SCI_FCK_DIV4)) {
> +			return dev_err_probe(dev, -ENODEV, "failed to get %s\n",
> +					     name);
> +		}
> +
>  		if (!clk && i == SCI_FCK) {
>  			/*
>  			 * Not all SH platforms declare a clock lookup entry
> -- 
> 2.43.0
> 
> 

-- 
Hugo Villeneuve

RE: [PATCH 12/19] serial: sh-sci: Add support for RZ/G3E RSCI clks

[Biju Das]

Hi Hugo,

Thanks for the feedback.

> -----Original Message-----
> From: Hugo Villeneuve <hugo@hugovil.com>
> Sent: 28 October 2025 14:51
> Subject: Re: [PATCH 12/19] serial: sh-sci: Add support for RZ/G3E RSCI clks
> 
> Hi Biju,
> 
> On Mon, 27 Oct 2025 15:45:59 +0000
> Biju Das <biju.das.jz@bp.renesas.com> wrote:
> 
> > RZ/G3E RSCI has 5 module clocks. Add support for these clocks.
> 
> In "[PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support", you mention that
> "...RZ/G3E has 6 clocks...", and here 5?

5 module clocks + 1 external clock = 6 clocks.

I just omitted external clock here as it is available on both G3E and T2H.

Cheers,
Biju

> 
> 
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  drivers/tty/serial/sh-sci-common.h |  3 +++
> >  drivers/tty/serial/sh-sci.c        | 14 ++++++++++++++
> >  2 files changed, 17 insertions(+)
> >
> > diff --git a/drivers/tty/serial/sh-sci-common.h
> > b/drivers/tty/serial/sh-sci-common.h
> > index ef1d94ae8b5c..f730ff9add60 100644
> > --- a/drivers/tty/serial/sh-sci-common.h
> > +++ b/drivers/tty/serial/sh-sci-common.h
> > @@ -17,6 +17,9 @@ enum SCI_CLKS {
> >  	SCI_SCK,		/* Optional External Clock */
> >  	SCI_BRG_INT,		/* Optional BRG Internal Clock Source */
> >  	SCI_SCIF_CLK,		/* Optional BRG External Clock Source */
> > +	SCI_FCK_DIV64,		/* Optional Functional Clock frequency-divided by 64 */
> > +	SCI_FCK_DIV16,		/* Optional Functional Clock frequency-divided by 16 */
> > +	SCI_FCK_DIV4,		/* Optional Functional Clock frequency-divided by 4 */
> 
> I see 6 clocks here?
> 
> >  	SCI_NUM_CLKS
> >  };
> >
> > diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> > index 5f5913410df9..d45bdda2b6c1 100644
> > --- a/drivers/tty/serial/sh-sci.c
> > +++ b/drivers/tty/serial/sh-sci.c
> > @@ -2994,6 +2994,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> >  		[SCI_SCK] = "sck",
> >  		[SCI_BRG_INT] = "brg_int",
> >  		[SCI_SCIF_CLK] = "scif_clk",
> > +		[SCI_FCK_DIV64] = "tclk_div64",
> > +		[SCI_FCK_DIV16] = "tclk_div16",
> > +		[SCI_FCK_DIV4] = "tclk_div4",
> >  	};
> >  	struct clk *clk;
> >  	unsigned int i;
> > @@ -3003,6 +3006,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> >  	} else if (sci_port->type == SCI_PORT_RSCI) {
> >  		clk_names[SCI_FCK] = "operation";
> >  		clk_names[SCI_BRG_INT] = "bus";
> > +	} else if (sci_port->type == RSCI_PORT_SCI || sci_port->type == RSCI_PORT_SCIF) {
> > +		clk_names[SCI_FCK] = "tclk";
> > +		clk_names[SCI_BRG_INT] = "bus";
> >  	}
> >
> >  	for (i = 0; i < SCI_NUM_CLKS; i++) { @@ -3018,6 +3024,14 @@ static
> > int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> >  					     name);
> >  		}
> >
> > +		if (!clk && (sci_port->type == RSCI_PORT_SCI ||
> > +			     sci_port->type == RSCI_PORT_SCIF) &&
> > +		    (i == SCI_FCK || i == SCI_BRG_INT || i == SCI_FCK_DIV64 ||
> > +		     i == SCI_FCK_DIV16 || i == SCI_FCK_DIV4)) {
> > +			return dev_err_probe(dev, -ENODEV, "failed to get %s\n",
> > +					     name);
> > +		}
> > +
> >  		if (!clk && i == SCI_FCK) {
> >  			/*
> >  			 * Not all SH platforms declare a clock lookup entry
> > --
> > 2.43.0
> >
> >
> 
> --
> Hugo Villeneuve

Re: [PATCH 15/19] serial: sh-sci: Add support for RZ/G3E RSCI SCIF

[Hugo Villeneuve]

Hi Biju,

On Mon, 27 Oct 2025 15:46:02 +0000
Biju Das <biju.das.jz@bp.renesas.com> wrote:

> Add support for RZ/G3E RSCI SCIF(a.k.a FIFO mode). RSCI IP found on the
> RZ/G3E SoC is similar to RZ/T2H, but it has a 32-stage FIFO. it has 5
> module clocks instead of 2 on T2H and has multiple resets. Add support
> for hardware flow control.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  drivers/tty/serial/rsci.c   | 279 ++++++++++++++++++++++++++++++++++--
>  drivers/tty/serial/rsci.h   |   1 +
>  drivers/tty/serial/sh-sci.c |   9 +-
>  3 files changed, 279 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
> index ade5ee479e99..4c74251dc171 100644
> --- a/drivers/tty/serial/rsci.c
> +++ b/drivers/tty/serial/rsci.c
> @@ -11,6 +11,8 @@
>  #include <linux/serial_core.h>
>  #include <linux/serial_sci.h>
>  #include <linux/tty_flip.h>
> +
> +#include "serial_mctrl_gpio.h"
>  #include "rsci.h"
>  
>  MODULE_IMPORT_NS("SH_SCI");
> @@ -59,6 +61,41 @@ MODULE_IMPORT_NS("SH_SCI");
>  #define CCR1_CTSPEN		BIT(1)	/* CTS External Pin Enable */
>  #define CCR1_CTSE		BIT(0)	/* CTS Enable */
>  
> +/* CCR2 (Common Control Register 2) */
> +#define CCR2_INIT			0xFF000004
> +#define CCR2_CKS_TCLK			(0)	/* TCLK clock */
> +#define CCR2_CKS_TCLK_DIV4		BIT(20)	/* TCLK/4 clock */
> +#define CCR2_CKS_TCLK_DIV16		BIT(21)	/* TCLK16 clock */
> +#define CCR2_CKS_TCLK_DIV64		(BIT(21) | BIT(20)) /* TCLK/64 clock */
> +#define CCR2_BRME			BIT(16)	/* Bitrate Modulation Enable */
> +#define CCR2_ABCSE			BIT(6)	/* Asynchronous Mode Extended Base Clock Select */
> +#define CCR2_ABCS			BIT(5)	/* Asynchronous Mode Base Clock Select */
> +#define CCR2_BGDM			BIT(4)	/* Baud Rate Generator Double-Speed Mode Select */
> +
> +/* CCR3 (Common Control Register 3) */
> +#define CCR3_INIT			0x1203
> +#define CCR3_BLK			BIT(29)	/* Block Transfer Mode */
> +#define CCR3_GM				BIT(28)	/* GSM Mode */
> +#define CCR3_CKE1			BIT(25)	/* Clock Enable 1 */
> +#define CCR3_CKE0			BIT(24)	/* Clock Enable 0 */
> +#define CCR3_DEN			BIT(21)	/* Driver Enabled */
> +#define CCR3_FM				BIT(20)	/* FIFO Mode Select */
> +#define CCR3_MP				BIT(19)	/* Multi-Processor Mode */
> +#define CCR3_MOD_ASYNC			0	/* Asynchronous mode (Multi-processor mode) */
> +#define CCR3_MOD_IRDA			BIT(16)	/* Smart card interface mode */
> +#define CCR3_MOD_CLK_SYNC		BIT(17)	/* Clock synchronous mode */
> +#define CCR3_MOD_SPI			(BIT(17) | BIT(16)) /* Simple SPI mode */
> +#define CCR3_MOD_I2C			BIT(18)	/* Simple I2C mode */
> +#define CCR3_RXDESEL			BIT(15)	/* Asynchronous Start Bit Edge Detection Select */
> +#define CCR3_STP			BIT(14)	/* Stop bit Length */
> +#define CCR3_SINV			BIT(13)	/* Transmitted/Received Data Invert */
> +#define CCR3_LSBF			BIT(12)	/* LSB First select */
> +#define CCR3_CHR1			BIT(9)	/* Character Length */
> +#define CCR3_CHR0			BIT(8)	/* Character Length */
> +#define CCR3_BPEN			BIT(7)	/* Synchronizer Bypass Enable */
> +#define CCR3_CPOL			BIT(1)	/* Clock Polarity Select */
> +#define CCR3_CPHA			BIT(0)	/* Clock Phase Select */
> +
>  /* FCR (FIFO Control Register) */
>  #define FCR_RFRST		BIT(23)	/* Receive FIFO Data Register Reset */
>  #define FCR_TFRST		BIT(15)	/* Transmit FIFO Data Register Reset */
> @@ -142,21 +179,162 @@ static void rsci_start_rx(struct uart_port *port)
>  	rsci_serial_out(port, CCR0, ctrl);
>  }
>  
> +static void rsci_enable_ms(struct uart_port *port)
> +{
> +	mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
> +}
> +
> +static void rsci_init_pins(struct uart_port *port, unsigned int cflag)
> +{
> +	struct sci_port *s = to_sci_port(port);
> +
> +	/*
> +	 * Use port-specific handler if provided.
> +	 */

Put on one line: /* Use... */

> +	if (s->cfg->ops && s->cfg->ops->init_pins) {
> +		s->cfg->ops->init_pins(port, cflag);
> +		return;
> +	}
> +
> +	if (!s->has_rtscts)
> +		return;
> +
> +	if (s->autorts)
> +		rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) |
> +				CCR1_CTSE | CCR1_CTSPEN);
> +}
> +
> +static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig)
> +{
> +	unsigned int bits;
> +
> +	if (rx_trig >= port->fifosize)
> +		rx_trig = port->fifosize - 1;
> +	else if (rx_trig < 1)
> +		rx_trig = 1;
> +
> +	bits = rx_trig << 16;
> +	rsci_serial_out(port, FCR, (rsci_serial_in(port, FCR) & ~FCR_RTRG4_0) | bits);
> +
> +	return rx_trig;
> +}
> +
>  static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
>  			     const struct ktermios *old)
>  {
> +	unsigned int ccr2_val = CCR2_INIT, ccr3_val = CCR3_INIT;
> +	unsigned int ccr0_val = 0, ccr1_val = 0, ccr4_val = 0;
> +	unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
>  	struct sci_port *s = to_sci_port(port);
> +	unsigned int brr = 255, cks = 0;
> +	int min_err = INT_MAX, err;
> +	unsigned long max_freq = 0;
> +	unsigned int baud, i;
>  	unsigned long flags;
> +	unsigned int ctrl;
> +	int best_clk = -1;
> +
> +	if ((termios->c_cflag & CSIZE) == CS7) {
> +		ccr3_val |= CCR3_CHR0;
> +	} else {
> +		termios->c_cflag &= ~CSIZE;
> +		termios->c_cflag |= CS8;
> +	}
> +	if (termios->c_cflag & PARENB)
> +		ccr1_val |= CCR1_PE;
> +	if (termios->c_cflag & PARODD)
> +		ccr1_val |= (CCR1_PE | CCR1_PM);
> +	if (termios->c_cflag & CSTOPB)
> +		ccr3_val |= CCR3_STP;
> +
> +	/* Enable noise filter function */
> +	ccr1_val |= CCR1_NFEN;
> +
> +	/*
> +	 * earlyprintk comes here early on with port->uartclk set to zero.
> +	 * the clock framework is not up and running at this point so here
> +	 * we assume that 115200 is the maximum baud rate. please note that
> +	 * the baud rate is not programmed during earlyprintk - it is assumed
> +	 * that the previous boot loader has enabled required clocks and
> +	 * setup the baud rate generator hardware for us already.
> +	 */
> +	if (!port->uartclk) {
> +		baud = uart_get_baud_rate(port, termios, old, 0, 115200);

Here you do not check the baud return value, as you do a few lines
below...

> +		goto done;
> +	}
> +
> +	for (i = 0; i < SCI_NUM_CLKS; i++)
> +		max_freq = max(max_freq, s->clk_rates[i]);
> +
> +	baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
> +	if (!baud)

Here you check the baud return value...

Maybe simplify and commonize the above code with something
like:

--------
if (!port->uartclk) {
    max_freq = 115200;
} else {
    for (i = 0; i < SCI_NUM_CLKS; i++)
	max_freq = max(max_freq, s->clk_rates[i]);

    max_freq /= min_sr(s);
}

baud = uart_get_baud_rate(port, termios, old, 0, max_freq);
if (!baud)
    goto done;
--------




> +		goto done;
> +
> +	/* Divided Functional Clock using standard Bit Rate Register */
> +	err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
> +	if (abs(err) < abs(min_err)) {
> +		best_clk = SCI_FCK;
> +		ccr0_val = 0;
> +		min_err = err;
> +		brr = brr1;
> +		cks = cks1;
> +	}
> +
> +done:
> +	if (best_clk >= 0)
> +		dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
> +			s->clks[best_clk], baud, min_err);
>  
>  	sci_port_enable(s);
>  	uart_port_lock_irqsave(port, &flags);
>  
> -	/* For now, only RX enabling is supported */
> -	if (termios->c_cflag & CREAD)
> +	uart_update_timeout(port, termios->c_cflag, baud);
> +
> +	rsci_serial_out(port, CCR0, ccr0_val);
> +
> +	ccr3_val |= CCR3_FM;
> +

Remove space here to be consistent with below statements?

> +	rsci_serial_out(port, CCR3, ccr3_val);
> +
> +	ccr2_val |= (cks << 20) | (brr << 8);
> +	rsci_serial_out(port, CCR2, ccr2_val);
> +
> +	rsci_serial_out(port, CCR1, ccr1_val);
> +
> +	rsci_serial_out(port, CCR4, ccr4_val);
> +
> +	ctrl = rsci_serial_in(port, FCR);
> +
> +	ctrl |= (FCR_RFRST | FCR_TFRST);
> +	rsci_serial_out(port, FCR, ctrl);
> +
> +	if (s->rx_trigger > 1)
> +		rsci_scif_set_rtrg(port, s->rx_trigger);
> +
> +	port->status &= ~UPSTAT_AUTOCTS;
> +	s->autorts = false;
> +
> +	if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) {
> +		port->status |= UPSTAT_AUTOCTS;
> +		s->autorts = true;
> +	}
> +
> +	rsci_init_pins(port, termios->c_cflag);
> +	rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG);
> +
> +	rsci_serial_out(port, FFCLR, FFCLR_DRC);
> +
> +	ccr0_val |= CCR0_RE;
> +	rsci_serial_out(port, CCR0, ccr0_val);
> +
> +	if ((termios->c_cflag & CREAD) != 0)
>  		rsci_start_rx(port);
>  
>  	uart_port_unlock_irqrestore(port, flags);
>  	sci_port_disable(s);
> +
> +	if (UART_ENABLE_MS(port, termios->c_cflag))
> +		rsci_enable_ms(port);
>  }
>  
>  static int rsci_txfill(struct uart_port *port)
> @@ -181,13 +359,32 @@ static unsigned int rsci_tx_empty(struct uart_port *port)
>  
>  static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl)
>  {
> -	/* Not supported yet */
> +	if (mctrl & TIOCM_LOOP) {
> +		/* Standard loopback mode */
> +		rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP);
> +	}
>  }
>  
>  static unsigned int rsci_get_mctrl(struct uart_port *port)
>  {
> -	/* Not supported yet */
> -	return 0;
> +	struct sci_port *s = to_sci_port(port);
> +	struct mctrl_gpios *gpios = s->gpios;
> +	unsigned int mctrl = 0;
> +
> +	mctrl_gpio_get(gpios, &mctrl);
> +
> +	/*
> +	 * CTS/RTS is handled in hardware when supported, while nothing
> +	 * else is wired up.
> +	 */
> +	if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))
> +		mctrl |= TIOCM_CTS;
> +	if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
> +		mctrl |= TIOCM_DSR;
> +	if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
> +		mctrl |= TIOCM_CAR;

Maybe separate these if blocks with a blank line for readability.

> +
> +	return mctrl;
>  }
>  
>  static void rsci_start_tx(struct uart_port *port)
> @@ -346,6 +543,28 @@ static void rsci_receive_chars(struct uart_port *port)
>  	}
>  }
>  
> +static void rsci_break_ctl(struct uart_port *port, int break_state)
> +{
> +	unsigned short ccr0_val, ccr1_val;
> +	unsigned long flags;
> +
> +	uart_port_lock_irqsave(port, &flags);
> +	ccr1_val = rsci_serial_in(port, CCR1);
> +	ccr0_val = rsci_serial_in(port, CCR0);
> +
> +	if (break_state == -1) {
> +		ccr1_val = (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT;
> +		ccr0_val &= ~CCR0_TE;
> +	} else {
> +		ccr1_val = (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO;
> +		ccr0_val |= CCR0_TE;
> +	}
> +
> +	rsci_serial_out(port, CCR1, ccr1_val);
> +	rsci_serial_out(port, CCR0, ccr0_val);
> +	uart_port_unlock_irqrestore(port, flags);
> +}
> +
>  static void rsci_poll_put_char(struct uart_port *port, unsigned char c)
>  {
>  	u32 status;
> @@ -367,14 +586,30 @@ static void rsci_poll_put_char(struct uart_port *port, unsigned char c)
>  static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl)
>  {
>  	struct sci_port *s = to_sci_port(port);
> -	u32 ctrl_temp =
> -		s->params->param_bits->rxtx_enable | CCR0_TIE |
> -		s->hscif_tot;
> +	u32 ctrl_temp = s->params->param_bits->rxtx_enable;
> +
> +	if (s->type == SCI_PORT_RSCI)
> +		ctrl_temp |= CCR0_TIE | s->hscif_tot;
> +
>  	rsci_serial_out(port, CCR0, ctrl_temp);
>  }
>  
> +static void rsci_finish_console_write(struct uart_port *port, u32 ctrl)
> +{
> +	rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE);
> +	cpu_relax();
> +	rsci_serial_out(port, CCR0, ctrl);
> +}
> +
>  static const char *rsci_type(struct uart_port *port)
>  {
> +	struct sci_port *s = to_sci_port(port);
> +
> +	switch (s->type) {
> +	case RSCI_PORT_SCIF:
> +		return "scif";
> +	}
> +
>  	return "rsci";
>  }
>  
> @@ -414,6 +649,17 @@ static const struct sci_port_params rsci_port_params = {
>  	.common_regs = &rsci_common_regs,
>  };
>  
> +static const struct sci_port_params rsci_rzg3e_scif_port_params = {
> +	.fifosize = 32,
> +	.overrun_reg = CSR,
> +	.overrun_mask = CSR_ORER,
> +	.sampling_rate_mask = SCI_SR(32),
> +	.error_mask = RSCI_DEFAULT_ERROR_MASK,
> +	.error_clear = RSCI_ERROR_CLEAR,
> +	.param_bits = &rsci_port_param_bits,
> +	.common_regs = &rsci_common_regs,
> +};
> +
>  static const struct uart_ops rsci_uart_ops = {
>  	.tx_empty	= rsci_tx_empty,
>  	.set_mctrl	= rsci_set_mctrl,
> @@ -421,6 +667,8 @@ static const struct uart_ops rsci_uart_ops = {
>  	.start_tx	= rsci_start_tx,
>  	.stop_tx	= rsci_stop_tx,
>  	.stop_rx	= rsci_stop_rx,
> +	.enable_ms	= rsci_enable_ms,
> +	.break_ctl	= rsci_break_ctl,
>  	.startup	= sci_startup,
>  	.shutdown	= sci_shutdown,
>  	.set_termios	= rsci_set_termios,
> @@ -440,6 +688,7 @@ static const struct sci_port_ops rsci_port_ops = {
>  	.receive_chars		= rsci_receive_chars,
>  	.poll_put_char		= rsci_poll_put_char,
>  	.prepare_console_write	= rsci_prepare_console_write,
> +	.finish_console_write	= rsci_finish_console_write,
>  	.suspend_regs_size	= rsci_suspend_regs_size,
>  	.shutdown_complete	= rsci_shutdown_complete,
>  };
> @@ -451,6 +700,13 @@ struct sci_of_data of_sci_rsci_data = {
>  	.params = &rsci_port_params,
>  };
>  
> +struct sci_of_data of_rsci_scif_data = {
> +	.type = RSCI_PORT_SCIF,
> +	.ops = &rsci_port_ops,
> +	.uart_ops = &rsci_uart_ops,
> +	.params = &rsci_rzg3e_scif_port_params,
> +};
> +
>  #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
>  
>  static int __init rsci_early_console_setup(struct earlycon_device *device,
> @@ -459,6 +715,13 @@ static int __init rsci_early_console_setup(struct earlycon_device *device,
>  	return scix_early_console_setup(device, &of_sci_rsci_data);
>  }
>  
> +static int __init rsci_rzg3e_scif_early_console_setup(struct earlycon_device *device,
> +						      const char *opt)
> +{
> +	return scix_early_console_setup(device, &of_rsci_scif_data);
> +}
> +
> +OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rscif", rsci_rzg3e_scif_early_console_setup);
>  OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_setup);
>  
>  #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
> diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h
> index 2af3f28b465a..ba255f58c088 100644
> --- a/drivers/tty/serial/rsci.h
> +++ b/drivers/tty/serial/rsci.h
> @@ -6,5 +6,6 @@
>  #include "sh-sci-common.h"
>  
>  extern struct sci_of_data of_sci_rsci_data;
> +extern struct sci_of_data of_rsci_scif_data;
>  
>  #endif /* __RSCI_H__ */
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 7d1c8338f36c..379528c6725a 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -3403,7 +3403,7 @@ static void sci_remove(struct platform_device *dev)
>  	if (s->port.fifosize > 1)
>  		device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
>  	if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF ||
> -	    type == SCI_PORT_RSCI)
> +	    type == SCI_PORT_RSCI || type == RSCI_PORT_SCIF)
>  		device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
>  }
>  
> @@ -3498,6 +3498,10 @@ static const struct of_device_id of_sci_match[] __maybe_unused = {
>  		.data = &of_sci_scif_rzv2h,
>  	},
>  #ifdef CONFIG_SERIAL_RSCI
> +	{
> +		.compatible = "renesas,r9a09g047-rscif",
> +		.data = &of_rsci_scif_data,
> +	},
>  	{
>  		.compatible = "renesas,r9a09g077-rsci",
>  		.data = &of_sci_rsci_data,
> @@ -3765,7 +3769,8 @@ static int sci_probe(struct platform_device *dev)
>  			return ret;
>  	}
>  	if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB ||
> -	    sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) {
> +	    sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI ||
> +	    sp->type == RSCI_PORT_SCIF) {
>  		ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
>  		if (ret) {
>  			if (sp->port.fifosize > 1) {
> -- 
> 2.43.0
> 
> 

Hugo.

Re: [PATCH 12/19] serial: sh-sci: Add support for RZ/G3E RSCI clks

[Hugo Villeneuve]

Hi Biju,

On Tue, 28 Oct 2025 15:08:50 +0000
Biju Das <biju.das.jz@bp.renesas.com> wrote:

> Hi Hugo,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Hugo Villeneuve <hugo@hugovil.com>
> > Sent: 28 October 2025 14:51
> > Subject: Re: [PATCH 12/19] serial: sh-sci: Add support for RZ/G3E RSCI clks
> > 
> > Hi Biju,
> > 
> > On Mon, 27 Oct 2025 15:45:59 +0000
> > Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > 
> > > RZ/G3E RSCI has 5 module clocks. Add support for these clocks.
> > 
> > In "[PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support", you mention that
> > "...RZ/G3E has 6 clocks...", and here 5?
> 
> 5 module clocks + 1 external clock = 6 clocks.

Ok, maybe add this precision in your cover letter (and possibly
other commits) to remove any ambiguity...

> 
> I just omitted external clock here as it is available on both G3E and T2H.
> 
> Cheers,
> Biju
> 
> > 
> > 
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > >  drivers/tty/serial/sh-sci-common.h |  3 +++
> > >  drivers/tty/serial/sh-sci.c        | 14 ++++++++++++++
> > >  2 files changed, 17 insertions(+)
> > >
> > > diff --git a/drivers/tty/serial/sh-sci-common.h
> > > b/drivers/tty/serial/sh-sci-common.h
> > > index ef1d94ae8b5c..f730ff9add60 100644
> > > --- a/drivers/tty/serial/sh-sci-common.h
> > > +++ b/drivers/tty/serial/sh-sci-common.h
> > > @@ -17,6 +17,9 @@ enum SCI_CLKS {
> > >  	SCI_SCK,		/* Optional External Clock */
> > >  	SCI_BRG_INT,		/* Optional BRG Internal Clock Source */
> > >  	SCI_SCIF_CLK,		/* Optional BRG External Clock Source */
> > > +	SCI_FCK_DIV64,		/* Optional Functional Clock frequency-divided by 64 */
> > > +	SCI_FCK_DIV16,		/* Optional Functional Clock frequency-divided by 16 */
> > > +	SCI_FCK_DIV4,		/* Optional Functional Clock frequency-divided by 4 */
> > 
> > I see 6 clocks here?
> > 
> > >  	SCI_NUM_CLKS
> > >  };
> > >
> > > diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> > > index 5f5913410df9..d45bdda2b6c1 100644
> > > --- a/drivers/tty/serial/sh-sci.c
> > > +++ b/drivers/tty/serial/sh-sci.c
> > > @@ -2994,6 +2994,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> > >  		[SCI_SCK] = "sck",
> > >  		[SCI_BRG_INT] = "brg_int",
> > >  		[SCI_SCIF_CLK] = "scif_clk",
> > > +		[SCI_FCK_DIV64] = "tclk_div64",
> > > +		[SCI_FCK_DIV16] = "tclk_div16",
> > > +		[SCI_FCK_DIV4] = "tclk_div4",
> > >  	};
> > >  	struct clk *clk;
> > >  	unsigned int i;
> > > @@ -3003,6 +3006,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> > >  	} else if (sci_port->type == SCI_PORT_RSCI) {
> > >  		clk_names[SCI_FCK] = "operation";
> > >  		clk_names[SCI_BRG_INT] = "bus";
> > > +	} else if (sci_port->type == RSCI_PORT_SCI || sci_port->type == RSCI_PORT_SCIF) {
> > > +		clk_names[SCI_FCK] = "tclk";
> > > +		clk_names[SCI_BRG_INT] = "bus";
> > >  	}
> > >
> > >  	for (i = 0; i < SCI_NUM_CLKS; i++) { @@ -3018,6 +3024,14 @@ static
> > > int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> > >  					     name);
> > >  		}
> > >
> > > +		if (!clk && (sci_port->type == RSCI_PORT_SCI ||
> > > +			     sci_port->type == RSCI_PORT_SCIF) &&
> > > +		    (i == SCI_FCK || i == SCI_BRG_INT || i == SCI_FCK_DIV64 ||
> > > +		     i == SCI_FCK_DIV16 || i == SCI_FCK_DIV4)) {
> > > +			return dev_err_probe(dev, -ENODEV, "failed to get %s\n",
> > > +					     name);
> > > +		}
> > > +
> > >  		if (!clk && i == SCI_FCK) {
> > >  			/*
> > >  			 * Not all SH platforms declare a clock lookup entry
> > > --
> > > 2.43.0
> > >
> > >
> > 
> > --
> > Hugo Villeneuve
> 


-- 
Hugo Villeneuve

Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"

[Conor Dooley]

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On Mon, Oct 27, 2025 at 03:45:49PM +0000, Biju Das wrote:
> Drop "uart-has-rtscts: false" from binding as the IP support hardware
> flow control.

Why is it being removed, rather than only being required for the
existing devices? It's not clear to me that the comment about the IP
supporting flow control excludes the integration on these particular
devices from somehow having flow control disabled.

> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/serial/renesas,rsci.yaml | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> index f50d8e02f476..6b1f827a335b 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> @@ -54,8 +54,6 @@ properties:
>    power-domains:
>      maxItems: 1
>  
> -  uart-has-rtscts: false
> -
>  required:
>    - compatible
>    - reg
> -- 
> 2.43.0
> 

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Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Conor Dooley]

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On Mon, Oct 27, 2025 at 03:45:50PM +0000, Biju Das wrote:
> Add documentation for the serial communication interface (RSCI) found on
> the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
> to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
> to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
> has 6 clocks compared to 3 on RZ/T2H, and it has multiple resets.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../bindings/serial/renesas,rsci.yaml         | 82 ++++++++++++++++---
>  1 file changed, 71 insertions(+), 11 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> index 6b1f827a335b..7cf6348e2b5b 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> @@ -10,17 +10,16 @@ maintainers:
>    - Geert Uytterhoeven <geert+renesas@glider.be>
>    - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>  
> -allOf:
> -  - $ref: serial.yaml#
> -
>  properties:
>    compatible:
>      oneOf:
> -      - items:
> -          - const: renesas,r9a09g087-rsci # RZ/N2H
> -          - const: renesas,r9a09g077-rsci # RZ/T2H
> +      - enum:
> +          - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
> +          - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
> +          - renesas,r9a09g077-rsci # RZ/T2H
>  
>        - items:
> +          - const: renesas,r9a09g087-rsci # RZ/N2H
>            - const: renesas,r9a09g077-rsci # RZ/T2H
>  
>    reg:
> @@ -42,14 +41,40 @@ properties:
>  
>    clocks:
>      minItems: 2
> -    maxItems: 3
> +    maxItems: 6
>  
>    clock-names:
> -    minItems: 2
> +    oneOf:
> +      - items:
> +          - const: operation
> +          - const: bus
> +      - items:
> +          - const: operation
> +          - const: bus
> +          - const: sck # optional external clock input
> +      - items:
> +          - const: bus
> +          - const: tclk
> +          - const: tclk_div64
> +          - const: tclk_div16
> +          - const: tclk_div4
> +      - items:
> +          - const: bus
> +          - const: tclk
> +          - const: tclk_div64
> +          - const: tclk_div16
> +          - const: tclk_div4
> +          - const: sck # optional external clock input
> +
> +  resets:
> +    items:
> +      - description: Input for resetting the APB clock
> +      - description: Input for resetting TCLK
> +
> +  reset-names:
>      items:
> -      - const: operation
> -      - const: bus
> -      - const: sck # optional external clock input
> +      - const: presetn
> +      - const: tresetn
>  
>    power-domains:
>      maxItems: 1
> @@ -62,6 +87,41 @@ required:
>    - clock-names
>    - power-domains
>  
> +allOf:
> +  - $ref: serial.yaml#
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g077-rsci
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 3
> +
> +        clock-names:
> +          maxItems: 3
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - renesas,r9a09g047-rsci
> +              - renesas,r9a09g047-rscif
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 5
> +
> +        clock-names:
> +          minItems: 5
> +
> +      required:
> +        - resets
> +        - reset-names

Does this need an "else: properties: resets: false"? Or do other devices
actually have resets too?

> +
>  unevaluatedProperties: false
>  
>  examples:
> -- 
> 2.43.0
> 

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RE: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"

[Biju Das]

Hi Conor Dooley,

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 28 October 2025 19:28
> Subject: Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"
> 
> On Mon, Oct 27, 2025 at 03:45:49PM +0000, Biju Das wrote:
> > Drop "uart-has-rtscts: false" from binding as the IP support hardware
> > flow control.
> 
> Why is it being removed, rather than only being required for the existing devices? It's not clear to
> me that the comment about the IP supporting flow control excludes the integration on these particular
> devices from somehow having flow control disabled.

It was a mistake previously as the driver does not implement hardware flow control and
is excluded in device tree.

Actually, the RSCI IP on all SoCs supports hardware flow control.
If a channel need flow control it can make use of the property uart-has-rtscts;
That is the reason for removing hardware flow control disabled property("uart-has-rtscts: false")


Cheers,
Biju



> 
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  Documentation/devicetree/bindings/serial/renesas,rsci.yaml | 2 --
> >  1 file changed, 2 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > index f50d8e02f476..6b1f827a335b 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > @@ -54,8 +54,6 @@ properties:
> >    power-domains:
> >      maxItems: 1
> >
> > -  uart-has-rtscts: false
> > -
> >  required:
> >    - compatible
> >    - reg
> > --
> > 2.43.0
> >

RE: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Biju Das]

Hi Conor Dooley,

Thanks for the feedback.

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 28 October 2025 19:31
> Subject: Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
> 
> On Mon, Oct 27, 2025 at 03:45:50PM +0000, Biju Das wrote:
> > Add documentation for the serial communication interface (RSCI) found
> > on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is
> > identical to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage
> > FIFO compared to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode
> > operation. RZ/G3E has 6 clocks compared to 3 on RZ/T2H, and it has multiple resets.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  .../bindings/serial/renesas,rsci.yaml         | 82 ++++++++++++++++---
> >  1 file changed, 71 insertions(+), 11 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > index 6b1f827a335b..7cf6348e2b5b 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > @@ -10,17 +10,16 @@ maintainers:
> >    - Geert Uytterhoeven <geert+renesas@glider.be>
> >    - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > -allOf:
> > -  - $ref: serial.yaml#
> > -
> >  properties:
> >    compatible:
> >      oneOf:
> > -      - items:
> > -          - const: renesas,r9a09g087-rsci # RZ/N2H
> > -          - const: renesas,r9a09g077-rsci # RZ/T2H
> > +      - enum:
> > +          - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
> > +          - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
> > +          - renesas,r9a09g077-rsci # RZ/T2H
> >
> >        - items:
> > +          - const: renesas,r9a09g087-rsci # RZ/N2H
> >            - const: renesas,r9a09g077-rsci # RZ/T2H
> >
> >    reg:
> > @@ -42,14 +41,40 @@ properties:
> >
> >    clocks:
> >      minItems: 2
> > -    maxItems: 3
> > +    maxItems: 6
> >
> >    clock-names:
> > -    minItems: 2
> > +    oneOf:
> > +      - items:
> > +          - const: operation
> > +          - const: bus
> > +      - items:
> > +          - const: operation
> > +          - const: bus
> > +          - const: sck # optional external clock input
> > +      - items:
> > +          - const: bus
> > +          - const: tclk
> > +          - const: tclk_div64
> > +          - const: tclk_div16
> > +          - const: tclk_div4
> > +      - items:
> > +          - const: bus
> > +          - const: tclk
> > +          - const: tclk_div64
> > +          - const: tclk_div16
> > +          - const: tclk_div4
> > +          - const: sck # optional external clock input
> > +
> > +  resets:
> > +    items:
> > +      - description: Input for resetting the APB clock
> > +      - description: Input for resetting TCLK
> > +
> > +  reset-names:
> >      items:
> > -      - const: operation
> > -      - const: bus
> > -      - const: sck # optional external clock input
> > +      - const: presetn
> > +      - const: tresetn
> >
> >    power-domains:
> >      maxItems: 1
> > @@ -62,6 +87,41 @@ required:
> >    - clock-names
> >    - power-domains
> >
> > +allOf:
> > +  - $ref: serial.yaml#
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,r9a09g077-rsci
> > +    then:
> > +      properties:
> > +        clocks:
> > +          maxItems: 3
> > +
> > +        clock-names:
> > +          maxItems: 3
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - renesas,r9a09g047-rsci
> > +              - renesas,r9a09g047-rscif
> > +    then:
> > +      properties:
> > +        clocks:
> > +          minItems: 5
> > +
> > +        clock-names:
> > +          minItems: 5
> > +
> > +      required:
> > +        - resets
> > +        - reset-names
> 
> Does this need an "else: properties: resets: false"? Or do other devices actually have resets too?

It is not required as resets are optional for RZ/T2H and RZ/N2H. RZ/T2H and N2H does not have
Resets.

Cheers,
Biju

> 
> > +
> >  unevaluatedProperties: false
> >
> >  examples:
> > --
> > 2.43.0
> >

Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"

[Conor Dooley]

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On Tue, Oct 28, 2025 at 07:39:41PM +0000, Biju Das wrote:
> Hi Conor Dooley,
> 
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 28 October 2025 19:28
> > Subject: Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"
> > 
> > On Mon, Oct 27, 2025 at 03:45:49PM +0000, Biju Das wrote:
> > > Drop "uart-has-rtscts: false" from binding as the IP support hardware
> > > flow control.
> > 
> > Why is it being removed, rather than only being required for the existing devices? It's not clear to
> > me that the comment about the IP supporting flow control excludes the integration on these particular
> > devices from somehow having flow control disabled.
> 
> It was a mistake previously as the driver does not implement hardware flow control and
> is excluded in device tree.
> 
> Actually, the RSCI IP on all SoCs supports hardware flow control.
> If a channel need flow control it can make use of the property uart-has-rtscts;
> That is the reason for removing hardware flow control disabled property("uart-has-rtscts: false")

Could you update the commit message to be clear that that's the case?
Just something like "as the IP supports hardware flow control on all
SoCs".

With that,
Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

pw-bot: changes-requested

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Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Conor Dooley]

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On Tue, Oct 28, 2025 at 07:41:33PM +0000, Biju Das wrote:
> > > +  - if:
> > > +      properties:
> > > +        compatible:
> > > +          contains:
> > > +            enum:
> > > +              - renesas,r9a09g047-rsci
> > > +              - renesas,r9a09g047-rscif
> > > +    then:
> > > +      properties:
> > > +        clocks:
> > > +          minItems: 5
> > > +
> > > +        clock-names:
> > > +          minItems: 5
> > > +
> > > +      required:
> > > +        - resets
> > > +        - reset-names
> > 
> > Does this need an "else: properties: resets: false"? Or do other devices actually have resets too?
> 
> It is not required as resets are optional for RZ/T2H and RZ/N2H. RZ/T2H and N2H does not have
> Resets.

This is a contradiction. Either they are optional for these platforms or
the platforms do not have resets. Cannot be both!

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RE: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Biju Das]

Hi Conor Dooley,

Thanks for the feedback.

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 28 October 2025 19:52
> Subject: Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
> 
> On Tue, Oct 28, 2025 at 07:41:33PM +0000, Biju Das wrote:
> > > > +  - if:
> > > > +      properties:
> > > > +        compatible:
> > > > +          contains:
> > > > +            enum:
> > > > +              - renesas,r9a09g047-rsci
> > > > +              - renesas,r9a09g047-rscif
> > > > +    then:
> > > > +      properties:
> > > > +        clocks:
> > > > +          minItems: 5
> > > > +
> > > > +        clock-names:
> > > > +          minItems: 5
> > > > +
> > > > +      required:
> > > > +        - resets
> > > > +        - reset-names
> > >
> > > Does this need an "else: properties: resets: false"? Or do other devices actually have resets too?
> >
> > It is not required as resets are optional for RZ/T2H and RZ/N2H.
> > RZ/T2H and N2H does not have Resets.
> 
> This is a contradiction. Either they are optional for these platforms or the platforms do not have
> resets. Cannot be both!

Some RSCI IP SoCs has resets and some does not have. From RSCI IP point of view
this property is optional.

I just try to avoid complex if else statements in dt schema by adding
Per SoC properties.

If you prefer else statements for resets, I can add that as well. Please let me know.

Cheers,
Biju

RE: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"

[Biju Das]

Hi Conor Dooley,

Thanks for the feedback.

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 28 October 2025 19:51
> Subject: Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"
> 
> On Tue, Oct 28, 2025 at 07:39:41PM +0000, Biju Das wrote:
> > Hi Conor Dooley,
> >
> > > -----Original Message-----
> > > From: Conor Dooley <conor@kernel.org>
> > > Sent: 28 October 2025 19:28
> > > Subject: Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"
> > >
> > > On Mon, Oct 27, 2025 at 03:45:49PM +0000, Biju Das wrote:
> > > > Drop "uart-has-rtscts: false" from binding as the IP support
> > > > hardware flow control.
> > >
> > > Why is it being removed, rather than only being required for the
> > > existing devices? It's not clear to me that the comment about the IP
> > > supporting flow control excludes the integration on these particular devices from somehow having
> flow control disabled.
> >
> > It was a mistake previously as the driver does not implement hardware
> > flow control and is excluded in device tree.
> >
> > Actually, the RSCI IP on all SoCs supports hardware flow control.
> > If a channel need flow control it can make use of the property
> > uart-has-rtscts; That is the reason for removing hardware flow control
> > disabled property("uart-has-rtscts: false")
> 
> Could you update the commit message to be clear that that's the case?
> Just something like "as the IP supports hardware flow control on all SoCs".

Agreed, Should I add fixes tag as well?

Cheers,
Biju

> 
> With that,
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> 
> Cheers,
> Conor.
> 
> pw-bot: changes-requested

Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Conor Dooley]

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On Tue, Oct 28, 2025 at 08:26:08PM +0000, Biju Das wrote:
> Hi Conor Dooley,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 28 October 2025 19:52
> > Subject: Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
> > 
> > On Tue, Oct 28, 2025 at 07:41:33PM +0000, Biju Das wrote:
> > > > > +  - if:
> > > > > +      properties:
> > > > > +        compatible:
> > > > > +          contains:
> > > > > +            enum:
> > > > > +              - renesas,r9a09g047-rsci
> > > > > +              - renesas,r9a09g047-rscif
> > > > > +    then:
> > > > > +      properties:
> > > > > +        clocks:
> > > > > +          minItems: 5
> > > > > +
> > > > > +        clock-names:
> > > > > +          minItems: 5
> > > > > +
> > > > > +      required:
> > > > > +        - resets
> > > > > +        - reset-names
> > > >
> > > > Does this need an "else: properties: resets: false"? Or do other devices actually have resets too?
> > >
> > > It is not required as resets are optional for RZ/T2H and RZ/N2H.
> > > RZ/T2H and N2H does not have Resets.
> > 
> > This is a contradiction. Either they are optional for these platforms or the platforms do not have
> > resets. Cannot be both!
> 
> Some RSCI IP SoCs has resets and some does not have. From RSCI IP point of view
> this property is optional.
> 
> I just try to avoid complex if else statements in dt schema by adding
> Per SoC properties.
> 
> If you prefer else statements for resets, I can add that as well. Please let me know.

I would prefer that you do that, yes.

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RE: [PATCH 06/19] serial: sh-sci: Drop extra line

[Biju Das]

Hi Hugo,

> -----Original Message-----
> From: Hugo Villeneuve <hugo@hugovil.com>
> Sent: 28 October 2025 14:35
> Subject: Re: [PATCH 06/19] serial: sh-sci: Drop extra line
> 
> Hi Biju,
> 
> On Mon, 27 Oct 2025 15:45:53 +0000
> Biju Das <biju.das.jz@bp.renesas.com> wrote:
> 
> > Shorten the number lines in sci_init_clocks() by fitting the error
> > message within an 80-character length limit.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  drivers/tty/serial/sh-sci.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> > index b33894d0273b..699c39b81c4b 100644
> > --- a/drivers/tty/serial/sh-sci.c
> > +++ b/drivers/tty/serial/sh-sci.c
> > @@ -3009,8 +3009,7 @@ static int sci_init_clocks(struct sci_port
> > *sci_port, struct device *dev)
> >
> >  		if (!clk && sci_port->type == SCI_PORT_RSCI &&
> >  		    (i == SCI_FCK || i == SCI_BRG_INT)) {
> > -			return dev_err_probe(dev, -ENODEV,
> > -					     "failed to get %s\n",
> > +			return dev_err_probe(dev, -ENODEV, "failed to get %s\n",
> >  					     name);
> 
> You can even put it all on one line with the now 100 columns limit.

Ok will fit into 100 columns limit.

Cheers,
Biju

Re: [PATCH 01/19] clk: renesas: r9a09g047: Add RSCI clocks/resets

[Geert Uytterhoeven]

Hi Biju,

On Mon, 27 Oct 2025 at 16:46, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add RSCI clock and reset entries.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -218,6 +224,106 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
>                                                 BUS_MSTOP(5, BIT(13))),
>         DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
>                                                 BUS_MSTOP(5, BIT(13))),
> +       DEF_MOD("rsci0_pclk",                   CLK_PLLCM33_DIV16, 5, 13, 2, 29,
> +                                               BUS_MSTOP(11, BIT(3))),
> +       DEF_MOD("rsci0_tclk",                   CLK_PLLCM33_DIV16, 5, 14, 2, 30,
> +                                               BUS_MSTOP(11, BIT(3))),

According to both the clock list and the clock system diagram, the
parent clock of rsciN_pclk and rsciN_tclk is CLK_PLLCLN_DIV16?

The rest LGTM, so with the above clarified:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 01/19] clk: renesas: r9a09g047: Add RSCI clocks/resets

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 13 November 2025 18:20
> Subject: Re: [PATCH 01/19] clk: renesas: r9a09g047: Add RSCI clocks/resets
> 
> Hi Biju,
> 
> On Mon, 27 Oct 2025 at 16:46, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Add RSCI clock and reset entries.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > @@ -218,6 +224,106 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> >                                                 BUS_MSTOP(5, BIT(13))),
> >         DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
> >                                                 BUS_MSTOP(5,
> > BIT(13))),
> > +       DEF_MOD("rsci0_pclk",                   CLK_PLLCM33_DIV16, 5, 13, 2, 29,
> > +                                               BUS_MSTOP(11, BIT(3))),
> > +       DEF_MOD("rsci0_tclk",                   CLK_PLLCM33_DIV16, 5, 14, 2, 30,
> > +                                               BUS_MSTOP(11,
> > + BIT(3))),
> 
> According to both the clock list and the clock system diagram, the parent clock of rsciN_pclk and
> rsciN_tclk is CLK_PLLCLN_DIV16?

Thanks, you are correct, I will fix this in next version.

Cheers,
Biju

> 
> The rest LGTM, so with the above clarified:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But when I'm talking to
> journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Re: [PATCH 01/19] clk: renesas: r9a09g047: Add RSCI clocks/resets

[Geert Uytterhoeven]

Hi Biju,

On Thu, 13 Nov 2025 at 20:35, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > On Mon, 27 Oct 2025 at 16:46, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > Add RSCI clock and reset entries.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > > @@ -218,6 +224,106 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> > >                                                 BUS_MSTOP(5, BIT(13))),
> > >         DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
> > >                                                 BUS_MSTOP(5,
> > > BIT(13))),
> > > +       DEF_MOD("rsci0_pclk",                   CLK_PLLCM33_DIV16, 5, 13, 2, 29,
> > > +                                               BUS_MSTOP(11, BIT(3))),
> > > +       DEF_MOD("rsci0_tclk",                   CLK_PLLCM33_DIV16, 5, 14, 2, 30,
> > > +                                               BUS_MSTOP(11,
> > > + BIT(3))),
> >
> > According to both the clock list and the clock system diagram, the parent clock of rsciN_pclk and
> > rsciN_tclk is CLK_PLLCLN_DIV16?
>
> Thanks, you are correct, I will fix this in next version.

Thanks for confirming!
I will fix it while applying, i.e. will queue in renesas-clk for v6.19.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 01/19] clk: renesas: r9a09g047: Add RSCI clocks/resets

[Biju Das]

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 13 November 2025 19:39
> Subject: Re: [PATCH 01/19] clk: renesas: r9a09g047: Add RSCI clocks/resets
> 
> Hi Biju,
> 
> On Thu, 13 Nov 2025 at 20:35, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Mon, 27 Oct 2025
> > > at 16:46, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > Add RSCI clock and reset entries.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > > > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > > > @@ -218,6 +224,106 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> > > >                                                 BUS_MSTOP(5, BIT(13))),
> > > >         DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
> > > >                                                 BUS_MSTOP(5,
> > > > BIT(13))),
> > > > +       DEF_MOD("rsci0_pclk",                   CLK_PLLCM33_DIV16, 5, 13, 2, 29,
> > > > +                                               BUS_MSTOP(11, BIT(3))),
> > > > +       DEF_MOD("rsci0_tclk",                   CLK_PLLCM33_DIV16, 5, 14, 2, 30,
> > > > +                                               BUS_MSTOP(11,
> > > > + BIT(3))),
> > >
> > > According to both the clock list and the clock system diagram, the
> > > parent clock of rsciN_pclk and rsciN_tclk is CLK_PLLCLN_DIV16?
> >
> > Thanks, you are correct, I will fix this in next version.
> 
> Thanks for confirming!
> I will fix it while applying, i.e. will queue in renesas-clk for v6.19.

Thank you for taking care of it.

Cheers,
Biju

Re: [PATCH 17/19] arm64: dts: renesas: r9a09g047: Add RSCI nodes

[Geert Uytterhoeven]

Hi Biju,

On Mon, 27 Oct 2025 at 16:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add RSCI nodes to RZ/G3E ("R9A09G047") SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> @@ -823,6 +823,196 @@ i2c8: i2c@11c01000 {
>                         status = "disabled";
>                 };
>
> +               rsci0: serial@12800c00 {
> +                       compatible = "renesas,r9a09g047-rscif";

"renesas,r9a09g047-rsci", as per the updated DT bindings.

> +                       reg = <0 0x12800c00 0 0x400>;
> +                       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "eri", "rxi", "txi", "tei";

Missing "aed" and "bfd" interrupts, as per to-be-updated DT bindings.

> +                       clocks = <&cpg CPG_MOD 93>, <&cpg CPG_MOD 94>,
> +                                <&cpg CPG_MOD 95>, <&cpg CPG_MOD 96>,
> +                                <&cpg CPG_MOD 97>;
> +                       clock-names = "bus", "tclk", "tclk_div64",
> +                                     "tclk_div16", "tclk_div4";

Third and fifth clock and clock name should be exchanged, as per the
updated DT bindings.

> +                       power-domains = <&cpg>;
> +                       resets = <&cpg 129>, <&cpg 130>;

Please use hexadecimal numbers for module clocks and resets, for
easier matching with the documentation.

> +                       reset-names = "presetn", "tresetn";
> +                       status = "disabled";
> +               };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 18/19] arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS

[Geert Uytterhoeven]

Hi Biju,

On Mon, 27 Oct 2025 at 16:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> SMARC2 board dtsi is common for multiple SoCs. So Move aliases
> to board DTS as SoC may have different IPs for a given alias.
> eg: RZ/G3S does not have RSCI interface.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

Makes sense, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 19/19] arm64: dts: renesas: renesas-smarc2: Enable rsci{2,4,9} nodes

[Geert Uytterhoeven]

Hi Biju,

On Mon, 27 Oct 2025 at 16:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Enable device rsci{2,4,9} nodes for the RZ SMARC Carrier-II Board.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> @@ -38,6 +38,9 @@ / {
>
>         aliases {
>                 i2c0 = &i2c0;
> +               serial0 = &rsci4;
> +               serial1 = &rsci9;
> +               serial2 = &rsci2;
>                 serial3 = &scif0;
>                 mmc1 = &sdhi1;
>         };
> @@ -141,6 +144,26 @@ nmi_pins: nmi {
>                 input-schmitt-enable;
>         };
>
> +       rsci2_pins: rsci2 {
> +               pinmux = <RZG3E_PORT_PINMUX(1, 1, 1)>, /* SER2_TX */
> +                        <RZG3E_PORT_PINMUX(1, 0, 1)>, /* SER2_RX */

Why not order by port number?

> +                        <RZG3E_PORT_PINMUX(1, 2, 6)>, /* SER2_CTS# */
> +                        <RZG3E_PORT_PINMUX(1, 3, 1)>; /* SER2_RTS# */

These comments reflect the board signals?  Usually we put the pin
functions ("TXD2", "RXD2", "CTS2N", "RTS2N") in the comments.

> +               bias-pull-up;
> +       };
> +
> +       rsci4_pins: rsci4 {
> +               pinmux = <RZG3E_PORT_PINMUX(7, 7, 5)>, /* SER0_TX */
> +                        <RZG3E_PORT_PINMUX(7, 6, 5)>; /* SER0_RX */

Why not order by port number?

Pin functions are "TXD4" and "RXD4".

CTS4N and RTS4N seem to be wired, too?

> +               bias-pull-up;
> +       };
> +
> +       rsci9_pins: rsci9 {
> +               pinmux = <RZG3E_PORT_PINMUX(8, 3, 5)>, /* SER1_TX */
> +                        <RZG3E_PORT_PINMUX(8, 2, 5)>; /* SER1_RX */

Why not order by port number?

Pin functions are "TXD9" and "RXD9".

> +               bias-pull-up;
> +       };
> +
>         scif_pins: scif {
>                 pins = "SCIF_TXD", "SCIF_RXD";
>                 renesas,output-impedance = <1>;
> @@ -172,6 +195,23 @@ sd1-data {
>         };
>  };
>
> +&rsci2 {
> +       pinctrl-0 = <&rsci2_pins>;
> +       pinctrl-names = "default";
> +
> +       uart-has-rtscts;
> +};

Shouldn't this be wrapped inside an #ifdef controlled by new defines
SW_SER2_EN and SW_SER0_PMOD?

> +
> +&rsci4 {
> +       pinctrl-0 = <&rsci4_pins>;
> +       pinctrl-names = "default";

uart-has-rtscts?

> +};

Shouldn't this be wrapped inside an #ifdef controlled by SW_LCD_EN?
The port seems to be available irrespective of the setting of
SW_SER0_PMOD, which merely controls routing to either the PMOD or the
M.2 connector.

> +
> +&rsci9 {
> +       pinctrl-0 = <&rsci9_pins>;
> +       pinctrl-names = "default";
> +};
> +
>  &scif0 {
>         pinctrl-0 = <&scif_pins>;
>         pinctrl-names = "default";
> diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> index a296c2c1c7ab..305215cdaeb3 100644
> --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> @@ -89,6 +89,18 @@ &i2c0 {
>         clock-frequency = <400000>;
>  };
>
> +&rsci2 {
> +       status = "okay";
> +};
> +
> +&rsci4 {
> +       status = "okay";
> +};
> +
> +&rsci9 {
> +       status = "okay";
> +};

Given "[PATCH 18/19] arm64: dts: renesas: renesas-smarc2: Move aliases
to board DTS" because RZ/G3S does not have RSCI interfaces, why are
these added here instead of to r9a09g047e57-smarc.dts?

> +
>  &scif0 {
>         status = "okay";
>  };

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 17/19] arm64: dts: renesas: r9a09g047: Add RSCI nodes

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 28 November 2025 13:05
> Subject: Re: [PATCH 17/19] arm64: dts: renesas: r9a09g047: Add RSCI nodes
> 
> Hi Biju,
> 
> On Mon, 27 Oct 2025 at 16:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Add RSCI nodes to RZ/G3E ("R9A09G047") SoC DTSI.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > @@ -823,6 +823,196 @@ i2c8: i2c@11c01000 {
> >                         status = "disabled";
> >                 };
> >
> > +               rsci0: serial@12800c00 {
> > +                       compatible = "renesas,r9a09g047-rscif";
> 
> "renesas,r9a09g047-rsci", as per the updated DT bindings.

OK.

> 
> > +                       reg = <0 0x12800c00 0 0x400>;
> > +                       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
> > +                                    <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
> > +                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-names = "eri", "rxi", "txi", "tei";
> 
> Missing "aed" and "bfd" interrupts, as per to-be-updated DT bindings.

OK.

> 
> > +                       clocks = <&cpg CPG_MOD 93>, <&cpg CPG_MOD 94>,
> > +                                <&cpg CPG_MOD 95>, <&cpg CPG_MOD 96>,
> > +                                <&cpg CPG_MOD 97>;
> > +                       clock-names = "bus", "tclk", "tclk_div64",
> > +                                     "tclk_div16", "tclk_div4";
> 
> Third and fifth clock and clock name should be exchanged, as per the updated DT bindings.

OK.
> 
> > +                       power-domains = <&cpg>;
> > +                       resets = <&cpg 129>, <&cpg 130>;
> 
> Please use hexadecimal numbers for module clocks and resets, for easier matching with the
> documentation.

Agreed, Will fix this in next version.

Cheers,
Biju

RE: [PATCH 19/19] arm64: dts: renesas: renesas-smarc2: Enable rsci{2,4,9} nodes

[Biju Das]

Hi Geert,

Thanks for the feedback

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 28 November 2025 13:41
> Subject: Re: [PATCH 19/19] arm64: dts: renesas: renesas-smarc2: Enable rsci{2,4,9} nodes
> 
> Hi Biju,
> 
> On Mon, 27 Oct 2025 at 16:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Enable device rsci{2,4,9} nodes for the RZ SMARC Carrier-II Board.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > @@ -38,6 +38,9 @@ / {
> >
> >         aliases {
> >                 i2c0 = &i2c0;
> > +               serial0 = &rsci4;
> > +               serial1 = &rsci9;
> > +               serial2 = &rsci2;
> >                 serial3 = &scif0;
> >                 mmc1 = &sdhi1;
> >         };
> > @@ -141,6 +144,26 @@ nmi_pins: nmi {
> >                 input-schmitt-enable;
> >         };
> >
> > +       rsci2_pins: rsci2 {
> > +               pinmux = <RZG3E_PORT_PINMUX(1, 1, 1)>, /* SER2_TX */
> > +                        <RZG3E_PORT_PINMUX(1, 0, 1)>, /* SER2_RX */
> 
> Why not order by port number?

It is mistake, will fix it.

> 
> > +                        <RZG3E_PORT_PINMUX(1, 2, 6)>, /* SER2_CTS# */
> > +                        <RZG3E_PORT_PINMUX(1, 3, 1)>; /* SER2_RTS# */
> 
> These comments reflect the board signals?  Usually we put the pin functions ("TXD2", "RXD2", "CTS2N",
> "RTS2N") in the comments.

OK.

> 
> > +               bias-pull-up;
> > +       };
> > +
> > +       rsci4_pins: rsci4 {
> > +               pinmux = <RZG3E_PORT_PINMUX(7, 7, 5)>, /* SER0_TX */
> > +                        <RZG3E_PORT_PINMUX(7, 6, 5)>; /* SER0_RX */
> 
> Why not order by port number?
> 
> Pin functions are "TXD4" and "RXD4".
> 

OK.

> CTS4N and RTS4N seem to be wired, too?

OK, Will add.

> 
> > +               bias-pull-up;
> > +       };
> > +
> > +       rsci9_pins: rsci9 {
> > +               pinmux = <RZG3E_PORT_PINMUX(8, 3, 5)>, /* SER1_TX */
> > +                        <RZG3E_PORT_PINMUX(8, 2, 5)>; /* SER1_RX */
> 
> Why not order by port number?
> 
> Pin functions are "TXD9" and "RXD9".

OK, will fix this.

> 
> > +               bias-pull-up;
> > +       };
> > +
> >         scif_pins: scif {
> >                 pins = "SCIF_TXD", "SCIF_RXD";
> >                 renesas,output-impedance = <1>; @@ -172,6 +195,23 @@
> > sd1-data {
> >         };
> >  };
> >
> > +&rsci2 {
> > +       pinctrl-0 = <&rsci2_pins>;
> > +       pinctrl-names = "default";
> > +
> > +       uart-has-rtscts;
> > +};
> 
> Shouldn't this be wrapped inside an #ifdef controlled by new defines SW_SER2_EN and SW_SER0_PMOD?

OK, Will add this macros.

SW_SER2_EN by default ON
SW_SER0_PMOD by default ON.

> 
> > +
> > +&rsci4 {
> > +       pinctrl-0 = <&rsci4_pins>;
> > +       pinctrl-names = "default";
> 
> uart-has-rtscts?

OK, Will add.

> 
> > +};
> 
> Shouldn't this be wrapped inside an #ifdef controlled by SW_LCD_EN?

Yes. We cannot use this signal if DPI turned on.

> The port seems to be available irrespective of the setting of SW_SER0_PMOD, which merely controls
> routing to either the PMOD or the
> M.2 connector.

I agree, SW_OPT_MUX.4 will be always on for that
(SMARC SER0 signals connect to PMOD, SMARC SER2 signals connect to M.2 Key-E)

> 
> > +
> > +&rsci9 {
> > +       pinctrl-0 = <&rsci9_pins>;
> > +       pinctrl-names = "default";
> > +};
> > +
> >  &scif0 {
> >         pinctrl-0 = <&scif_pins>;
> >         pinctrl-names = "default";
> > diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > index a296c2c1c7ab..305215cdaeb3 100644
> > --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > @@ -89,6 +89,18 @@ &i2c0 {
> >         clock-frequency = <400000>;
> >  };
> >
> > +&rsci2 {
> > +       status = "okay";
> > +};
> > +
> > +&rsci4 {
> > +       status = "okay";
> > +};
> > +
> > +&rsci9 {
> > +       status = "okay";
> > +};
> 
> Given "[PATCH 18/19] arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS" because RZ/G3S
> does not have RSCI interfaces, why are these added here instead of to r9a09g047e57-smarc.dts?

Agreed.


Cheers,
Biju