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From: Sergey Matyukevich <geomatsi@gmail.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-kselftest@vger.kernel.org
Cc: Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alexandre Ghiti <alex@ghiti.fr>, Oleg Nesterov <oleg@redhat.com>,
	Shuah Khan <shuah@kernel.org>, Thomas Huth <thuth@redhat.com>,
	Charlie Jenkins <charlie@rivosinc.com>,
	Andy Chiu <andybnac@gmail.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Joel Granados <joel.granados@kernel.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Yong-Xuan Wang <yongxuan.wang@sifive.com>,
	Heiko Stuebner <heiko@sntech.de>,
	Sergey Matyukevich <geomatsi@gmail.com>
Subject: [PATCH v4 5/9] riscv: csr: define vtype registers elements
Date: Sat,  8 Nov 2025 22:41:44 +0300	[thread overview]
Message-ID: <20251108194207.1257866-6-geomatsi@gmail.com> (raw)
In-Reply-To: <20251108194207.1257866-1-geomatsi@gmail.com>

Define masks and shifts for vtype csr according to the RVV spec 1.0.

Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
---
 arch/riscv/include/asm/csr.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 4a37a98398ad..4f55dcf86627 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -444,6 +444,17 @@
 #define CSR_VTYPE		0xc21
 #define CSR_VLENB		0xc22
 
+#define VTYPE_VLMUL		_AC(7, UL)
+#define VTYPE_VLMUL_FRAC	_AC(4, UL)
+#define VTYPE_VSEW_SHIFT	3
+#define VTYPE_VSEW		(_AC(7, UL) << VTYPE_VSEW_SHIFT)
+#define VTYPE_VTA_SHIFT		6
+#define VTYPE_VTA		(_AC(1, UL) << VTYPE_VTA_SHIFT)
+#define VTYPE_VMA_SHIFT		7
+#define VTYPE_VMA		(_AC(1, UL) << VTYPE_VMA_SHIFT)
+#define VTYPE_VILL_SHIFT	(__riscv_xlen - 1)
+#define VTYPE_VILL		(_AC(1, UL) << VTYPE_VILL_SHIFT)
+
 /* Scalar Crypto Extension - Entropy */
 #define CSR_SEED		0x015
 #define SEED_OPST_MASK		_AC(0xC0000000, UL)
-- 
2.51.0


WARNING: multiple messages have this Message-ID (diff)
From: Sergey Matyukevich <geomatsi@gmail.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-kselftest@vger.kernel.org
Cc: Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alexandre Ghiti <alex@ghiti.fr>, Oleg Nesterov <oleg@redhat.com>,
	Shuah Khan <shuah@kernel.org>, Thomas Huth <thuth@redhat.com>,
	Charlie Jenkins <charlie@rivosinc.com>,
	Andy Chiu <andybnac@gmail.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Joel Granados <joel.granados@kernel.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Yong-Xuan Wang <yongxuan.wang@sifive.com>,
	Heiko Stuebner <heiko@sntech.de>,
	Sergey Matyukevich <geomatsi@gmail.com>
Subject: [PATCH v4 5/9] riscv: csr: define vtype registers elements
Date: Sat,  8 Nov 2025 22:41:44 +0300	[thread overview]
Message-ID: <20251108194207.1257866-6-geomatsi@gmail.com> (raw)
In-Reply-To: <20251108194207.1257866-1-geomatsi@gmail.com>

Define masks and shifts for vtype csr according to the RVV spec 1.0.

Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
---
 arch/riscv/include/asm/csr.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 4a37a98398ad..4f55dcf86627 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -444,6 +444,17 @@
 #define CSR_VTYPE		0xc21
 #define CSR_VLENB		0xc22
 
+#define VTYPE_VLMUL		_AC(7, UL)
+#define VTYPE_VLMUL_FRAC	_AC(4, UL)
+#define VTYPE_VSEW_SHIFT	3
+#define VTYPE_VSEW		(_AC(7, UL) << VTYPE_VSEW_SHIFT)
+#define VTYPE_VTA_SHIFT		6
+#define VTYPE_VTA		(_AC(1, UL) << VTYPE_VTA_SHIFT)
+#define VTYPE_VMA_SHIFT		7
+#define VTYPE_VMA		(_AC(1, UL) << VTYPE_VMA_SHIFT)
+#define VTYPE_VILL_SHIFT	(__riscv_xlen - 1)
+#define VTYPE_VILL		(_AC(1, UL) << VTYPE_VILL_SHIFT)
+
 /* Scalar Crypto Extension - Entropy */
 #define CSR_SEED		0x015
 #define SEED_OPST_MASK		_AC(0xC0000000, UL)
-- 
2.51.0


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  parent reply	other threads:[~2025-11-08 19:42 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-08 19:41 [PATCH v4 0/9] riscv: vector: misc ptrace fixes for debug use-cases Sergey Matyukevich
2025-11-08 19:41 ` Sergey Matyukevich
2025-11-08 19:41 ` [PATCH v4 1/9] selftests: riscv: test ptrace vector interface Sergey Matyukevich
2025-11-08 19:41   ` Sergey Matyukevich
2025-11-19 17:13   ` Andy Chiu
2025-11-19 17:13     ` Andy Chiu
2025-11-20 19:02     ` Sergey Matyukevich
2025-11-20 19:02       ` Sergey Matyukevich
2025-11-08 19:41 ` [PATCH v4 2/9] riscv: ptrace: return ENODATA for inactive vector extension Sergey Matyukevich
2025-11-08 19:41   ` Sergey Matyukevich
2025-11-08 19:41 ` [PATCH v4 3/9] selftests: riscv: verify initial vector state with ptrace Sergey Matyukevich
2025-11-08 19:41   ` Sergey Matyukevich
2025-11-08 19:41 ` [PATCH v4 4/9] riscv: vector: init vector context with proper vlenb Sergey Matyukevich
2025-11-08 19:41   ` Sergey Matyukevich
2025-11-08 19:41 ` Sergey Matyukevich [this message]
2025-11-08 19:41   ` [PATCH v4 5/9] riscv: csr: define vtype registers elements Sergey Matyukevich
2025-11-08 19:41 ` [PATCH v4 6/9] riscv: ptrace: validate input vector csr registers Sergey Matyukevich
2025-11-08 19:41   ` Sergey Matyukevich
2025-11-08 19:41 ` [PATCH v4 7/9] selftests: riscv: verify ptrace rejects invalid vector csr inputs Sergey Matyukevich
2025-11-08 19:41   ` Sergey Matyukevich
2025-11-08 19:41 ` [PATCH v4 8/9] selftests: riscv: verify ptrace accepts valid vector csr values Sergey Matyukevich
2025-11-08 19:41   ` Sergey Matyukevich
2025-11-08 19:41 ` [PATCH v4 9/9] selftests: riscv: verify syscalls discard vector context Sergey Matyukevich
2025-11-08 19:41   ` Sergey Matyukevich

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