From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <linux-cxl@vger.kernel.org>
Cc: <benjamin.cheatham@amd.com>
Subject: [PATCH 04/17] cxl/core: Add CXL.cache device struct
Date: Tue, 11 Nov 2025 15:40:19 -0600 [thread overview]
Message-ID: <20251111214032.8188-5-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20251111214032.8188-1-Benjamin.Cheatham@amd.com>
Add a new CXL.cache device (struct cxl_cachedev) that is the cache
analogue to struct cxl_memdev. This device will be created by
endpoint vendor-specific drivers to enable and manage the cache
capabilities of the endpoint.
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
drivers/cxl/core/Makefile | 1 +
drivers/cxl/core/cachedev.c | 95 +++++++++++++++++++++++++++++++++++++
drivers/cxl/core/port.c | 3 ++
drivers/cxl/cxl.h | 3 ++
drivers/cxl/cxlcache.h | 25 ++++++++++
drivers/cxl/private.h | 4 ++
6 files changed, 131 insertions(+)
create mode 100644 drivers/cxl/core/cachedev.c
diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
index 5ad8fef210b5..94db05d1f351 100644
--- a/drivers/cxl/core/Makefile
+++ b/drivers/cxl/core/Makefile
@@ -9,6 +9,7 @@ cxl_core-y := port.o
cxl_core-y += pmem.o
cxl_core-y += regs.o
cxl_core-y += memdev.o
+cxl_core-y += cachedev.o
cxl_core-y += mbox.o
cxl_core-y += pci.o
cxl_core-y += hdm.o
diff --git a/drivers/cxl/core/cachedev.c b/drivers/cxl/core/cachedev.c
new file mode 100644
index 000000000000..5693a63baa9b
--- /dev/null
+++ b/drivers/cxl/core/cachedev.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (C) 2025 Advanced Micro Devices, Inc. */
+#include <linux/device.h>
+#include <linux/pci.h>
+
+#include "../cxlcache.h"
+#include "private.h"
+
+static DEFINE_IDA(cxl_cachedev_ida);
+
+static void cxl_cachedev_release(struct device *dev)
+{
+ struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev);
+
+ ida_free(&cxl_cachedev_ida, cxlcd->id);
+ kfree(cxlcd);
+}
+
+static void cxl_cachedev_unregister(void *dev)
+{
+ struct cxl_cachedev *cxlcd = dev;
+
+ cxlcd->cxlds = NULL;
+ device_del(&cxlcd->dev);
+ put_device(&cxlcd->dev);
+}
+
+static char *cxl_cachedev_devnode(const struct device *dev, umode_t *mode,
+ kuid_t *uid, kgid_t *gid)
+{
+ return kasprintf(GFP_KERNEL, "cxl/%s", dev_name(dev));
+}
+
+static const struct device_type cxl_cachedev_type = {
+ .name = "cxl_cachedev",
+ .release = cxl_cachedev_release,
+ .devnode = cxl_cachedev_devnode,
+};
+
+bool is_cxl_cachedev(const struct device *dev)
+{
+ return dev->type == &cxl_cachedev_type;
+}
+EXPORT_SYMBOL_NS_GPL(is_cxl_cachedev, "CXL");
+
+static struct lock_class_key cxl_cachedev_key;
+
+struct cxl_cachedev *cxl_cachedev_alloc(struct cxl_dev_state *cxlds)
+{
+ struct device *dev;
+ int rc;
+
+ struct cxl_cachedev *cxlcd __free(kfree) =
+ kzalloc(sizeof(*cxlcd), GFP_KERNEL);
+ if (!cxlcd)
+ return ERR_PTR(-ENOMEM);
+
+ rc = ida_alloc(&cxl_cachedev_ida, GFP_KERNEL);
+ if (rc < 0)
+ return ERR_PTR(rc);
+
+ cxlcd->id = rc;
+ cxlcd->depth = -1;
+ cxlcd->cxlds = cxlds;
+ cxlds->cxlcd = cxlcd;
+ cxlcd->endpoint = ERR_PTR(-ENXIO);
+
+ dev = &cxlcd->dev;
+ device_initialize(dev);
+ lockdep_set_class(&dev->mutex, &cxl_cachedev_key);
+ dev->parent = cxlds->dev;
+ dev->bus = &cxl_bus_type;
+ dev->type = &cxl_cachedev_type;
+ device_set_pm_not_required(dev);
+
+ return_ptr(cxlcd);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_cachedev_alloc, "CXL");
+
+struct cxl_cachedev *devm_cxl_cachedev_add_or_reset(struct device *host,
+ struct cxl_cachedev *cxlcd)
+{
+ int rc;
+
+ rc = device_add(&cxlcd->dev);
+ if (rc)
+ return ERR_PTR(rc);
+
+ rc = devm_add_action_or_reset(host, cxl_cachedev_unregister, cxlcd);
+ if (rc)
+ return ERR_PTR(rc);
+
+ return cxlcd;
+}
+EXPORT_SYMBOL_NS_GPL(devm_cxl_cachedev_add_or_reset, "CXL");
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 8128fd2b5b31..603cf862e311 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -11,6 +11,7 @@
#include <linux/idr.h>
#include <linux/node.h>
#include <cxl/einj.h>
+#include <cxlcache.h>
#include <cxlmem.h>
#include <cxlpci.h>
#include <cxl.h>
@@ -77,6 +78,8 @@ static int cxl_device_id(const struct device *dev)
return CXL_DEVICE_REGION;
if (dev->type == &cxl_pmu_type)
return CXL_DEVICE_PMU;
+ if (is_cxl_cachedev(dev))
+ return CXL_DEVICE_ACCELERATOR;
return 0;
}
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 259d806fb3e3..4cf8ca3a2494 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -779,6 +779,7 @@ struct cxl_cache_state {
*
* @dev: The device associated with this CXL state
* @cxlmd: The device representing the CXL.mem capabilities of @dev
+ * @cxlcd: The device representing the CXL.cache capabilities of @dev
* @reg_map: component and ras register mapping parameters
* @regs: Parsed register blocks
* @cxl_dvsec: Offset to the PCIe device DVSEC
@@ -796,6 +797,7 @@ struct cxl_cache_state {
struct cxl_dev_state {
struct device *dev;
struct cxl_memdev *cxlmd;
+ struct cxl_cachedev *cxlcd;
struct cxl_register_map reg_map;
struct cxl_regs regs;
int cxl_dvsec;
@@ -982,6 +984,7 @@ void cxl_driver_unregister(struct cxl_driver *cxl_drv);
#define CXL_DEVICE_PMEM_REGION 7
#define CXL_DEVICE_DAX_REGION 8
#define CXL_DEVICE_PMU 9
+#define CXL_DEVICE_ACCELERATOR 10
#define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
#define CXL_MODALIAS_FMT "cxl:t%d"
diff --git a/drivers/cxl/cxlcache.h b/drivers/cxl/cxlcache.h
index 8f8597755947..24ec8dddefe7 100644
--- a/drivers/cxl/cxlcache.h
+++ b/drivers/cxl/cxlcache.h
@@ -3,5 +3,30 @@
#define __CXL_CACHE_H__
#include "cxl.h"
+/**
+ * struct cxl_cachedev - CXL bus object representing a cache-capable CXL device
+ * @dev: driver core device object
+ * @cxlds: device state backing this device
+ * @endpoint: connection to the CXL port topology for this device
+ * @ops: caller specific probe routine
+ * @id: id number of this cachedev instance
+ * @depth: endpoint port depth in hierarchy
+ */
+struct cxl_cachedev {
+ struct device dev;
+ struct cxl_dev_state *cxlds;
+ struct cxl_port *endpoint;
+ const struct cxl_dev_ops *ops;
+ int id;
+ int depth;
+};
+
+static inline struct cxl_cachedev *to_cxl_cachedev(struct device *dev)
+{
+ return container_of(dev, struct cxl_cachedev, dev);
+}
+
+bool is_cxl_cachedev(const struct device *dev);
+
int cxl_accel_read_cache_info(struct cxl_dev_state *cxlds);
#endif
diff --git a/drivers/cxl/private.h b/drivers/cxl/private.h
index ff517452e735..25e6bce2457f 100644
--- a/drivers/cxl/private.h
+++ b/drivers/cxl/private.h
@@ -12,4 +12,8 @@
#define __CXL_PRIVATE_H__
int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
struct cxl_dport *parent_dport);
+
+struct cxl_cachedev *cxl_cachedev_alloc(struct cxl_dev_state *cxlds);
+struct cxl_cachedev *devm_cxl_cachedev_add_or_reset(struct device *host,
+ struct cxl_cachedev *cxlcd);
#endif /* __CXL_PRIVATE_H__ */
--
2.51.1
next prev parent reply other threads:[~2025-11-11 21:41 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-11 21:40 [RFC v2 PATCH 00/17] Initial CXL.cache device support Ben Cheatham
2025-11-11 21:40 ` [PATCH 01/17] cxl/port: Arrange for always synchronous endpoint attach Ben Cheatham
2025-11-17 15:56 ` Jonathan Cameron
2025-11-11 21:40 ` [PATCH 02/17] cxl: Move struct cxl_dev_state definition Ben Cheatham
2025-11-11 21:40 ` [PATCH 03/17] cxl/core: Add function for getting CXL cache info Ben Cheatham
2025-12-17 16:09 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` Ben Cheatham [this message]
2025-12-17 16:14 ` [PATCH 04/17] cxl/core: Add CXL.cache device struct Jonathan Cameron
2025-11-11 21:40 ` [PATCH 05/17] cxl/cache: Add cxl_cache driver Ben Cheatham
2025-12-17 16:17 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 06/17] cxl: Replace cxl_mem_find_port() with cxl_dev_find_port() Ben Cheatham
2025-12-17 16:18 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 07/17] cxl: Change cxl_ep_load() to use struct device * parameter Ben Cheatham
2025-11-11 21:40 ` [PATCH 08/17] cxl/core: Update devm_cxl_enumerate_ports() Ben Cheatham
2025-11-11 21:40 ` [PATCH 09/17] cxl/port: Split endpoint port probe on device type Ben Cheatham
2025-11-11 21:40 ` [PATCH 10/17] cxl/cache, mem: Prevent RAS register mapping race Ben Cheatham
2025-12-17 16:23 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 11/17] cxl/core, port: Update devm_cxl_add_endpoint() Ben Cheatham
2025-11-11 21:40 ` [PATCH 12/17] cxl/core: Add CXL snoop filter setup and allocation Ben Cheatham
2025-12-17 16:35 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 13/17] cxl/core: Add cache id verification Ben Cheatham
2025-12-22 13:47 ` Jonathan Cameron
2026-01-05 21:16 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 14/17] cxl/port: Add cache id programming Ben Cheatham
2025-11-11 21:40 ` [PATCH 15/17] cxl/port: Bypass cache id for singleton cache devices Ben Cheatham
2025-11-11 21:40 ` [PATCH 16/17] cxl/core: Add cache device attributes Ben Cheatham
2025-12-17 16:12 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 17/17] cxl/core: Add cache device cache management attributes Ben Cheatham
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