From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <linux-cxl@vger.kernel.org>
Cc: <benjamin.cheatham@amd.com>
Subject: [PATCH 08/17] cxl/core: Update devm_cxl_enumerate_ports()
Date: Tue, 11 Nov 2025 15:40:23 -0600 [thread overview]
Message-ID: <20251111214032.8188-9-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20251111214032.8188-1-Benjamin.Cheatham@amd.com>
Update devm_cxl_enumerate_ports() to handle cxl_cachedev devices. After
this commit cxl_cachedev's will be added to the CXL port hierarchy, but
immediately fail endpoint port probe.
Endpoint port probe will be updated to allow cxl cache devices in a
following commit.
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
drivers/cxl/cache.c | 16 ++++++
drivers/cxl/core/port.c | 109 ++++++++++++++++++++++++++--------------
drivers/cxl/cxl.h | 3 +-
drivers/cxl/mem.c | 2 +-
drivers/cxl/port.c | 3 ++
5 files changed, 94 insertions(+), 39 deletions(-)
diff --git a/drivers/cxl/cache.c b/drivers/cxl/cache.c
index 6f410fae9437..630452d53acc 100644
--- a/drivers/cxl/cache.c
+++ b/drivers/cxl/cache.c
@@ -56,6 +56,22 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_add_cachedev, "CXL");
static int cxl_cache_probe(struct device *dev)
{
+ struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev);
+ struct cxl_dev_state *cxlds = cxlcd->cxlds;
+ struct cxl_dport *dport;
+ int rc;
+
+ rc = devm_cxl_enumerate_ports(dev, cxlds);
+ if (rc)
+ return rc;
+
+ struct cxl_port *parent_port __free(put_cxl_port) =
+ cxl_dev_find_port(dev, &dport);
+ if (!parent_port) {
+ dev_err(dev, "CXL port topology not found\n");
+ return -ENXIO;
+ }
+
return 0;
}
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 2cccce49e3b4..e79ec29d0bb6 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -844,6 +844,45 @@ static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport)
&cxl_einj_inject_fops);
}
+static bool is_cxl_ep_device(struct device *dev)
+{
+ return is_cxl_memdev(dev) || is_cxl_cachedev(dev);
+}
+
+static int cxl_port_setup_endpoint(struct cxl_port *port)
+{
+ struct device *uport_dev = port->uport_dev;
+ struct cxl_dev_state *cxlds;
+ struct cxl_cachedev *cxlcd;
+ struct cxl_memdev *cxlmd;
+ int rc;
+
+ rc = dev_set_name(&port->dev, "endpoint%d", port->id);
+ if (rc)
+ return rc;
+
+ /*
+ * The endpoint driver already enumerated the component and RAS
+ * registers. Reuse that enumeration while prepping them to be
+ * mapped by the cxl_port driver.
+ */
+ if (is_cxl_memdev(uport_dev)) {
+ cxlmd = to_cxl_memdev(uport_dev);
+ cxlds = cxlmd->cxlds;
+
+ cxlmd->endpoint = port;
+ } else {
+ cxlcd = to_cxl_cachedev(uport_dev);
+ cxlds = cxlcd->cxlds;
+
+ cxlcd->endpoint = port;
+ }
+
+ port->reg_map = cxlds->reg_map;
+ port->reg_map.host = &port->dev;
+ return 0;
+}
+
static int cxl_port_add(struct cxl_port *port,
resource_size_t component_reg_phys,
struct cxl_dport *parent_dport)
@@ -851,22 +890,10 @@ static int cxl_port_add(struct cxl_port *port,
struct device *dev __free(put_device) = &port->dev;
int rc;
- if (is_cxl_memdev(port->uport_dev)) {
- struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
- struct cxl_dev_state *cxlds = cxlmd->cxlds;
-
- rc = dev_set_name(dev, "endpoint%d", port->id);
+ if (is_cxl_ep_device(port->uport_dev)) {
+ rc = cxl_port_setup_endpoint(port);
if (rc)
return rc;
-
- /*
- * The endpoint driver already enumerated the component and RAS
- * registers. Reuse that enumeration while prepping them to be
- * mapped by the cxl_port driver.
- */
- port->reg_map = cxlds->reg_map;
- port->reg_map.host = &port->dev;
- cxlmd->endpoint = port;
} else if (parent_dport) {
rc = dev_set_name(dev, "port%d", port->id);
if (rc)
@@ -1603,7 +1630,8 @@ static int update_decoder_targets(struct device *dev, void *data)
DEFINE_FREE(del_cxl_dport, struct cxl_dport *, if (!IS_ERR_OR_NULL(_T)) del_dport(_T))
static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
- struct device *dport_dev)
+ struct device *dport_dev,
+ struct device *ep_dev)
{
struct cxl_dport *dport;
int rc;
@@ -1624,6 +1652,10 @@ static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
if (IS_ERR(new_dport))
return new_dport;
+ /* CXL.cache devices aren't expected to have HDM decoders */
+ if (ep_dev && is_cxl_cachedev(ep_dev))
+ return no_free_ptr(new_dport);
+
cxl_switch_parse_cdat(new_dport);
if (ida_is_empty(&port->decoder_ida)) {
@@ -1655,9 +1687,10 @@ static struct cxl_dport *devm_cxl_create_port(struct device *ep_dev,
device_lock_assert(&parent_port->dev);
if (!parent_port->dev.driver) {
dev_warn(ep_dev,
- "port %s:%s:%s disabled, failed to enumerate CXL.mem\n",
+ "port %s:%s:%s disabled, failed to enumerate CXL.%s\n",
dev_name(&parent_port->dev), dev_name(uport_dev),
- dev_name(dport_dev));
+ dev_name(dport_dev),
+ is_cxl_memdev(ep_dev) ? "mem" : "cache");
}
struct cxl_port *port __free(put_cxl_port) =
@@ -1688,10 +1721,10 @@ static struct cxl_dport *devm_cxl_create_port(struct device *ep_dev,
}
guard(device)(&port->dev);
- return cxl_port_add_dport(port, dport_dev);
+ return cxl_port_add_dport(port, dport_dev, ep_dev);
}
-static int add_port_attach_ep(struct cxl_memdev *cxlmd,
+static int add_port_attach_ep(struct device *ep_dev,
struct device *uport_dev,
struct device *dport_dev)
{
@@ -1705,8 +1738,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd,
* CXL-root 'cxl_port' on a previous iteration, fail for now to
* be re-probed after platform driver attaches.
*/
- dev_dbg(&cxlmd->dev, "%s is a root dport\n",
- dev_name(dport_dev));
+ dev_dbg(ep_dev, "%s is a root dport\n", dev_name(dport_dev));
return -ENXIO;
}
@@ -1720,12 +1752,13 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd,
scoped_guard(device, &parent_port->dev) {
parent_dport = cxl_find_dport_by_dev(parent_port, dparent);
if (!parent_dport) {
- parent_dport = cxl_port_add_dport(parent_port, dparent);
+ parent_dport = cxl_port_add_dport(parent_port, dparent,
+ ep_dev);
if (IS_ERR(parent_dport))
return PTR_ERR(parent_dport);
}
- dport = devm_cxl_create_port(&cxlmd->dev, parent_port,
+ dport = devm_cxl_create_port(ep_dev, parent_port,
parent_dport, uport_dev,
dport_dev);
if (IS_ERR(dport)) {
@@ -1736,7 +1769,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd,
}
}
- rc = cxl_add_ep(dport, &cxlmd->dev);
+ rc = cxl_add_ep(dport, ep_dev);
if (rc == -EBUSY) {
/*
* "can't" happen, but this error code means
@@ -1756,7 +1789,7 @@ static struct cxl_dport *find_or_add_dport(struct cxl_port *port,
device_lock_assert(&port->dev);
dport = cxl_find_dport_by_dev(port, dport_dev);
if (!dport) {
- dport = cxl_port_add_dport(port, dport_dev);
+ dport = cxl_port_add_dport(port, dport_dev, NULL);
if (IS_ERR(dport))
return dport;
@@ -1767,9 +1800,8 @@ static struct cxl_dport *find_or_add_dport(struct cxl_port *port,
return dport;
}
-int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
+int devm_cxl_enumerate_ports(struct device *ep_dev, struct cxl_dev_state *cxlds)
{
- struct device *dev = &cxlmd->dev;
struct device *iter;
int rc;
@@ -1777,12 +1809,15 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
* Skip intermediate port enumeration in the RCH case, there
* are no ports in between a host bridge and an endpoint.
*/
- if (cxlmd->cxlds->rcd)
+ if (cxlds->rcd)
return 0;
- rc = devm_add_action_or_reset(&cxlmd->dev, cxl_detach_ep, cxlmd);
- if (rc)
- return rc;
+ if (is_cxl_memdev(ep_dev)) {
+ rc = devm_add_action_or_reset(ep_dev, cxl_detach_ep,
+ to_cxl_memdev(ep_dev));
+ if (rc)
+ return rc;
+ }
/*
* Scan for and add all cxl_ports in this device's ancestry.
@@ -1790,7 +1825,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
* attempt fails.
*/
retry:
- for (iter = dev; iter; iter = grandparent(iter)) {
+ for (iter = ep_dev; iter; iter = grandparent(iter)) {
struct device *dport_dev = grandparent(iter);
struct device *uport_dev;
struct cxl_dport *dport;
@@ -1800,18 +1835,18 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
uport_dev = dport_dev->parent;
if (!uport_dev) {
- dev_warn(dev, "at %s no parent for dport: %s\n",
+ dev_warn(ep_dev, "at %s no parent for dport: %s\n",
dev_name(iter), dev_name(dport_dev));
return -ENXIO;
}
- dev_dbg(dev, "scan: iter: %s dport_dev: %s parent: %s\n",
+ dev_dbg(ep_dev, "scan: iter: %s dport_dev: %s parent: %s\n",
dev_name(iter), dev_name(dport_dev),
dev_name(uport_dev));
struct cxl_port *port __free(put_cxl_port) =
find_cxl_port_by_uport(uport_dev);
if (port) {
- dev_dbg(&cxlmd->dev,
+ dev_dbg(ep_dev,
"found already registered port %s:%s\n",
dev_name(&port->dev),
dev_name(port->uport_dev));
@@ -1829,7 +1864,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
}
}
- rc = cxl_add_ep(dport, &cxlmd->dev);
+ rc = cxl_add_ep(dport, ep_dev);
/*
* If the endpoint already exists in the port's list,
@@ -1850,7 +1885,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
return 0;
}
- rc = add_port_attach_ep(cxlmd, uport_dev, dport_dev);
+ rc = add_port_attach_ep(ep_dev, uport_dev, dport_dev);
/* port missing, try to add parent */
if (rc == -EAGAIN)
continue;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 5ef0fb71af91..6c7b8278bec3 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -885,7 +885,8 @@ DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device
DEFINE_FREE(put_cxl_root_decoder, struct cxl_root_decoder *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev))
DEFINE_FREE(put_cxl_region, struct cxl_region *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev))
-int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
+int devm_cxl_enumerate_ports(struct device *ep_dev,
+ struct cxl_dev_state *cxlds);
void cxl_bus_rescan(void);
void cxl_bus_drain(void);
struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev,
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index d12c96b68c82..3b230f8c5925 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -104,7 +104,7 @@ static int cxl_mem_probe(struct device *dev)
if (rc)
return rc;
- rc = devm_cxl_enumerate_ports(cxlmd);
+ rc = devm_cxl_enumerate_ports(dev, cxlds);
if (rc)
return rc;
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index c2fbdbfe0b6b..efea9b04b323 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -74,6 +74,9 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
int rc;
+ if (!is_cxl_memdev(port->uport_dev))
+ return -EOPNOTSUPP;
+
/* Cache the data early to ensure is_visible() works */
read_cdat_data(port);
cxl_endpoint_parse_cdat(port);
--
2.51.1
next prev parent reply other threads:[~2025-11-11 21:42 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-11 21:40 [RFC v2 PATCH 00/17] Initial CXL.cache device support Ben Cheatham
2025-11-11 21:40 ` [PATCH 01/17] cxl/port: Arrange for always synchronous endpoint attach Ben Cheatham
2025-11-17 15:56 ` Jonathan Cameron
2025-11-11 21:40 ` [PATCH 02/17] cxl: Move struct cxl_dev_state definition Ben Cheatham
2025-11-11 21:40 ` [PATCH 03/17] cxl/core: Add function for getting CXL cache info Ben Cheatham
2025-12-17 16:09 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 04/17] cxl/core: Add CXL.cache device struct Ben Cheatham
2025-12-17 16:14 ` Jonathan Cameron
2025-11-11 21:40 ` [PATCH 05/17] cxl/cache: Add cxl_cache driver Ben Cheatham
2025-12-17 16:17 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 06/17] cxl: Replace cxl_mem_find_port() with cxl_dev_find_port() Ben Cheatham
2025-12-17 16:18 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 07/17] cxl: Change cxl_ep_load() to use struct device * parameter Ben Cheatham
2025-11-11 21:40 ` Ben Cheatham [this message]
2025-11-11 21:40 ` [PATCH 09/17] cxl/port: Split endpoint port probe on device type Ben Cheatham
2025-11-11 21:40 ` [PATCH 10/17] cxl/cache, mem: Prevent RAS register mapping race Ben Cheatham
2025-12-17 16:23 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 11/17] cxl/core, port: Update devm_cxl_add_endpoint() Ben Cheatham
2025-11-11 21:40 ` [PATCH 12/17] cxl/core: Add CXL snoop filter setup and allocation Ben Cheatham
2025-12-17 16:35 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 13/17] cxl/core: Add cache id verification Ben Cheatham
2025-12-22 13:47 ` Jonathan Cameron
2026-01-05 21:16 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 14/17] cxl/port: Add cache id programming Ben Cheatham
2025-11-11 21:40 ` [PATCH 15/17] cxl/port: Bypass cache id for singleton cache devices Ben Cheatham
2025-11-11 21:40 ` [PATCH 16/17] cxl/core: Add cache device attributes Ben Cheatham
2025-12-17 16:12 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 17/17] cxl/core: Add cache device cache management attributes Ben Cheatham
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251111214032.8188-9-Benjamin.Cheatham@amd.com \
--to=benjamin.cheatham@amd.com \
--cc=linux-cxl@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.