From: Dave Airlie <airlied@gmail.com>
To: dri-devel@lists.freedesktop.org
Subject: [PATCH 1/2] drm/scdc: add frl config/status registers to scdc header.
Date: Fri, 14 Nov 2025 13:53:37 +1000 [thread overview]
Message-ID: <20251114035338.15144-1-airlied@gmail.com> (raw)
From: Dave Airlie <airlied@redhat.com>
These are sourced from publically available presentations like
https://www.ti.com/content/dam/videos/external-videos/en-us/11/3816841626001/overview-ddc-bus-hdmi-systems.mp4/subassets/overview-ddc-bus-hdmi-systems-presentation.pdf
Document in the kernel in case they are of use to someone.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
include/drm/display/drm_scdc.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/drm/display/drm_scdc.h b/include/drm/display/drm_scdc.h
index 3d58f37e8ed8..3b6a8a4a4bca 100644
--- a/include/drm/display/drm_scdc.h
+++ b/include/drm/display/drm_scdc.h
@@ -29,6 +29,8 @@
#define SCDC_SOURCE_VERSION 0x02
#define SCDC_UPDATE_0 0x10
+#define SCDC_FLT_UPDATE (1 << 5)
+#define SCDC_FRL_START (1 << 4)
#define SCDC_READ_REQUEST_TEST (1 << 2)
#define SCDC_CED_UPDATE (1 << 1)
#define SCDC_STATUS_UPDATE (1 << 0)
@@ -46,7 +48,20 @@
#define SCDC_CONFIG_0 0x30
#define SCDC_READ_REQUEST_ENABLE (1 << 0)
+#define SCDC_CONFIG_FRL 0x31
+#define SCDC_FRL_RATE(x) (((x) & 0x7) << 0)
+#define SCDC_FRL_RATE_DISABLE 0
+#define SCDC_FRL_RATE_FIXED_3LANE_3GB 1
+#define SCDC_FRL_RATE_FIXED_3LANE_6GB 2
+#define SCDC_FRL_RATE_FIXED_4LANE_6GB 3
+#define SCDC_FRL_RATE_FIXED_4LANE_8GB 4
+#define SCDC_FRL_RATE_FIXED_4LANE_10GB 5
+#define SCDC_FRL_RATE_FIXED_4LANE_12GB 6
+#define SCDC_FRL_FFE_LEVELS(x) (((x) & 0xF) << 4)
+
#define SCDC_STATUS_FLAGS_0 0x40
+#define SCDC_FLT_READY (1 << 6)
+#define SCDC_LANE3_LOCK (1 << 4)
#define SCDC_CH2_LOCK (1 << 3)
#define SCDC_CH1_LOCK (1 << 2)
#define SCDC_CH0_LOCK (1 << 1)
@@ -55,6 +70,9 @@
#define SCDC_STATUS_FLAGS_1 0x41
+#define SCDC_LN_LTP_01 0x41
+#define SCDC_LN_LTP_23 0x42
+
#define SCDC_ERR_DET_0_L 0x50
#define SCDC_ERR_DET_0_H 0x51
#define SCDC_ERR_DET_1_L 0x52
--
2.51.1
next reply other threads:[~2025-11-14 3:53 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-14 3:53 Dave Airlie [this message]
2025-11-14 3:53 ` [PATCH 2/2] amd/dc: add frl bits to the registers Dave Airlie
2025-11-21 14:31 ` Derek Foreman
2025-11-21 14:31 ` [PATCH 1/2] drm/scdc: add frl config/status registers to scdc header Derek Foreman
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