From: Anand Moon <linux.amoon@gmail.com>
To: "Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
linux-pci@vger.kernel.org (open list:PCIE DRIVER FOR ROCKCHIP),
linux-rockchip@lists.infradead.org (open list:PCIE DRIVER FOR
ROCKCHIP),
linux-arm-kernel@lists.infradead.org (moderated
list:ARM/Rockchip SoC support),
linux-kernel@vger.kernel.org (open list)
Cc: Anand Moon <linux.amoon@gmail.com>
Subject: [RFC v1 0/5] Fix some register offset as per RK3399 TRM part 2
Date: Mon, 17 Nov 2025 23:40:08 +0530 [thread overview]
Message-ID: <20251117181023.482138-1-linux.amoon@gmail.com> (raw)
In order to enable ASPM we need to fix the register offset as
RK3399 TRM part 2 - PCIe Controller.
Tested on Radxa Rock Pi 4b.
Thanks
-Anand
Anand Moon (5):
PCI: rockchip: Fix Link Control register offset and enable ASPM/CLKREQ
PCI: rockchip: Fix Device Control register offset for Max payload size
PCI: rockchip: Fix Slot Capability Register offset for slot power
limit
PCI: rockchip: Fix Link Control and Status Register 2 for target link
speed
PCI: rockchip: Fix Linkwidth Control Register offset for Retrain Link
drivers/pci/controller/pcie-rockchip-host.c | 31 +++++++++++----------
drivers/pci/controller/pcie-rockchip.h | 5 ++++
2 files changed, 21 insertions(+), 15 deletions(-)
base-commit: e7c375b181600caf135cfd03eadbc45eb530f2cb
--
2.50.1
WARNING: multiple messages have this Message-ID (diff)
From: Anand Moon <linux.amoon@gmail.com>
To: "Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
linux-pci@vger.kernel.org (open list:PCIE DRIVER FOR ROCKCHIP),
linux-rockchip@lists.infradead.org (open list:PCIE DRIVER FOR
ROCKCHIP),
linux-arm-kernel@lists.infradead.org (moderated
list:ARM/Rockchip SoC support),
linux-kernel@vger.kernel.org (open list)
Cc: Anand Moon <linux.amoon@gmail.com>
Subject: [RFC v1 0/5] Fix some register offset as per RK3399 TRM part 2
Date: Mon, 17 Nov 2025 23:40:08 +0530 [thread overview]
Message-ID: <20251117181023.482138-1-linux.amoon@gmail.com> (raw)
In order to enable ASPM we need to fix the register offset as
RK3399 TRM part 2 - PCIe Controller.
Tested on Radxa Rock Pi 4b.
Thanks
-Anand
Anand Moon (5):
PCI: rockchip: Fix Link Control register offset and enable ASPM/CLKREQ
PCI: rockchip: Fix Device Control register offset for Max payload size
PCI: rockchip: Fix Slot Capability Register offset for slot power
limit
PCI: rockchip: Fix Link Control and Status Register 2 for target link
speed
PCI: rockchip: Fix Linkwidth Control Register offset for Retrain Link
drivers/pci/controller/pcie-rockchip-host.c | 31 +++++++++++----------
drivers/pci/controller/pcie-rockchip.h | 5 ++++
2 files changed, 21 insertions(+), 15 deletions(-)
base-commit: e7c375b181600caf135cfd03eadbc45eb530f2cb
--
2.50.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next reply other threads:[~2025-11-17 18:10 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-17 18:10 Anand Moon [this message]
2025-11-17 18:10 ` [RFC v1 0/5] Fix some register offset as per RK3399 TRM part 2 Anand Moon
2025-11-17 18:10 ` [RFC v1 1/5] PCI: rockchip: Fix Link Control register offset and enable ASPM/CLKREQ Anand Moon
2025-11-17 18:10 ` Anand Moon
2025-11-18 17:50 ` Bjorn Helgaas
2025-11-18 17:50 ` Bjorn Helgaas
2025-11-19 14:19 ` Anand Moon
2025-11-19 14:19 ` Anand Moon
2025-11-20 3:44 ` Bjorn Helgaas
2025-11-20 3:44 ` Bjorn Helgaas
2025-11-20 13:58 ` Anand Moon
2025-11-20 13:58 ` Anand Moon
2025-11-26 10:33 ` Anand Moon
2025-11-26 10:33 ` Anand Moon
2025-11-26 14:39 ` Bjorn Helgaas
2025-11-26 14:39 ` Bjorn Helgaas
2025-11-27 7:34 ` Anand Moon
2025-11-27 7:34 ` Anand Moon
2025-11-17 18:10 ` [RFC v1 2/5] PCI: rockchip: Fix Device Control register offset for Max payload size Anand Moon
2025-11-17 18:10 ` Anand Moon
2025-11-18 0:50 ` Bjorn Helgaas
2025-11-18 0:50 ` Bjorn Helgaas
2025-11-18 11:16 ` Anand Moon
2025-11-18 11:16 ` Anand Moon
2025-11-17 18:10 ` [RFC v1 3/5] PCI: rockchip: Fix Slot Capability Register offset for slot power limit Anand Moon
2025-11-17 18:10 ` Anand Moon
2025-11-17 18:10 ` [RFC v1 4/5] PCI: rockchip: Fix Link Control and Status Register 2 for target link speed Anand Moon
2025-11-17 18:10 ` Anand Moon
2025-11-17 18:10 ` [RFC v1 5/5] PCI: rockchip: Fix Linkwidth Control Register offset for Retrain Link Anand Moon
2025-11-17 18:10 ` Anand Moon
2025-11-18 0:54 ` [RFC v1 0/5] Fix some register offset as per RK3399 TRM part 2 Shawn Lin
2025-11-18 0:54 ` Shawn Lin
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