* Re: [PATCH 2/2] mmc: dw_mmc: add dw_mci_prepare_desc() for both of 32bit and 64bit DMA
@ 2025-11-22 20:26 kernel test robot
0 siblings, 0 replies; 3+ messages in thread
From: kernel test robot @ 2025-11-22 20:26 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "low confidence static check warning: drivers/mmc/host/dw_mmc.c:609:29: sparse: sparse: cannot dereference this type"
::::::
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <1763540498-84315-2-git-send-email-shawn.lin@rock-chips.com>
References: <1763540498-84315-2-git-send-email-shawn.lin@rock-chips.com>
TO: Shawn Lin <shawn.lin@rock-chips.com>
TO: Ulf Hansson <ulf.hansson@linaro.org>
CC: linux-mmc@vger.kernel.org
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Shawn Lin <shawn.lin@rock-chips.com>
Hi Shawn,
kernel test robot noticed the following build warnings:
[auto build test WARNING on linus/master]
[also build test WARNING on v6.18-rc6 next-20251121]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Shawn-Lin/mmc-dw_mmc-add-dw_mci_prepare_desc-for-both-of-32bit-and-64bit-DMA/20251119-163950
base: linus/master
patch link: https://lore.kernel.org/r/1763540498-84315-2-git-send-email-shawn.lin%40rock-chips.com
patch subject: [PATCH 2/2] mmc: dw_mmc: add dw_mci_prepare_desc() for both of 32bit and 64bit DMA
:::::: branch date: 4 days ago
:::::: commit date: 4 days ago
config: m68k-randconfig-r132-20251122 (https://download.01.org/0day-ci/archive/20251123/202511230424.HoqupIig-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 12.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251123/202511230424.HoqupIig-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202511230424.HoqupIig-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
drivers/mmc/host/dw_mmc.c:609:29: sparse: sparse: incompatible types in conditional expression (different base types):
drivers/mmc/host/dw_mmc.c:609:29: sparse: unsigned int *
drivers/mmc/host/dw_mmc.c:609:29: sparse: restricted __le32 *
drivers/mmc/host/dw_mmc.c:609:29: sparse: sparse: cast from unknown type
>> drivers/mmc/host/dw_mmc.c:609:29: sparse: sparse: cannot dereference this type
vim +609 drivers/mmc/host/dw_mmc.c
3b2a067b98b45f Shawn Lin 2016-09-02 577
c4eee1cd5533e3 Shawn Lin 2025-11-19 578 static inline int dw_mci_prepare_desc(struct dw_mci *host, struct mmc_data *data,
c4eee1cd5533e3 Shawn Lin 2025-11-19 579 unsigned int sg_len, bool is_64bit)
f95f3850f7a9e1 Will Newton 2011-01-02 580 {
5959b32e3636f9 Alexey Brodkin 2015-06-25 581 unsigned int desc_len;
c4eee1cd5533e3 Shawn Lin 2025-11-19 582 struct idmac_desc *desc_first, *desc_last, *desc;
c4eee1cd5533e3 Shawn Lin 2025-11-19 583 struct idmac_desc_64addr *desc64_first, *desc64_last, *desc64;
c4eee1cd5533e3 Shawn Lin 2025-11-19 584 u32 val, des0;
ec0baaa6b33932 Shawn Lin 2016-09-02 585 int i;
5959b32e3636f9 Alexey Brodkin 2015-06-25 586
c4eee1cd5533e3 Shawn Lin 2025-11-19 587 if (is_64bit)
c4eee1cd5533e3 Shawn Lin 2025-11-19 588 desc64_first = desc64_last = desc64 = host->sg_cpu;
c4eee1cd5533e3 Shawn Lin 2025-11-19 589 else
5959b32e3636f9 Alexey Brodkin 2015-06-25 590 desc_first = desc_last = desc = host->sg_cpu;
69d99fdcfd7815 Prabu Thangamuthu 2014-10-20 591
5959b32e3636f9 Alexey Brodkin 2015-06-25 592 for (i = 0; i < sg_len; i++) {
69d99fdcfd7815 Prabu Thangamuthu 2014-10-20 593 unsigned int length = sg_dma_len(&data->sg[i]);
0e3a22c044478b Shawn Lin 2015-08-03 594
69d99fdcfd7815 Prabu Thangamuthu 2014-10-20 595 u64 mem_addr = sg_dma_address(&data->sg[i]);
69d99fdcfd7815 Prabu Thangamuthu 2014-10-20 596
5959b32e3636f9 Alexey Brodkin 2015-06-25 597 for ( ; length ; desc++) {
5959b32e3636f9 Alexey Brodkin 2015-06-25 598 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
5959b32e3636f9 Alexey Brodkin 2015-06-25 599 length : DW_MCI_DESC_DATA_LENGTH;
5959b32e3636f9 Alexey Brodkin 2015-06-25 600
5959b32e3636f9 Alexey Brodkin 2015-06-25 601 length -= desc_len;
5959b32e3636f9 Alexey Brodkin 2015-06-25 602
3b2a067b98b45f Shawn Lin 2016-09-02 603 /*
3b2a067b98b45f Shawn Lin 2016-09-02 604 * Wait for the former clear OWN bit operation
3b2a067b98b45f Shawn Lin 2016-09-02 605 * of IDMAC to make sure that this descriptor
3b2a067b98b45f Shawn Lin 2016-09-02 606 * isn't still owned by IDMAC as IDMAC's write
3b2a067b98b45f Shawn Lin 2016-09-02 607 * ops and CPU's read ops are asynchronous.
3b2a067b98b45f Shawn Lin 2016-09-02 608 */
c4eee1cd5533e3 Shawn Lin 2025-11-19 @609 if (readl_poll_timeout_atomic(is_64bit ? &desc64->des0 : &desc->des0,
c4eee1cd5533e3 Shawn Lin 2025-11-19 610 val, IDMAC_OWN_CLR64(val), 10, 100 * USEC_PER_MSEC))
3b2a067b98b45f Shawn Lin 2016-09-02 611 goto err_own_bit;
3b2a067b98b45f Shawn Lin 2016-09-02 612
c4eee1cd5533e3 Shawn Lin 2025-11-19 613 des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
c4eee1cd5533e3 Shawn Lin 2025-11-19 614 if (is_64bit)
c4eee1cd5533e3 Shawn Lin 2025-11-19 615 desc64->des0 = des0;
c4eee1cd5533e3 Shawn Lin 2025-11-19 616 else
c4eee1cd5533e3 Shawn Lin 2025-11-19 617 desc->des0 = cpu_to_le32(des0);
3b2a067b98b45f Shawn Lin 2016-09-02 618
69d99fdcfd7815 Prabu Thangamuthu 2014-10-20 619 /*
c4eee1cd5533e3 Shawn Lin 2025-11-19 620 * 1. Set OWN bit and disable interrupts for this descriptor
c4eee1cd5533e3 Shawn Lin 2025-11-19 621 * 2. Set Buffer length
c4eee1cd5533e3 Shawn Lin 2025-11-19 622 * Set physical address to DMA to/from
69d99fdcfd7815 Prabu Thangamuthu 2014-10-20 623 */
c4eee1cd5533e3 Shawn Lin 2025-11-19 624 if (is_64bit) {
c4eee1cd5533e3 Shawn Lin 2025-11-19 625 desc64->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
c4eee1cd5533e3 Shawn Lin 2025-11-19 626 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc64, desc_len);
c4eee1cd5533e3 Shawn Lin 2025-11-19 627 desc64->des4 = mem_addr & 0xffffffff;
c4eee1cd5533e3 Shawn Lin 2025-11-19 628 desc64->des5 = mem_addr >> 32;
c4eee1cd5533e3 Shawn Lin 2025-11-19 629 } else {
5959b32e3636f9 Alexey Brodkin 2015-06-25 630 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
6687c42fa71acd Ben Dooks 2015-03-25 631 desc->des2 = cpu_to_le32(mem_addr);
c4eee1cd5533e3 Shawn Lin 2025-11-19 632 }
5959b32e3636f9 Alexey Brodkin 2015-06-25 633
5959b32e3636f9 Alexey Brodkin 2015-06-25 634 /* Update physical address for the next desc */
5959b32e3636f9 Alexey Brodkin 2015-06-25 635 mem_addr += desc_len;
5959b32e3636f9 Alexey Brodkin 2015-06-25 636
5959b32e3636f9 Alexey Brodkin 2015-06-25 637 /* Save pointer to the last descriptor */
c4eee1cd5533e3 Shawn Lin 2025-11-19 638 if (is_64bit)
c4eee1cd5533e3 Shawn Lin 2025-11-19 639 desc64_last = desc64;
c4eee1cd5533e3 Shawn Lin 2025-11-19 640 else
5959b32e3636f9 Alexey Brodkin 2015-06-25 641 desc_last = desc;
5959b32e3636f9 Alexey Brodkin 2015-06-25 642 }
f95f3850f7a9e1 Will Newton 2011-01-02 643 }
f95f3850f7a9e1 Will Newton 2011-01-02 644
c4eee1cd5533e3 Shawn Lin 2025-11-19 645 /* Set the first descriptor and the last descriptor */
c4eee1cd5533e3 Shawn Lin 2025-11-19 646 if (is_64bit) {
c4eee1cd5533e3 Shawn Lin 2025-11-19 647 desc64_first->des0 |= IDMAC_DES0_FD;
c4eee1cd5533e3 Shawn Lin 2025-11-19 648 desc64_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
c4eee1cd5533e3 Shawn Lin 2025-11-19 649 desc64_last->des0 |= IDMAC_DES0_LD;
c4eee1cd5533e3 Shawn Lin 2025-11-19 650 } else {
5959b32e3636f9 Alexey Brodkin 2015-06-25 651 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
c4eee1cd5533e3 Shawn Lin 2025-11-19 652 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | IDMAC_DES0_DIC));
5959b32e3636f9 Alexey Brodkin 2015-06-25 653 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
c4eee1cd5533e3 Shawn Lin 2025-11-19 654 }
3b2a067b98b45f Shawn Lin 2016-09-02 655
3b2a067b98b45f Shawn Lin 2016-09-02 656 return 0;
3b2a067b98b45f Shawn Lin 2016-09-02 657 err_own_bit:
3b2a067b98b45f Shawn Lin 2016-09-02 658 /* restore the descriptor chain as it's polluted */
26be9d705f4452 Colin Ian King 2016-11-16 659 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
cc190d4c6499b1 Shawn Lin 2016-09-02 660 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
3b2a067b98b45f Shawn Lin 2016-09-02 661 dw_mci_idmac_init(host);
3b2a067b98b45f Shawn Lin 2016-09-02 662 return -EINVAL;
69d99fdcfd7815 Prabu Thangamuthu 2014-10-20 663 }
f95f3850f7a9e1 Will Newton 2011-01-02 664
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH 1/2] mmc: dw_mmc: Remove unused struct dma_pdata @ 2025-11-19 8:21 Shawn Lin 2025-11-19 8:21 ` [PATCH 2/2] mmc: dw_mmc: add dw_mci_prepare_desc() for both of 32bit and 64bit DMA Shawn Lin 0 siblings, 1 reply; 3+ messages in thread From: Shawn Lin @ 2025-11-19 8:21 UTC (permalink / raw) To: Ulf Hansson; +Cc: linux-mmc, Jaehoon Chung, Shawn Lin Thers is no public user for it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- drivers/mmc/host/dw_mmc.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 648b4a5..b4ceca0 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -255,8 +255,6 @@ struct dw_mci_dma_ops { void (*exit)(struct dw_mci *host); }; -struct dma_pdata; - /* Board platform data */ struct dw_mci_board { unsigned int bus_hz; /* Clock speed at the cclk_in pad */ @@ -276,7 +274,6 @@ struct dw_mci_board { struct reset_control *rstc; struct dw_mci_dma_ops *dma_ops; - struct dma_pdata *data; }; /* Support for longer data read timeout */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] mmc: dw_mmc: add dw_mci_prepare_desc() for both of 32bit and 64bit DMA 2025-11-19 8:21 [PATCH 1/2] mmc: dw_mmc: Remove unused struct dma_pdata Shawn Lin @ 2025-11-19 8:21 ` Shawn Lin 2025-11-20 16:00 ` kernel test robot 0 siblings, 1 reply; 3+ messages in thread From: Shawn Lin @ 2025-11-19 8:21 UTC (permalink / raw) To: Ulf Hansson; +Cc: linux-mmc, Jaehoon Chung, Shawn Lin dw_mci_prepare_desc64() and dw_mci_prepare_desc32() duplicate a lot of code, add a new dw_mci_prepare_desc() to save the bits. No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- drivers/mmc/host/dw_mmc.c | 147 ++++++++++++++-------------------------------- 1 file changed, 43 insertions(+), 104 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 9e74b67..80d3851 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -575,16 +575,19 @@ static int dw_mci_idmac_init(struct dw_mci *host) return 0; } -static inline int dw_mci_prepare_desc64(struct dw_mci *host, - struct mmc_data *data, - unsigned int sg_len) +static inline int dw_mci_prepare_desc(struct dw_mci *host, struct mmc_data *data, + unsigned int sg_len, bool is_64bit) { unsigned int desc_len; - struct idmac_desc_64addr *desc_first, *desc_last, *desc; - u32 val; + struct idmac_desc *desc_first, *desc_last, *desc; + struct idmac_desc_64addr *desc64_first, *desc64_last, *desc64; + u32 val, des0; int i; - desc_first = desc_last = desc = host->sg_cpu; + if (is_64bit) + desc64_first = desc64_last = desc64 = host->sg_cpu; + else + desc_first = desc_last = desc = host->sg_cpu; for (i = 0; i < sg_len; i++) { unsigned int length = sg_dma_len(&data->sg[i]); @@ -603,113 +606,52 @@ static inline int dw_mci_prepare_desc64(struct dw_mci *host, * isn't still owned by IDMAC as IDMAC's write * ops and CPU's read ops are asynchronous. */ - if (readl_poll_timeout_atomic(&desc->des0, val, - !(val & IDMAC_DES0_OWN), - 10, 100 * USEC_PER_MSEC)) + if (readl_poll_timeout_atomic(is_64bit ? &desc64->des0 : &desc->des0, + val, IDMAC_OWN_CLR64(val), 10, 100 * USEC_PER_MSEC)) goto err_own_bit; - /* - * Set the OWN bit and disable interrupts - * for this descriptor - */ - desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | - IDMAC_DES0_CH; - - /* Buffer length */ - IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); - - /* Physical address to DMA to/from */ - desc->des4 = mem_addr & 0xffffffff; - desc->des5 = mem_addr >> 32; - - /* Update physical address for the next desc */ - mem_addr += desc_len; - - /* Save pointer to the last descriptor */ - desc_last = desc; - } - } - - /* Set first descriptor */ - desc_first->des0 |= IDMAC_DES0_FD; - - /* Set last descriptor */ - desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); - desc_last->des0 |= IDMAC_DES0_LD; - - return 0; -err_own_bit: - /* restore the descriptor chain as it's polluted */ - dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); - memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); - dw_mci_idmac_init(host); - return -EINVAL; -} - - -static inline int dw_mci_prepare_desc32(struct dw_mci *host, - struct mmc_data *data, - unsigned int sg_len) -{ - unsigned int desc_len; - struct idmac_desc *desc_first, *desc_last, *desc; - u32 val; - int i; - - desc_first = desc_last = desc = host->sg_cpu; - - for (i = 0; i < sg_len; i++) { - unsigned int length = sg_dma_len(&data->sg[i]); - - u32 mem_addr = sg_dma_address(&data->sg[i]); - - for ( ; length ; desc++) { - desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? - length : DW_MCI_DESC_DATA_LENGTH; - - length -= desc_len; - - /* - * Wait for the former clear OWN bit operation - * of IDMAC to make sure that this descriptor - * isn't still owned by IDMAC as IDMAC's write - * ops and CPU's read ops are asynchronous. - */ - if (readl_poll_timeout_atomic(&desc->des0, val, - IDMAC_OWN_CLR64(val), - 10, - 100 * USEC_PER_MSEC)) - goto err_own_bit; + des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH; + if (is_64bit) + desc64->des0 = des0; + else + desc->des0 = cpu_to_le32(des0); /* - * Set the OWN bit and disable interrupts - * for this descriptor + * 1. Set OWN bit and disable interrupts for this descriptor + * 2. Set Buffer length + * Set physical address to DMA to/from */ - desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | - IDMAC_DES0_DIC | - IDMAC_DES0_CH); - - /* Buffer length */ - IDMAC_SET_BUFFER1_SIZE(desc, desc_len); - - /* Physical address to DMA to/from */ - desc->des2 = cpu_to_le32(mem_addr); + if (is_64bit) { + desc64->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH; + IDMAC_64ADDR_SET_BUFFER1_SIZE(desc64, desc_len); + desc64->des4 = mem_addr & 0xffffffff; + desc64->des5 = mem_addr >> 32; + } else { + IDMAC_SET_BUFFER1_SIZE(desc, desc_len); + desc->des2 = cpu_to_le32(mem_addr); + } /* Update physical address for the next desc */ mem_addr += desc_len; /* Save pointer to the last descriptor */ - desc_last = desc; + if (is_64bit) + desc64_last = desc64; + else + desc_last = desc; } } - /* Set first descriptor */ - desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); - - /* Set last descriptor */ - desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | - IDMAC_DES0_DIC)); - desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); + /* Set the first descriptor and the last descriptor */ + if (is_64bit) { + desc64_first->des0 |= IDMAC_DES0_FD; + desc64_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); + desc64_last->des0 |= IDMAC_DES0_LD; + } else { + desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); + desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | IDMAC_DES0_DIC)); + desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); + } return 0; err_own_bit: @@ -725,10 +667,7 @@ static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) u32 temp; int ret; - if (host->dma_64bit_address == 1) - ret = dw_mci_prepare_desc64(host, host->data, sg_len); - else - ret = dw_mci_prepare_desc32(host, host->data, sg_len); + ret = dw_mci_prepare_desc(host, host->data, sg_len, host->dma_64bit_address); if (ret) goto out; -- 2.7.4 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 2/2] mmc: dw_mmc: add dw_mci_prepare_desc() for both of 32bit and 64bit DMA 2025-11-19 8:21 ` [PATCH 2/2] mmc: dw_mmc: add dw_mci_prepare_desc() for both of 32bit and 64bit DMA Shawn Lin @ 2025-11-20 16:00 ` kernel test robot 0 siblings, 0 replies; 3+ messages in thread From: kernel test robot @ 2025-11-20 16:00 UTC (permalink / raw) To: Shawn Lin, Ulf Hansson; +Cc: oe-kbuild-all, linux-mmc, Jaehoon Chung, Shawn Lin Hi Shawn, kernel test robot noticed the following build warnings: [auto build test WARNING on linus/master] [also build test WARNING on ulf-hansson-mmc-mirror/next v6.18-rc6 next-20251120] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Shawn-Lin/mmc-dw_mmc-add-dw_mci_prepare_desc-for-both-of-32bit-and-64bit-DMA/20251119-163950 base: linus/master patch link: https://lore.kernel.org/r/1763540498-84315-2-git-send-email-shawn.lin%40rock-chips.com patch subject: [PATCH 2/2] mmc: dw_mmc: add dw_mci_prepare_desc() for both of 32bit and 64bit DMA config: arm64-randconfig-r121-20251120 (https://download.01.org/0day-ci/archive/20251120/202511202301.b4PYJbNg-lkp@intel.com/config) compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 0bba1e76581bad04e7d7f09f5115ae5e2989e0d9) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251120/202511202301.b4PYJbNg-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202511202301.b4PYJbNg-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) >> drivers/mmc/host/dw_mmc.c:609:29: sparse: sparse: incompatible types in conditional expression (different base types): drivers/mmc/host/dw_mmc.c:609:29: sparse: unsigned int * drivers/mmc/host/dw_mmc.c:609:29: sparse: restricted __le32 * vim +609 drivers/mmc/host/dw_mmc.c 577 578 static inline int dw_mci_prepare_desc(struct dw_mci *host, struct mmc_data *data, 579 unsigned int sg_len, bool is_64bit) 580 { 581 unsigned int desc_len; 582 struct idmac_desc *desc_first, *desc_last, *desc; 583 struct idmac_desc_64addr *desc64_first, *desc64_last, *desc64; 584 u32 val, des0; 585 int i; 586 587 if (is_64bit) 588 desc64_first = desc64_last = desc64 = host->sg_cpu; 589 else 590 desc_first = desc_last = desc = host->sg_cpu; 591 592 for (i = 0; i < sg_len; i++) { 593 unsigned int length = sg_dma_len(&data->sg[i]); 594 595 u64 mem_addr = sg_dma_address(&data->sg[i]); 596 597 for ( ; length ; desc++) { 598 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 599 length : DW_MCI_DESC_DATA_LENGTH; 600 601 length -= desc_len; 602 603 /* 604 * Wait for the former clear OWN bit operation 605 * of IDMAC to make sure that this descriptor 606 * isn't still owned by IDMAC as IDMAC's write 607 * ops and CPU's read ops are asynchronous. 608 */ > 609 if (readl_poll_timeout_atomic(is_64bit ? &desc64->des0 : &desc->des0, 610 val, IDMAC_OWN_CLR64(val), 10, 100 * USEC_PER_MSEC)) 611 goto err_own_bit; 612 613 des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH; 614 if (is_64bit) 615 desc64->des0 = des0; 616 else 617 desc->des0 = cpu_to_le32(des0); 618 619 /* 620 * 1. Set OWN bit and disable interrupts for this descriptor 621 * 2. Set Buffer length 622 * Set physical address to DMA to/from 623 */ 624 if (is_64bit) { 625 desc64->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH; 626 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc64, desc_len); 627 desc64->des4 = mem_addr & 0xffffffff; 628 desc64->des5 = mem_addr >> 32; 629 } else { 630 IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 631 desc->des2 = cpu_to_le32(mem_addr); 632 } 633 634 /* Update physical address for the next desc */ 635 mem_addr += desc_len; 636 637 /* Save pointer to the last descriptor */ 638 if (is_64bit) 639 desc64_last = desc64; 640 else 641 desc_last = desc; 642 } 643 } 644 645 /* Set the first descriptor and the last descriptor */ 646 if (is_64bit) { 647 desc64_first->des0 |= IDMAC_DES0_FD; 648 desc64_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 649 desc64_last->des0 |= IDMAC_DES0_LD; 650 } else { 651 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 652 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | IDMAC_DES0_DIC)); 653 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 654 } 655 656 return 0; 657 err_own_bit: 658 /* restore the descriptor chain as it's polluted */ 659 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 660 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 661 dw_mci_idmac_init(host); 662 return -EINVAL; 663 } 664 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-11-22 20:27 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-11-22 20:26 [PATCH 2/2] mmc: dw_mmc: add dw_mci_prepare_desc() for both of 32bit and 64bit DMA kernel test robot -- strict thread matches above, loose matches on Subject: below -- 2025-11-19 8:21 [PATCH 1/2] mmc: dw_mmc: Remove unused struct dma_pdata Shawn Lin 2025-11-19 8:21 ` [PATCH 2/2] mmc: dw_mmc: add dw_mci_prepare_desc() for both of 32bit and 64bit DMA Shawn Lin 2025-11-20 16:00 ` kernel test robot
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