From: Anup Patel <apatel@ventanamicro.com>
To: Sunil V L <sunilvl@ventanamicro.com>,
"Rafael J . Wysocki" <rafael@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Alexandre Ghiti <alex@ghiti.fr>, Len Brown <lenb@kernel.org>,
Atish Patra <atish.patra@linux.dev>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v4 0/1] Common csr_read_num() and csr_write_num() for RISC-V
Date: Mon, 24 Nov 2025 16:50:30 +0530 [thread overview]
Message-ID: <20251124112031.170350-1-apatel@ventanamicro.com> (raw)
Some of the RISC-V drivers (such as RISC-V PMU and ACPI CPPC) need to
access CSR based on CSR number discovered from somewhere. Add common
RISC-V csr_read_num() and csr_write_num() functions under arch/riscv
for such drivers.
These patches can be found in the riscv_csr_read_num_v4 branch at:
https://github.com/avpatel/linux.git
Changes since v3:
- Rebased on Linux-6.18-rc7
- Updated commit decription of PATCH1 to reflect the fact that
we are removing sanity checks on CSR number which are already
taken care by csr_read_num() and csr_write_num().
Changes since v2:
- Rebased on Linux-6.18-rc1
- Added reviewed-by tags
Changes since v1:
- Make "out_err" mandatory for csr_read_num() and csr_write_num()
in PATCH2 as suggested by Sunil and Drew. This also helps further
simplify csr_read_num() and csr_write_num().
Anup Patel (1):
RISC-V: Add common csr_read_num() and csr_write_num() functions
arch/riscv/include/asm/csr.h | 3 +
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/csr.c | 165 +++++++++++++++++++++++++++++++++++
drivers/acpi/riscv/cppc.c | 17 ++--
drivers/perf/riscv_pmu.c | 54 ++----------
5 files changed, 184 insertions(+), 56 deletions(-)
create mode 100644 arch/riscv/kernel/csr.c
--
2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Sunil V L <sunilvl@ventanamicro.com>,
"Rafael J . Wysocki" <rafael@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Alexandre Ghiti <alex@ghiti.fr>, Len Brown <lenb@kernel.org>,
Atish Patra <atish.patra@linux.dev>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v4 0/1] Common csr_read_num() and csr_write_num() for RISC-V
Date: Mon, 24 Nov 2025 16:50:30 +0530 [thread overview]
Message-ID: <20251124112031.170350-1-apatel@ventanamicro.com> (raw)
Some of the RISC-V drivers (such as RISC-V PMU and ACPI CPPC) need to
access CSR based on CSR number discovered from somewhere. Add common
RISC-V csr_read_num() and csr_write_num() functions under arch/riscv
for such drivers.
These patches can be found in the riscv_csr_read_num_v4 branch at:
https://github.com/avpatel/linux.git
Changes since v3:
- Rebased on Linux-6.18-rc7
- Updated commit decription of PATCH1 to reflect the fact that
we are removing sanity checks on CSR number which are already
taken care by csr_read_num() and csr_write_num().
Changes since v2:
- Rebased on Linux-6.18-rc1
- Added reviewed-by tags
Changes since v1:
- Make "out_err" mandatory for csr_read_num() and csr_write_num()
in PATCH2 as suggested by Sunil and Drew. This also helps further
simplify csr_read_num() and csr_write_num().
Anup Patel (1):
RISC-V: Add common csr_read_num() and csr_write_num() functions
arch/riscv/include/asm/csr.h | 3 +
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/csr.c | 165 +++++++++++++++++++++++++++++++++++
drivers/acpi/riscv/cppc.c | 17 ++--
drivers/perf/riscv_pmu.c | 54 ++----------
5 files changed, 184 insertions(+), 56 deletions(-)
create mode 100644 arch/riscv/kernel/csr.c
--
2.43.0
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next reply other threads:[~2025-11-24 11:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-24 11:20 Anup Patel [this message]
2025-11-24 11:20 ` [PATCH v4 0/1] Common csr_read_num() and csr_write_num() for RISC-V Anup Patel
2025-11-24 11:20 ` [PATCH v4 1/1] RISC-V: Add common csr_read_num() and csr_write_num() functions Anup Patel
2025-11-24 11:20 ` Anup Patel
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