[RFC PATCH 0/3] soc: Enable cache lockdown for HiSilicon L3 cache

[RFC PATCH 0/3] soc: Enable cache lockdown for HiSilicon L3 cache

[Yushan Wang]

Cache has been playing the transparent yet crucial role of performance
for modern computers. To fully exploit the potential of SoC cache, we
made an attempt to lockdown the HiSilicon L3 cache.

Cache lockdown means to make a memory region locked inside the L3 cache
for better access latency. The data stored in L3 cache will behave like
any other data (i.e. it still follows cache coherency protocol etc.)
except it won't be evicted unless explicitly asked to by deallocation.

Ideally locked data will have stable low access latency despite high
background stress. It is also useful for scenarios that have especially
high cache miss penalty. However, while enhancing some processes,
reserving cache resource will raise the performance problem to other
processes running on the CPUs that share the L3 cache that carries
locked data, users should be careful to do so.

I would like to ask for opinions about the possibility to make this
driver upstream, and the possible usecase of L3 cache lock within
kernel. Further tests are needed to obtain the performance benefits and
impact we get from L3 cache lock on such usecases.

Yushan Wang (3):
  soc cache: L3 cache driver for HiSilicon SoC
  soc cache: L3 cache lockdown support for HiSilicon SoC
  Documentation: soc cache: Add documentation to HiSilicon SoC cache

 Documentation/driver-api/hisi-soc-cache.rst   |  62 ++
 Documentation/driver-api/index.rst            |   1 +
 .../userspace-api/ioctl/ioctl-number.rst      |   1 +
 drivers/soc/hisilicon/Kconfig                 |  10 +
 drivers/soc/hisilicon/Makefile                |   2 +
 drivers/soc/hisilicon/hisi_soc_l3c.c          | 877 ++++++++++++++++++
 include/uapi/misc/hisi_l3c.h                  |  28 +
 7 files changed, 981 insertions(+)
 create mode 100644 Documentation/driver-api/hisi-soc-cache.rst
 create mode 100644 drivers/soc/hisilicon/hisi_soc_l3c.c
 create mode 100644 include/uapi/misc/hisi_l3c.h

-- 
2.33.0

[RFC PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC

[Yushan Wang]

The driver will create a file of `/dev/hisi_l3c` on init, mmap
operations to it will allocate a memory region that is guaranteed to be
placed in L3 cache.

The driver also provides unmap() to deallocated the locked memory.

The driver also provides an ioctl interface for user to get cache lock
information, such as lock restrictions and locked sizes.

Signed-off-by: Yushan Wang <wangyushan12@huawei.com>
---
 .../userspace-api/ioctl/ioctl-number.rst      |   1 +
 drivers/soc/hisilicon/Kconfig                 |  10 +
 drivers/soc/hisilicon/Makefile                |   2 +
 drivers/soc/hisilicon/hisi_soc_l3c.c          | 359 ++++++++++++++++++
 include/uapi/misc/hisi_l3c.h                  |  28 ++
 5 files changed, 400 insertions(+)
 create mode 100644 drivers/soc/hisilicon/hisi_soc_l3c.c
 create mode 100644 include/uapi/misc/hisi_l3c.h

diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst
index 7c527a01d1cf..759469386e60 100644
--- a/Documentation/userspace-api/ioctl/ioctl-number.rst
+++ b/Documentation/userspace-api/ioctl/ioctl-number.rst
@@ -385,6 +385,7 @@ Code  Seq#    Include File                                             Comments
 0xB8  01-02  uapi/misc/mrvl_cn10k_dpi.h                                Marvell CN10K DPI driver
 0xB8  all    uapi/linux/mshv.h                                         Microsoft Hyper-V /dev/mshv driver
                                                                        <mailto:linux-hyperv@vger.kernel.org>
+0xBA  all    uapi/misc/hisi_soc_cache.h                                HiSilicon SoC cache driver
 0xC0  00-0F  linux/usb/iowarrior.h
 0xCA  00-0F  uapi/misc/cxl.h                                           Dead since 6.15
 0xCA  10-2F  uapi/misc/ocxl.h
diff --git a/drivers/soc/hisilicon/Kconfig b/drivers/soc/hisilicon/Kconfig
index 6d7c244d2e78..ea16dffccd5e 100644
--- a/drivers/soc/hisilicon/Kconfig
+++ b/drivers/soc/hisilicon/Kconfig
@@ -21,4 +21,14 @@ config KUNPENG_HCCS
 	  health status and port information of HCCS, or reducing system
 	  power consumption on Kunpeng SoC.
 
+config HISI_SOC_L3C
+	bool "HiSilicon L3 Cache device driver"
+	depends on ARM64 && ACPI || COMPILE_TEST
+	help
+	  This driver provides the functions to lock L3 cache entries from
+	  being evicted for better performance.
+
+	  This driver can be built as a module. If so, the module will be
+	  called hisi_soc_l3c.
+
 endmenu
diff --git a/drivers/soc/hisilicon/Makefile b/drivers/soc/hisilicon/Makefile
index 226e747e70d6..16ff2c73c4a5 100644
--- a/drivers/soc/hisilicon/Makefile
+++ b/drivers/soc/hisilicon/Makefile
@@ -1,2 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_KUNPENG_HCCS)	+= kunpeng_hccs.o
+
+obj-$(CONFIG_HISI_SOC_L3C)	+= hisi_soc_l3c.o
diff --git a/drivers/soc/hisilicon/hisi_soc_l3c.c b/drivers/soc/hisilicon/hisi_soc_l3c.c
new file mode 100644
index 000000000000..2c196c4dfff1
--- /dev/null
+++ b/drivers/soc/hisilicon/hisi_soc_l3c.c
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for HiSilicon L3 cache.
+ *
+ * Copyright (c) 2025 HiSilicon Technologies Co., Ltd.
+ * Author: Yushan Wang <wangyushan12@huawei.com>
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/cleanup.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/spinlock_types.h>
+#include <linux/types.h>
+
+#include <asm/cputype.h>
+
+#include <uapi/misc/hisi_l3c.h>
+
+#define to_hisi_l3c(p) container_of((p), struct hisi_l3c, comp)
+
+/**
+ * struct hisi_soc_comp - Struct of HiSilicon SoC cache components.
+ *
+ * @node: list node of hisi_soc_comp_list.
+ * @ops: possible operations a component may perform.
+ * @affinity_mask: cpus that associate with this component.
+ * @private: component specific data.
+ */
+struct hisi_soc_comp {
+	struct list_head node;
+	struct hisi_soc_comp_ops *ops;
+	cpumask_t affinity_mask;
+	void *private;
+};
+
+/**
+ * struct hisi_soc_comp_ops - Callbacks for SoC cache drivers to handle
+ *			      operation requests.
+ *
+ * @do_lock: lock certain region of L3 cache from being evicted.
+ * @poll_lock_done: check if the lock operation has succeeded.
+ * @do_unlock: unlock the locked region of L3 cache back to normal.
+ * @poll_unlock_done: check if the unlock operation has succeeded.
+	      operation requests.
+ *
+ * Operations are decoupled into two phases so that framework does not have
+ * to wait for one operation to finish before calling the next when multiple
+ * hardwares onboard.
+ *
+ * Implementers must implement the functions in pairs.  Implementation should
+ * return -EBUSY when:
+ * - insufficient resources are available to perform the operation.
+ * - previously raised operation is not finished.
+ * - new operations (do_lock(), do_unlock() etc.) to the same address
+ *   before corresponding done functions being called.
+ */
+struct hisi_soc_comp_ops {
+	int (*do_lock)(struct hisi_soc_comp *comp, phys_addr_t addr, size_t size);
+	int (*poll_lock_done)(struct hisi_soc_comp *comp, phys_addr_t addr, size_t size);
+	int (*do_unlock)(struct hisi_soc_comp *comp, phys_addr_t addr);
+	int (*poll_unlock_done)(struct hisi_soc_comp *comp, phys_addr_t addr);
+};
+
+struct hisi_l3c_lock_region {
+	/* physical address of the arena allocated for aligned address */
+	unsigned long arena_start;
+	/* VMA region of locked memory for future release */
+	unsigned long vm_start;
+	unsigned long vm_end;
+	phys_addr_t addr;
+	size_t size;
+	/* Return value of cache lock call */
+	int status;
+	int cpu;
+};
+
+struct hisi_soc_comp_list {
+	struct list_head node;
+	/* protects list of HiSilicon SoC cache components */
+	spinlock_t lock;
+};
+
+static struct hisi_soc_comp_list l3c_devs;
+
+static int hisi_l3c_lock(int cpu, phys_addr_t addr, size_t size)
+{
+	struct hisi_soc_comp *comp;
+	int ret;
+
+	guard(spinlock)(&l3c_devs.lock);
+
+	/* When there is no instance onboard, no locked memory is available. */
+	if (list_empty(&l3c_devs.node))
+		return -ENOMEM;
+
+	/* Lock need to be performed on each channel of associated L3 cache. */
+	list_for_each_entry(comp, &l3c_devs.node, node) {
+		if (!cpumask_test_cpu(cpu, &comp->affinity_mask))
+			continue;
+		ret = comp->ops->do_lock(comp, addr, size);
+		if (ret)
+			return ret;
+	}
+
+	list_for_each_entry(comp, &l3c_devs.node, node) {
+		if (!cpumask_test_cpu(cpu, &comp->affinity_mask))
+			continue;
+		ret = comp->ops->poll_lock_done(comp, addr, size);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int hisi_l3c_unlock(int cpu, phys_addr_t addr)
+{
+	struct hisi_soc_comp *comp;
+	int ret;
+
+	guard(spinlock)(&l3c_devs.lock);
+
+	if (list_empty(&l3c_devs.node))
+		return -EINVAL;
+
+	/* Perform unlock on each channel of associated L3 cache. */
+	list_for_each_entry(comp, &l3c_devs.node, node) {
+		if (!cpumask_test_cpu(cpu, &comp->affinity_mask))
+			continue;
+		ret = comp->ops->do_unlock(comp, addr);
+		if (ret)
+			return ret;
+	}
+
+	list_for_each_entry(comp, &l3c_devs.node, node) {
+		if (!cpumask_test_cpu(cpu, &comp->affinity_mask))
+			continue;
+		ret = comp->ops->poll_unlock_done(comp, addr);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static void hisi_soc_comp_add(struct hisi_soc_comp *comp)
+{
+	guard(spinlock)(&l3c_devs.lock);
+	list_add_tail(&comp->node, &l3c_devs.node);
+}
+
+/* Null @comp means to delete all instances. */
+static int hisi_soc_comp_del(struct hisi_soc_comp *comp)
+{
+	struct hisi_soc_comp *entry, *tmp;
+
+	guard(spinlock)(&l3c_devs.lock);
+	list_for_each_entry_safe(entry, tmp, &l3c_devs.node, node) {
+		if (comp && comp != entry)
+			continue;
+
+		list_del(&entry->node);
+
+		/* Only continue to delete nodes when @comp is NULL */
+		if (comp)
+			break;
+	}
+
+	return 0;
+}
+
+static void hisi_l3c_vm_open(struct vm_area_struct *vma)
+{
+	struct hisi_l3c_lock_region *clr = vma->vm_private_data;
+
+	/*
+	 * Only perform cache lock when the vma passed in is created in
+	 * hisi_l3c_mmap.
+	 */
+	if (clr->vm_start != vma->vm_start || clr->vm_end != vma->vm_end)
+		return;
+
+	clr->status = hisi_l3c_lock(clr->cpu, clr->addr, clr->size);
+}
+
+static void hisi_l3c_vm_close(struct vm_area_struct *vma)
+{
+	struct hisi_l3c_lock_region *clr = vma->vm_private_data;
+	int order = get_order(clr->size);
+
+	/*
+	 * Only perform cache unlock when the vma passed in is created
+	 * in hisi_l3c_mmap.
+	 */
+	if (clr->vm_start != vma->vm_start || clr->vm_end != vma->vm_end)
+		return;
+
+	hisi_l3c_unlock(clr->cpu, clr->addr);
+
+	free_contig_range(PHYS_PFN(clr->addr), 1 << order);
+	kfree(clr);
+	vma->vm_private_data = NULL;
+}
+
+/* mremap operation is not supported for HiSilicon SoC cache. */
+static int hisi_l3c_vm_mremap(struct vm_area_struct *vma)
+{
+	struct hisi_l3c_lock_region *clr = vma->vm_private_data;
+
+	/*
+	 * vma region size will be changed as requested by mremap despite the
+	 * callback failure in this function.  Thus, change the vma region
+	 * stored in clr according to the parameters to verify if the pages
+	 * should be freed when unmapping.
+	 */
+	clr->vm_end = clr->vm_start + (vma->vm_end - vma->vm_start);
+	pr_err("mremap for HiSilicon SoC locked cache is not supported\n");
+
+	return -EOPNOTSUPP;
+}
+
+static int hisi_l3c_may_split(struct vm_area_struct *area, unsigned long addr)
+{
+	pr_err("HiSilicon SoC locked cache may not be split.\n");
+	return -EINVAL;
+}
+
+static const struct vm_operations_struct hisi_l3c_vm_ops = {
+	.open = hisi_l3c_vm_open,
+	.close = hisi_l3c_vm_close,
+	.may_split = hisi_l3c_may_split,
+	.mremap = hisi_l3c_vm_mremap,
+};
+
+static int hisi_l3c_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	unsigned long size = vma->vm_end - vma->vm_start;
+	int order = get_order(size);
+	unsigned long addr;
+	struct page *pg;
+	int ret;
+
+	struct hisi_l3c_lock_region *clr __free(kfree) = kzalloc(sizeof(*clr), GFP_KERNEL);
+	if (!clr)
+		return -ENOMEM;
+
+	/* Continuous physical memory is required for L3 cache lock. */
+	pg = alloc_contig_pages(1 << order, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO,
+				cpu_to_node(smp_processor_id()), NULL);
+	if (!pg)
+		return -ENOMEM;
+
+	addr = page_to_phys(pg);
+	*clr = (struct hisi_l3c_lock_region) {
+		.addr = addr,
+		.size = size,
+		.cpu = smp_processor_id(),
+		/* vma should not be moved, store here for validation */
+		.vm_start = vma->vm_start,
+		.vm_end = vma->vm_end,
+	};
+
+	vm_flags_set(vma, VM_DONTCOPY | VM_DONTEXPAND);
+	vma->vm_ops = &hisi_l3c_vm_ops;
+	vma->vm_private_data = clr;
+
+	hisi_l3c_vm_ops.open(vma);
+	if (clr->status) {
+		ret = clr->status;
+		goto out_page;
+	}
+
+	ret = remap_pfn_range(vma, vma->vm_start, PFN_DOWN(addr), size,
+			      vma->vm_page_prot);
+	if (ret)
+		goto out_page;
+
+	/* Save clr from being freed when lock succeeds. */
+	vma->vm_private_data = no_free_ptr(clr);
+
+	return 0;
+
+out_page:
+	free_contig_range(PHYS_PFN(clr->addr), 1 << order);
+	return ret;
+}
+
+static int hisi_l3c_lock_restriction(unsigned long arg)
+{
+	void __user *uarg = (void __user *)arg;
+	int cpu = smp_processor_id();
+	struct hisi_soc_comp *comp;
+
+	if (list_empty(&l3c_devs.node))
+		return -ENODEV;
+
+	list_for_each_entry(comp, &l3c_devs.node, node) {
+		if (!cpumask_test_cpu(cpu, &comp->affinity_mask))
+			continue;
+
+		if (!comp->private)
+			return -ENOENT;
+
+		if (copy_to_user(uarg, comp->private, sizeof(struct hisi_l3c_lock_info)))
+			return -EFAULT;
+
+		return 0;
+	}
+
+	return -ENODEV;
+}
+
+static long hisi_l3c_ioctl(struct file *file, u32 cmd, unsigned long arg)
+{
+	switch (cmd) {
+	case HISI_L3C_LOCK_INFO:
+		return hisi_l3c_lock_restriction(arg);
+	default:
+		return -EINVAL;
+	}
+}
+
+static const struct file_operations l3c_dev_fops = {
+	.owner = THIS_MODULE,
+	.unlocked_ioctl = hisi_l3c_ioctl,
+	.mmap = hisi_l3c_mmap,
+};
+
+static struct miscdevice l3c_miscdev = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "hisi_l3c",
+	.fops = &l3c_dev_fops,
+	.mode = 0600,
+};
+
+static int __init hisi_l3c_init(void)
+{
+	spin_lock_init(&l3c_devs.lock);
+	INIT_LIST_HEAD(&l3c_devs.node);
+
+	return misc_register(&l3c_miscdev);
+}
+module_init(hisi_l3c_init);
+
+static void __exit hisi_l3c_exit(void)
+{
+	misc_deregister(&l3c_miscdev);
+	hisi_soc_comp_del(NULL);
+}
+module_exit(hisi_l3c_exit);
+
+MODULE_DESCRIPTION("Hisilicon L3 Cache Driver");
+MODULE_AUTHOR("Yushan Wang <wangyushan12@huawei.com>");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/misc/hisi_l3c.h b/include/uapi/misc/hisi_l3c.h
new file mode 100644
index 000000000000..73086977a34e
--- /dev/null
+++ b/include/uapi/misc/hisi_l3c.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later WITH Linux-syscall-note */
+/* Copyright (c) 2024 HiSilicon Technologies Co., Ltd. */
+#ifndef _UAPI_HISI_SOC_L3C_H
+#define _UAPI_HISI_SOC_L3C_H
+
+#include <linux/types.h>
+
+/* HISI_L3C_INFO: cache lock info for HiSilicon SoC */
+#define HISI_L3C_LOCK_INFO	_IOW(0xBA, 1, unsigned long)
+
+/**
+ * struct hisi_l3c_info - User data for hisi cache operates.
+ * @lock_region_num: available locked memory region on a L3C instance
+ * @lock_size: available size to be locked of the L3C instance.
+ * @address_alignment: if the L3C lock requires locked region physical start
+ *		       address to be aligned with the memory region size.
+ * @max_lock_size: maximum locked memory size on a L3C instance.
+ * @min_lock_size: minimum locked memory size on a L3C instance.
+ */
+struct hisi_l3c_lock_info {
+	unsigned int lock_region_num;
+	size_t lock_size;
+	bool address_alignment;
+	size_t max_lock_size;
+	size_t min_lock_size;
+};
+
+#endif
-- 
2.33.0

[RFC PATCH 2/3] soc cache: L3 cache lockdown support for HiSilicon SoC

[Yushan Wang]

This driver implements the interface exposed by framework, passes cache
lock/unlock requests to hardware.

The number of locked memory region is limited according to firmware,
and the total size of locked memory regions must be less than 70% of
cache size.

Signed-off-by: Yushan Wang <wangyushan12@huawei.com>
---
 drivers/soc/hisilicon/hisi_soc_l3c.c | 520 ++++++++++++++++++++++++++-
 1 file changed, 519 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/hisilicon/hisi_soc_l3c.c b/drivers/soc/hisilicon/hisi_soc_l3c.c
index 2c196c4dfff1..1e3419436173 100644
--- a/drivers/soc/hisilicon/hisi_soc_l3c.c
+++ b/drivers/soc/hisilicon/hisi_soc_l3c.c
@@ -8,19 +8,49 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
+#include <linux/acpi.h>
 #include <linux/cleanup.h>
+#include <linux/cpuhotplug.h>
 #include <linux/init.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
 #include <linux/mm.h>
 #include <linux/miscdevice.h>
 #include <linux/module.h>
+#include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/spinlock_types.h>
 #include <linux/types.h>
+#include <linux/xarray.h>
 
 #include <asm/cputype.h>
 
 #include <uapi/misc/hisi_l3c.h>
 
+#define HISI_L3C_LOCK_CTRL	0x0530
+#define HISI_L3C_LOCK_AREA	0x0534
+#define HISI_L3C_LOCK_START_L	0x0538
+#define HISI_L3C_LOCK_START_H	0x053C
+
+#define HISI_L3C_DYNAMIC_AUCTRL	0x0404
+
+#define HISI_L3C_LOCK_CTRL_POLL_GAP_US	10
+#define HISI_L3C_LOCK_CTRL_POLL_MAX_US	10000
+
+/* L3C control register bit definition */
+#define HISI_L3C_LOCK_CTRL_LOCK_EN		BIT(0)
+#define HISI_L3C_LOCK_CTRL_LOCK_DONE		BIT(1)
+#define HISI_L3C_LOCK_CTRL_UNLOCK_EN		BIT(2)
+#define HISI_L3C_LOCK_CTRL_UNLOCK_DONE		BIT(3)
+
+#define HISI_L3C_LOCK_MIN_SIZE		(1 * 1024 * 1024)
+#define HISI_L3_CACHE_LINE_SIZE		64
+
+/* Allow maximum 70% of cache locked. */
+#define HISI_L3C_MAX_LOCK_SIZE(size)	((size) / 10 * 7)
+
+#define l3c_lock_reg_offset(reg, set)	((reg) + 16 * (set))
+
 #define to_hisi_l3c(p) container_of((p), struct hisi_l3c, comp)
 
 /**
@@ -85,8 +115,280 @@ struct hisi_soc_comp_list {
 	spinlock_t lock;
 };
 
+struct hisi_l3c {
+	struct hisi_soc_comp comp;
+	cpumask_t associated_cpus;
+
+	/* Stores the first address locked by each register sets. */
+	struct xarray lock_sets;
+	/* Locks lock_sets to forbid overlapping access. */
+	spinlock_t reg_lock;
+
+	struct hlist_node node;
+	void __iomem *base;
+
+	/* ID of Super CPU cluster on where the L3 cache locates. */
+	int sccl_id;
+	/* ID of CPU cluster where L3 cache is located. */
+	int ccl_id;
+};
+
+static int hisi_l3c_cpuhp_state;
+
 static struct hisi_soc_comp_list l3c_devs;
 
+/**
+ * hisi_l3c_alloc_lock_reg_set - Allocate an available control register set
+ *				     of L3 cache for lock & unlock operations.
+ * @l3c:	The L3C instance on which the register set will be allocated.
+ * @addr:	The address to be locked.
+ * @size:	The size to be locked.
+ *
+ * @return:
+ *   - -EBUSY: If there is no available register sets.
+ *   - -ENOMEM: If there is no available memory for lock region struct.
+ *   - -EINVAL: If there is no available cache size for lock.
+ *   - 0: If allocation succeeds.
+ *
+ * Maintains the resource of control registers of L3 cache.  On allocation,
+ * the index of a spare set of registers is returned, then the address is
+ * stored inside for future match of unlock operation.
+ */
+static int hisi_l3c_alloc_lock_reg_set(struct hisi_l3c *l3c, phys_addr_t addr, size_t size)
+{
+	struct hisi_l3c_lock_info *info = l3c->comp.private;
+	struct hisi_l3c_lock_region *lr;
+	void *entry;
+	int idx, ret;
+
+	if (size > info->lock_size)
+		return -EINVAL;
+
+	for (idx = 0; idx < info->lock_region_num; ++idx) {
+		entry = xa_load(&l3c->lock_sets, idx);
+		if (!entry)
+			break;
+	}
+
+	if (idx > info->lock_region_num)
+		return -EBUSY;
+
+	lr = kzalloc(sizeof(*lr), GFP_KERNEL);
+	if (!lr)
+		return -ENOMEM;
+
+	lr->addr = addr;
+	lr->size = size;
+
+	ret = xa_alloc(&l3c->lock_sets, &idx, lr, xa_limit_31b, GFP_KERNEL);
+	if (ret) {
+		kfree(lr);
+		return ret;
+	}
+
+	info->lock_size -= size;
+	info->lock_region_num -= 1;
+
+	return idx;
+}
+
+/**
+ * hisi_l3c_get_locked_reg_set - Get the index of an allocated register set
+ *				     by locked address.
+ * @l3c:	The L3C instance on which the register set is allocated.
+ * @addr:	The locked address.
+ *
+ * @return:
+ *   - >= 0: index of register set which controls locked memory region of @addr.
+ *   - -EINVAL: If @addr is not locked in this cache.
+ */
+static int hisi_l3c_get_locked_reg_set(struct hisi_l3c *l3c, phys_addr_t addr)
+{
+	struct hisi_l3c_lock_region *entry;
+	unsigned long idx;
+
+	xa_for_each(&l3c->lock_sets, idx, entry) {
+		if (entry->addr == addr)
+			return idx;
+	}
+	return -EINVAL;
+}
+
+/**
+ * hisi_l3c_free_lock_reg_set - Free an allocated register set by locked
+ *				    address.
+ *
+ * @l3c:	The L3C instance on which the register set is allocated.
+ * @regset:	ID of Register set to be freed.
+ */
+static void hisi_l3c_free_lock_reg_set(struct hisi_l3c *l3c, int regset)
+{
+	struct hisi_l3c_lock_info *info = l3c->comp.private;
+	struct hisi_l3c_lock_region *entry;
+
+	if (regset < 0)
+		return;
+
+	entry = xa_erase(&l3c->lock_sets, regset);
+	if (!entry)
+		return;
+
+	info->lock_size += entry->size;
+	info->lock_region_num += 1;
+	kfree(entry);
+}
+
+static bool hisi_l3c_lock_wait_finished(struct hisi_l3c *l3c, int regset)
+{
+	void *reg = l3c->base + l3c_lock_reg_offset(HISI_L3C_LOCK_CTRL, regset);
+	/* Wait until neither lock or unlock operation is going on. */
+	u32 mask = HISI_L3C_LOCK_CTRL_LOCK_DONE | HISI_L3C_LOCK_CTRL_UNLOCK_DONE;
+	u32 val;
+
+	/*
+	 * Lock/unlock done bits are initially 0 if no lock operation was ever
+	 * issued, and will be set until next operation comes.
+	 * Check if this is the first lock operation after boot by checking if
+	 * the register is 0. If so, proceed with the operation.
+	 */
+	val = readl(reg);
+	if (!val)
+		return true;
+
+	return !readl_poll_timeout_atomic(reg, val, val & mask,
+			HISI_L3C_LOCK_CTRL_POLL_GAP_US,
+			HISI_L3C_LOCK_CTRL_POLL_MAX_US);
+}
+
+static int hisi_l3c_do_lock(struct hisi_soc_comp *comp, phys_addr_t addr, size_t size)
+{
+	struct hisi_l3c *l3c = to_hisi_l3c(comp);
+	struct hisi_l3c_lock_info *info = l3c->comp.private;
+	void *base = l3c->base;
+	int regset;
+	u32 ctrl;
+
+	if (info->address_alignment && addr % size != 0)
+		return -EINVAL;
+
+	if (size < info->min_lock_size || size > info->max_lock_size)
+		return -EINVAL;
+
+	guard(spinlock)(&l3c->reg_lock);
+
+	regset = hisi_l3c_alloc_lock_reg_set(l3c, addr, size);
+	if (regset < 0)
+		return -EBUSY;
+
+	if (!hisi_l3c_lock_wait_finished(l3c, regset)) {
+		hisi_l3c_free_lock_reg_set(l3c, regset);
+		return -EBUSY;
+	}
+
+	writel(lower_32_bits(addr),
+	       base + l3c_lock_reg_offset(HISI_L3C_LOCK_START_L, regset));
+	writel(upper_32_bits(addr),
+	       base + l3c_lock_reg_offset(HISI_L3C_LOCK_START_H, regset));
+	writel(size, base + l3c_lock_reg_offset(HISI_L3C_LOCK_AREA, regset));
+
+	ctrl = readl(base + HISI_L3C_DYNAMIC_AUCTRL);
+	ctrl |= BIT(regset);
+	writel(ctrl, base + HISI_L3C_DYNAMIC_AUCTRL);
+
+	ctrl = readl(base + l3c_lock_reg_offset(HISI_L3C_LOCK_CTRL, regset));
+	ctrl = (ctrl | HISI_L3C_LOCK_CTRL_LOCK_EN) &
+		~HISI_L3C_LOCK_CTRL_UNLOCK_EN;
+	writel(ctrl, base + l3c_lock_reg_offset(HISI_L3C_LOCK_CTRL, regset));
+
+	return 0;
+}
+
+static int hisi_l3c_poll_lock_done(struct hisi_soc_comp *comp, phys_addr_t addr, size_t size)
+{
+	struct hisi_l3c *l3c = to_hisi_l3c(comp);
+	int regset;
+
+	guard(spinlock)(&l3c->reg_lock);
+
+	regset = hisi_l3c_get_locked_reg_set(l3c, addr);
+	if (regset < 0)
+		return -EINVAL;
+
+	if (!hisi_l3c_lock_wait_finished(l3c, regset))
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int hisi_l3c_do_unlock(struct hisi_soc_comp *comp, phys_addr_t addr)
+{
+	struct hisi_l3c *l3c = to_hisi_l3c(comp);
+	void *base = l3c->base;
+	int regset;
+	u32 ctrl;
+
+	guard(spinlock)(&l3c->reg_lock);
+
+	regset = hisi_l3c_get_locked_reg_set(l3c, addr);
+	if (regset < 0)
+		return -EINVAL;
+
+	if (!hisi_l3c_lock_wait_finished(l3c, regset))
+		return -EBUSY;
+
+	ctrl = readl(base + HISI_L3C_DYNAMIC_AUCTRL);
+	ctrl &= ~BIT(regset);
+	writel(ctrl, base + HISI_L3C_DYNAMIC_AUCTRL);
+
+	ctrl = readl(base + l3c_lock_reg_offset(HISI_L3C_LOCK_CTRL, regset));
+	ctrl = (ctrl | HISI_L3C_LOCK_CTRL_UNLOCK_EN) &
+		~HISI_L3C_LOCK_CTRL_LOCK_EN;
+	writel(ctrl, base + l3c_lock_reg_offset(HISI_L3C_LOCK_CTRL, regset));
+
+	return 0;
+}
+
+static int hisi_l3c_poll_unlock_done(struct hisi_soc_comp *comp, phys_addr_t addr)
+{
+	struct hisi_l3c *l3c = to_hisi_l3c(comp);
+	int regset;
+
+	guard(spinlock)(&l3c->reg_lock);
+
+	regset = hisi_l3c_get_locked_reg_set(l3c, addr);
+	if (regset < 0)
+		return -EINVAL;
+
+	if (!hisi_l3c_lock_wait_finished(l3c, regset))
+		return -ETIMEDOUT;
+
+	hisi_l3c_free_lock_reg_set(l3c, regset);
+
+	return 0;
+}
+
+static void hisi_l3c_remove_locks(struct hisi_l3c *l3c)
+{
+	void *base = l3c->base;
+	unsigned long regset;
+	void *entry;
+
+	guard(spinlock)(&l3c->reg_lock);
+
+	xa_for_each(&l3c->lock_sets, regset, entry) {
+		int timeout;
+		u32 ctrl;
+
+		ctrl = readl(base + l3c_lock_reg_offset(HISI_L3C_LOCK_CTRL, regset));
+		ctrl = (ctrl | HISI_L3C_LOCK_CTRL_UNLOCK_EN) & ~HISI_L3C_LOCK_CTRL_LOCK_EN;
+		writel(ctrl, base + l3c_lock_reg_offset(HISI_L3C_LOCK_CTRL, regset));
+
+		timeout = hisi_l3c_lock_wait_finished(l3c, regset);
+		if (timeout)
+			pr_err("failed to remove %lu-th cache lock.\n", regset);
+	}
+}
+
 static int hisi_l3c_lock(int cpu, phys_addr_t addr, size_t size)
 {
 	struct hisi_soc_comp *comp;
@@ -315,6 +617,196 @@ static int hisi_l3c_lock_restriction(unsigned long arg)
 	return -ENODEV;
 }
 
+static int hisi_l3c_init_lock_capacity(struct hisi_l3c *l3c, struct device *dev)
+{
+	int ret;
+	u32 val;
+
+	struct hisi_l3c_lock_info *info __free(kfree) = kmalloc(sizeof(*info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	ret = device_property_read_u32(dev, "hisilicon,l3c-lockregion-num", &val);
+	if (ret || val <= 0)
+		return -EINVAL;
+
+	info->lock_region_num = val;
+
+	ret = device_property_read_u32(dev, "hisilicon,l3c-max-single-lockregion-size", &val);
+	if (ret || val <= 0)
+		return -EINVAL;
+
+	info->lock_size = HISI_L3C_MAX_LOCK_SIZE(val);
+	info->address_alignment = info->lock_region_num == 1;
+	info->max_lock_size = HISI_L3C_MAX_LOCK_SIZE(val);
+	info->min_lock_size = info->lock_region_num == 1
+					? HISI_L3C_LOCK_MIN_SIZE
+					: HISI_L3_CACHE_LINE_SIZE;
+
+	l3c->comp.private = no_free_ptr(info);
+
+	return 0;
+}
+
+static int hisi_l3c_init_topology(struct hisi_l3c *l3c, struct device *dev)
+{
+	l3c->sccl_id = -1;
+	l3c->ccl_id = -1;
+
+	if (device_property_read_u32(dev, "hisilicon,scl-id", &l3c->sccl_id) ||
+	    l3c->sccl_id < 0)
+		return -EINVAL;
+
+	if (device_property_read_u32(dev, "hisilicon,ccl-id", &l3c->ccl_id) ||
+	    l3c->ccl_id < 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+static void hisi_init_associated_cpus(struct hisi_l3c *l3c)
+{
+	if (!cpumask_empty(&l3c->associated_cpus))
+		return;
+	cpumask_clear(&l3c->associated_cpus);
+	cpumask_copy(&l3c->comp.affinity_mask, &l3c->associated_cpus);
+}
+
+static struct hisi_soc_comp_ops hisi_comp_ops = {
+	.do_lock = hisi_l3c_do_lock,
+	.poll_lock_done = hisi_l3c_poll_lock_done,
+	.do_unlock = hisi_l3c_do_unlock,
+	.poll_unlock_done = hisi_l3c_poll_unlock_done,
+};
+
+static struct hisi_soc_comp hisi_comp = {
+	.ops = &hisi_comp_ops,
+};
+
+static int hisi_l3c_probe(struct platform_device *pdev)
+{
+	struct hisi_l3c *l3c;
+	struct resource *mem;
+	int ret;
+
+	l3c = devm_kzalloc(&pdev->dev, sizeof(*l3c), GFP_KERNEL);
+	if (!l3c)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, l3c);
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem)
+		return -ENODEV;
+
+	l3c->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
+	if (IS_ERR_OR_NULL(l3c->base))
+		return PTR_ERR(l3c->base);
+
+	l3c->comp = hisi_comp;
+	spin_lock_init(&l3c->reg_lock);
+	xa_init_flags(&l3c->lock_sets, XA_FLAGS_ALLOC);
+
+	ret = hisi_l3c_init_lock_capacity(l3c, &pdev->dev);
+	if (ret)
+		goto err_xa;
+
+	hisi_init_associated_cpus(l3c);
+
+	ret = hisi_l3c_init_topology(l3c, &pdev->dev);
+	if (ret)
+		goto err_xa;
+
+	ret = cpuhp_state_add_instance(hisi_l3c_cpuhp_state, &l3c->node);
+	if (ret)
+		goto err_xa;
+
+	hisi_soc_comp_add(&l3c->comp);
+
+	return 0;
+
+err_xa:
+	xa_destroy(&l3c->lock_sets);
+	return ret;
+}
+
+static void hisi_l3c_remove(struct platform_device *pdev)
+{
+	struct hisi_l3c *l3c = platform_get_drvdata(pdev);
+	unsigned long idx;
+	struct hisi_l3c_lock_region *entry;
+
+	hisi_l3c_remove_locks(l3c);
+
+	hisi_soc_comp_del(&l3c->comp);
+
+	cpuhp_state_remove_instance_nocalls(hisi_l3c_cpuhp_state, &l3c->node);
+
+	xa_for_each(&l3c->lock_sets, idx, entry)
+		entry = xa_erase(&l3c->lock_sets, idx);
+
+	xa_destroy(&l3c->lock_sets);
+}
+
+static void hisi_read_sccl_and_ccl_id(int *scclp, int *cclp)
+{
+	u64 mpidr = read_cpuid_mpidr();
+	int aff3 = MPIDR_AFFINITY_LEVEL(mpidr, 3);
+	int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+	int aff1 = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+	int sccl, ccl;
+
+	if (mpidr & MPIDR_MT_BITMASK) {
+		sccl = aff3;
+		ccl = aff2;
+	} else {
+		sccl = aff2;
+		ccl = aff1;
+	}
+
+	*scclp = sccl;
+	*cclp = ccl;
+}
+
+static bool hisi_l3c_is_associated(struct hisi_l3c *l3c)
+{
+	int sccl_id, ccl_id;
+
+	hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
+
+	return sccl_id == l3c->sccl_id && ccl_id == l3c->ccl_id;
+}
+
+static int hisi_l3c_online_cpu(unsigned int cpu, struct hlist_node *node)
+{
+	struct hisi_l3c *l3c = hlist_entry_safe(node, struct hisi_l3c, node);
+
+	if (!cpumask_test_cpu(cpu, &l3c->associated_cpus)) {
+		if (!(hisi_l3c_is_associated(l3c)))
+			return 0;
+
+		cpumask_set_cpu(cpu, &l3c->associated_cpus);
+		cpumask_copy(&l3c->comp.affinity_mask,
+			     &l3c->associated_cpus);
+	}
+	return 0;
+}
+
+static const struct acpi_device_id hisi_l3c_acpi_match[] = {
+	{ "HISI0501", },
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, hisi_l3c_acpi_match);
+
+static struct platform_driver hisi_l3c_driver = {
+	.driver = {
+		.name = "hisi_l3c",
+		.acpi_match_table = hisi_l3c_acpi_match,
+	},
+	.probe = hisi_l3c_probe,
+	.remove = hisi_l3c_remove,
+};
+
 static long hisi_l3c_ioctl(struct file *file, u32 cmd, unsigned long arg)
 {
 	switch (cmd) {
@@ -340,15 +832,41 @@ static struct miscdevice l3c_miscdev = {
 
 static int __init hisi_l3c_init(void)
 {
+	int ret;
+
 	spin_lock_init(&l3c_devs.lock);
 	INIT_LIST_HEAD(&l3c_devs.node);
 
-	return misc_register(&l3c_miscdev);
+	ret = misc_register(&l3c_miscdev);
+	if (ret)
+		return ret;
+
+	ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "hisi_l3c",
+				      hisi_l3c_online_cpu, NULL);
+	if (ret < 0)
+		goto err_hp;
+
+	hisi_l3c_cpuhp_state = ret;
+
+	ret = platform_driver_register(&hisi_l3c_driver);
+	if (ret)
+		goto err_plat;
+
+	return 0;
+
+err_plat:
+	cpuhp_remove_multi_state(CPUHP_AP_ONLINE_DYN);
+err_hp:
+	misc_deregister(&l3c_miscdev);
+
+	return ret;
 }
 module_init(hisi_l3c_init);
 
 static void __exit hisi_l3c_exit(void)
 {
+	platform_driver_unregister(&hisi_l3c_driver);
+	cpuhp_remove_multi_state(CPUHP_AP_ONLINE_DYN);
 	misc_deregister(&l3c_miscdev);
 	hisi_soc_comp_del(NULL);
 }
-- 
2.33.0

[RFC PATCH 3/3] Documentation: soc cache: Add documentation to HiSilicon SoC cache

[Yushan Wang]

Add necessary documentation to HiSilicon SoC cache for reference.

Signed-off-by: Yushan Wang <wangyushan12@huawei.com>
---
 Documentation/driver-api/hisi-soc-cache.rst | 62 +++++++++++++++++++++
 Documentation/driver-api/index.rst          |  1 +
 2 files changed, 63 insertions(+)
 create mode 100644 Documentation/driver-api/hisi-soc-cache.rst

diff --git a/Documentation/driver-api/hisi-soc-cache.rst b/Documentation/driver-api/hisi-soc-cache.rst
new file mode 100644
index 000000000000..a0da7ff20e44
--- /dev/null
+++ b/Documentation/driver-api/hisi-soc-cache.rst
@@ -0,0 +1,62 @@
+==========================
+HiSilicon SoC Cache Driver
+==========================
+
+Introduction
+===========
+
+HiSilicon SoC cache provides the capabilities of preventing given range of
+memory from being evicted from L3 cache. The driver exports the lockdown API to
+userspace, allowing allocation of memory that is guranteed to be placed in L3
+cache, thus decreasing average memory access latency.
+
+Usage
+=====
+
+Kernel built with CONFIG_HISI_SOC_CACHE on will have the device file at
+`/dev/hisi_l3c`, cache operations can be performed through it.
+
+mmap():
+-------
+
+This interface can be used to allocate memory that is guranteed to not be
+evicted out of HiSilicon L3 cache. Newly allocated memory will be prefetched to
+L3 cache automatically.
+
+Users should set `PROT_READ` or `PROT_WRITE` to enable read/write to the memory
+region. Once mmap call succeeds, read and write can be applied to the memory
+region indicated by the returned pointer.
+
+Calling `munmap()` to the pointer can be used to unlock the memory regions.
+
+Restrictions of the cache lockdown are listed below:
+  - Only limited number of memory regions are supported, the exact number is
+    reported by firmware.
+  - Sum of the sizes of locked memory regions should be less than 70% of the
+    total size of cache instance.
+  - Lock/unlock can only be performed during allocation/deallocation, locking
+    existing memory is not supported yet.
+
+ioctl():
+--------
+
+This interface provides useful information of HiSilicon L3 cache.
+
+HISI_L3C_LOCK_INFO
+  - struct hisi_l3c_lock_info (read)
+
+  Gets detailed information of L3 cache lock restrictions.
+
+This ioctl call returns the detailed information of HiSilicon L3 cache lock
+restriction. Information will be presented in the form of::
+
+        struct hisi_l3c_lock_info {
+                unsigned int lock_region_num;
+                size_t lock_size;
+                bool address_alignment;
+                size_t max_lock_size;
+                size_t min_lock_size;
+        };
+
+User may perform a query before issueing cache lock to check for available
+resource.
diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/index.rst
index 3e2a270bd828..a4be1fc67230 100644
--- a/Documentation/driver-api/index.rst
+++ b/Documentation/driver-api/index.rst
@@ -94,6 +94,7 @@ Subsystem-specific APIs
    aperture
    generic-counter
    gpio/index
+   hisi-soc-cache
    hsi
    hte/index
    i2c
-- 
2.33.0

Re: [RFC PATCH 3/3] Documentation: soc cache: Add documentation to HiSilicon SoC cache

[kernel test robot]

Hi Yushan,

[This is a private test report for your RFC patch.]
kernel test robot noticed the following build warnings:

[auto build test WARNING on soc/for-next]
[also build test WARNING on linus/master v6.18-rc7]
[cannot apply to next-20251126]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Yushan-Wang/soc-cache-L3-cache-driver-for-HiSilicon-SoC/20251125-160816
base:   https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
patch link:    https://lore.kernel.org/r/20251125080542.3721829-4-wangyushan12%40huawei.com
patch subject: [RFC PATCH 3/3] Documentation: soc cache: Add documentation to HiSilicon SoC cache
reproduce: (https://download.01.org/0day-ci/archive/20251126/202511261420.otuMPDcN-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511261420.otuMPDcN-lkp@intel.com/

All warnings (new ones prefixed by >>):

   ERROR: Cannot find file ./include/linux/counter.h
   WARNING: No kernel-doc for file ./include/linux/counter.h
   ERROR: Cannot find file ./include/linux/gpio/driver.h
   ERROR: Cannot find file ./include/linux/gpio/driver.h
   WARNING: No kernel-doc for file ./include/linux/gpio/driver.h
>> Documentation/driver-api/hisi-soc-cache.rst:6: WARNING: Title underline too short.


vim +6 Documentation/driver-api/hisi-soc-cache.rst

     4	
     5	Introduction
   > 6	===========
     7	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [RFC PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC

[kernel test robot]

Hi Yushan,

[This is a private test report for your RFC patch.]
kernel test robot noticed the following build errors:

[auto build test ERROR on soc/for-next]
[also build test ERROR on linus/master v6.18-rc7]
[cannot apply to next-20251126]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Yushan-Wang/soc-cache-L3-cache-driver-for-HiSilicon-SoC/20251125-160816
base:   https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
patch link:    https://lore.kernel.org/r/20251125080542.3721829-2-wangyushan12%40huawei.com
patch subject: [RFC PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC
config: x86_64-rhel-9.4-ltp (https://download.01.org/0day-ci/archive/20251126/202511261539.RGBE3ddC-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251126/202511261539.RGBE3ddC-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511261539.RGBE3ddC-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from <command-line>:
>> ./usr/include/misc/hisi_l3c.h:22:9: error: unknown type name 'size_t'
      22 |         size_t lock_size;
         |         ^~~~~~
   ./usr/include/misc/hisi_l3c.h:7:1: note: 'size_t' is defined in header '<stddef.h>'; this is probably fixable by adding '#include <stddef.h>'
       6 | #include <linux/types.h>
     +++ |+#include <stddef.h>
       7 | 
>> ./usr/include/misc/hisi_l3c.h:23:9: error: unknown type name 'bool'
      23 |         bool address_alignment;
         |         ^~~~
   ./usr/include/misc/hisi_l3c.h:24:9: error: unknown type name 'size_t'
      24 |         size_t max_lock_size;
         |         ^~~~~~
   ./usr/include/misc/hisi_l3c.h:24:9: note: 'size_t' is defined in header '<stddef.h>'; this is probably fixable by adding '#include <stddef.h>'
   ./usr/include/misc/hisi_l3c.h:25:9: error: unknown type name 'size_t'
      25 |         size_t min_lock_size;
         |         ^~~~~~
   ./usr/include/misc/hisi_l3c.h:25:9: note: 'size_t' is defined in header '<stddef.h>'; this is probably fixable by adding '#include <stddef.h>'

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Re: [RFC PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC

[kernel test robot]

Hi Yushan,

[This is a private test report for your RFC patch.]
kernel test robot noticed the following build errors:

[auto build test ERROR on soc/for-next]
[also build test ERROR on linus/master v6.18-rc7]
[cannot apply to next-20251127]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Yushan-Wang/soc-cache-L3-cache-driver-for-HiSilicon-SoC/20251125-160816
base:   https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
patch link:    https://lore.kernel.org/r/20251125080542.3721829-2-wangyushan12%40huawei.com
patch subject: [RFC PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC
config: um-randconfig-001-20251128 (https://download.01.org/0day-ci/archive/20251128/202511281454.4H2aIAJS-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project b3428bb966f1de8aa48375ffee0eba04ede133b7)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251128/202511281454.4H2aIAJS-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511281454.4H2aIAJS-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from <built-in>:1:
>> ./usr/include/misc/hisi_l3c.h:22:2: error: unknown type name 'size_t'
      22 |         size_t lock_size;
         |         ^
>> ./usr/include/misc/hisi_l3c.h:23:2: error: unknown type name 'bool'
      23 |         bool address_alignment;
         |         ^
   ./usr/include/misc/hisi_l3c.h:24:2: error: unknown type name 'size_t'
      24 |         size_t max_lock_size;
         |         ^
   ./usr/include/misc/hisi_l3c.h:25:2: error: unknown type name 'size_t'
      25 |         size_t min_lock_size;
         |         ^
   4 errors generated.

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for I2C_K1
   Depends on [n]: I2C [=y] && HAS_IOMEM [=y] && (ARCH_SPACEMIT || COMPILE_TEST [=y]) && OF [=n]
   Selected by [y]:
   - MFD_SPACEMIT_P1 [=y] && HAS_IOMEM [=y] && (ARCH_SPACEMIT || COMPILE_TEST [=y]) && I2C [=y]

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