From: Rob Herring <robh@kernel.org>
To: Jacky Chou <jacky_chou@aspeedtech.com>
Cc: "Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Joel Stanley" <joel@jms.id.au>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Andrew Jeffery" <andrew@aj.id.au>,
"openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>
Subject: Re: [PATCH v6 0/7] Add ASPEED PCIe Root Complex support
Date: Fri, 5 Dec 2025 18:08:06 -0600 [thread overview]
Message-ID: <20251206000806.GA969079-robh@kernel.org> (raw)
In-Reply-To: <SEYPR06MB5134D0D5911E3C86D869151E9DA7A@SEYPR06MB5134.apcprd06.prod.outlook.com>
On Fri, Dec 05, 2025 at 12:12:35AM +0000, Jacky Chou wrote:
> Hi Rob,
>
> Thanks for your comments.
>
> > > Changes in v6:
> > > - Refer to pci-cpi-bridge.yaml to update aspeed,ast2600-pcie.yaml and
> > > the pcie node of aspeed-g6.dtsi.
> >
> > Where is this? You don't describe the root port and its properties at all now.
> >
>
> May I confirm whether the pcie@8,0 in aspeed-g6.dtsi is not considered the
> root port? From my understanding, that node represents the root port, so I
> want to make sure I'm aligning with your expectation before updating the binding.
I believe you told me it was the root port.
> Could you help clarify how you would like the root port and its properties to
> be described in the schema?
properties:
pcie@8,0:
$ref: /schemas/pci/pci-pci-bridge.yaml#
unevaluatedProperties: false
properties:
And then add all the properties you have which are not defined in
pci-pci-bridge.yaml (and pci-device.yaml by reference) (i.e. clocks,
resets, phys, etc.).
Rob
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Jacky Chou <jacky_chou@aspeedtech.com>
Cc: "Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Joel Stanley" <joel@jms.id.au>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Andrew Jeffery" <andrew@aj.id.au>,
"openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>
Subject: Re: [PATCH v6 0/7] Add ASPEED PCIe Root Complex support
Date: Fri, 5 Dec 2025 18:08:06 -0600 [thread overview]
Message-ID: <20251206000806.GA969079-robh@kernel.org> (raw)
In-Reply-To: <SEYPR06MB5134D0D5911E3C86D869151E9DA7A@SEYPR06MB5134.apcprd06.prod.outlook.com>
On Fri, Dec 05, 2025 at 12:12:35AM +0000, Jacky Chou wrote:
> Hi Rob,
>
> Thanks for your comments.
>
> > > Changes in v6:
> > > - Refer to pci-cpi-bridge.yaml to update aspeed,ast2600-pcie.yaml and
> > > the pcie node of aspeed-g6.dtsi.
> >
> > Where is this? You don't describe the root port and its properties at all now.
> >
>
> May I confirm whether the pcie@8,0 in aspeed-g6.dtsi is not considered the
> root port? From my understanding, that node represents the root port, so I
> want to make sure I'm aligning with your expectation before updating the binding.
I believe you told me it was the root port.
> Could you help clarify how you would like the root port and its properties to
> be described in the schema?
properties:
pcie@8,0:
$ref: /schemas/pci/pci-pci-bridge.yaml#
unevaluatedProperties: false
properties:
And then add all the properties you have which are not defined in
pci-pci-bridge.yaml (and pci-device.yaml by reference) (i.e. clocks,
resets, phys, etc.).
Rob
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2025-12-06 0:08 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-01 6:29 [PATCH v6 0/7] Add ASPEED PCIe Root Complex support Jacky Chou
2025-12-01 6:29 ` Jacky Chou
2025-12-01 6:29 ` [PATCH v6 1/7] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY Jacky Chou
2025-12-01 6:29 ` Jacky Chou
2025-12-01 6:29 ` [PATCH v6 2/7] dt-bindings: PCI: Add ASPEED PCIe RC support Jacky Chou
2025-12-01 6:29 ` Jacky Chou
2025-12-01 6:29 ` [PATCH v6 3/7] ARM: dts: aspeed-g6: Add PCIe RC and PCIe PHY node Jacky Chou
2025-12-01 6:29 ` Jacky Chou
2025-12-01 6:29 ` [PATCH v6 4/7] PHY: aspeed: Add ASPEED PCIe PHY driver Jacky Chou
2025-12-01 6:29 ` Jacky Chou
2025-12-01 6:29 ` [PATCH v6 5/7] PCI: Add FMT, TYPE and CPL status definition for TLP header Jacky Chou
2025-12-01 6:29 ` Jacky Chou
2025-12-01 6:29 ` [PATCH v6 6/7] PCI: aspeed: Add ASPEED PCIe RC driver Jacky Chou
2025-12-01 6:29 ` Jacky Chou
2025-12-09 0:11 ` Bjorn Helgaas
2025-12-09 0:11 ` Bjorn Helgaas
2025-12-10 2:17 ` Jacky Chou
2025-12-10 2:17 ` Jacky Chou
2025-12-01 6:29 ` [PATCH v6 7/7] MAINTAINERS: " Jacky Chou
2025-12-01 6:29 ` Jacky Chou
2025-12-04 19:53 ` [PATCH v6 0/7] Add ASPEED PCIe Root Complex support Rob Herring
2025-12-04 19:53 ` Rob Herring
2025-12-05 0:12 ` Jacky Chou
2025-12-05 0:12 ` Jacky Chou
2025-12-06 0:08 ` Rob Herring [this message]
2025-12-06 0:08 ` Rob Herring
2025-12-08 3:01 ` Jacky Chou
2025-12-08 3:01 ` Jacky Chou
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