From: Jay Chang <jay.chang@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Jay Chang <jay.chang@sifive.com>,
Frank Chang <frank.chang@sifive.com>
Subject: [PATCH 1/2] hw/riscv: Don't insert DDT cache in Bare mode
Date: Thu, 11 Dec 2025 10:56:10 +0800 [thread overview]
Message-ID: <20251211025611.99038-2-jay.chang@sifive.com> (raw)
In-Reply-To: <20251211025611.99038-1-jay.chang@sifive.com>
In Bare mode the IOMMU does not perform DDT look-ups, therefore
caching DDT entries is unnecessary.
Signed-off-by: Jay Chang <jay.chang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
hw/riscv/riscv-iommu.c | 23 +++++++++++++++--------
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 69852f4f13..79eee2e85e 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -1312,16 +1312,23 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
int fault = riscv_iommu_ctx_fetch(s, ctx);
if (!fault) {
- if (g_hash_table_size(ctx_cache) >= LIMIT_CACHE_CTX) {
+ if (mode != RISCV_IOMMU_DDTP_MODE_BARE) {
+ if (g_hash_table_size(ctx_cache) >= LIMIT_CACHE_CTX) {
+ g_hash_table_unref(ctx_cache);
+ ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
+ riscv_iommu_ctx_equal,
+ g_free, NULL);
+ g_hash_table_ref(ctx_cache);
+ g_hash_table_unref(qatomic_xchg(&s->ctx_cache, ctx_cache));
+ }
+
+ g_hash_table_add(ctx_cache, ctx);
+ *ref = ctx_cache;
+ } else {
g_hash_table_unref(ctx_cache);
- ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
- riscv_iommu_ctx_equal,
- g_free, NULL);
- g_hash_table_ref(ctx_cache);
- g_hash_table_unref(qatomic_xchg(&s->ctx_cache, ctx_cache));
+ /* Remember ctx so it can be freed */
+ *ref = ctx;
}
- g_hash_table_add(ctx_cache, ctx);
- *ref = ctx_cache;
return ctx;
}
--
2.48.1
next prev parent reply other threads:[~2025-12-11 2:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-11 2:56 [PATCH 0/2] Don't insert DDT cache in Bare mode Jay Chang
2025-12-11 2:56 ` Jay Chang [this message]
2025-12-27 12:24 ` [PATCH 1/2] hw/riscv: " Daniel Henrique Barboza
2025-12-31 10:20 ` Nutty.Liu
2025-12-11 2:56 ` [PATCH 2/2] hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling Jay Chang
2025-12-27 12:24 ` Daniel Henrique Barboza
2025-12-31 10:21 ` Nutty.Liu
2026-05-18 2:36 ` [PATCH 0/2] Don't insert DDT cache in Bare mode Jay Chang
2026-05-18 5:05 ` Alistair Francis
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