Re: [PATCH 2/2] hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling

[Daniel Henrique Barboza <dbarboza@ventanamicro.com>]

On 12/10/25 11:56 PM, Jay Chang wrote:
> Align SPEC: Bare mode contexts are not cached, so they require
> direct memory deallocation via g_free instead of hash table cleanup.
> 
> Signed-off-by: Jay Chang <jay.chang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---


Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   hw/riscv/riscv-iommu.c | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 79eee2e85e..fca5763858 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -1344,7 +1344,16 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
>   
>   static void riscv_iommu_ctx_put(RISCVIOMMUState *s, void *ref)
>   {
> -    if (ref) {
> +    unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
> +
> +    if (!ref) {
> +        return;
> +    }
> +
> +    /* ref is pointing to ctx in Bare mode. Bare mode ctx is not cached */
> +    if (mode == RISCV_IOMMU_DDTP_MODE_BARE) {
> +        g_free(ref);
> +    } else {
>           g_hash_table_unref((GHashTable *)ref);
>       }
>   }