[PATCH 0/2] Don't insert DDT cache in Bare mode

[PATCH 0/2] Don't insert DDT cache in Bare mode

[Jay Chang]

When IOMMU is in Bare mode, DDT (Device Directory Table) lookup is not
performed. This series fixes two issues:

1. Avoid inserting unnecessary DDT cache entries in Bare mode
2. Properly free Bare mode contexts to prevent memory leaks

Jay Chang (2):
  hw/riscv: Don't insert DDT cache in Bare mode
  hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling

 hw/riscv/riscv-iommu.c | 34 +++++++++++++++++++++++++---------
 1 file changed, 25 insertions(+), 9 deletions(-)

-- 
2.48.1

[PATCH 1/2] hw/riscv: Don't insert DDT cache in Bare mode

[Jay Chang]

In Bare mode the IOMMU does not perform DDT look-ups, therefore
caching DDT entries is unnecessary.

Signed-off-by: Jay Chang <jay.chang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
 hw/riscv/riscv-iommu.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 69852f4f13..79eee2e85e 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -1312,16 +1312,23 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
 
     int fault = riscv_iommu_ctx_fetch(s, ctx);
     if (!fault) {
-        if (g_hash_table_size(ctx_cache) >= LIMIT_CACHE_CTX) {
+        if (mode != RISCV_IOMMU_DDTP_MODE_BARE) {
+            if (g_hash_table_size(ctx_cache) >= LIMIT_CACHE_CTX) {
+                g_hash_table_unref(ctx_cache);
+                ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
+                                                  riscv_iommu_ctx_equal,
+                                                  g_free, NULL);
+                g_hash_table_ref(ctx_cache);
+                g_hash_table_unref(qatomic_xchg(&s->ctx_cache, ctx_cache));
+            }
+
+            g_hash_table_add(ctx_cache, ctx);
+            *ref = ctx_cache;
+        } else {
             g_hash_table_unref(ctx_cache);
-            ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
-                                              riscv_iommu_ctx_equal,
-                                              g_free, NULL);
-            g_hash_table_ref(ctx_cache);
-            g_hash_table_unref(qatomic_xchg(&s->ctx_cache, ctx_cache));
+            /* Remember ctx so it can be freed */
+            *ref = ctx;
         }
-        g_hash_table_add(ctx_cache, ctx);
-        *ref = ctx_cache;
         return ctx;
     }
 
-- 
2.48.1

[PATCH 2/2] hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling

[Jay Chang]

Align SPEC: Bare mode contexts are not cached, so they require
direct memory deallocation via g_free instead of hash table cleanup.

Signed-off-by: Jay Chang <jay.chang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
 hw/riscv/riscv-iommu.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 79eee2e85e..fca5763858 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -1344,7 +1344,16 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
 
 static void riscv_iommu_ctx_put(RISCVIOMMUState *s, void *ref)
 {
-    if (ref) {
+    unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
+
+    if (!ref) {
+        return;
+    }
+
+    /* ref is pointing to ctx in Bare mode. Bare mode ctx is not cached */
+    if (mode == RISCV_IOMMU_DDTP_MODE_BARE) {
+        g_free(ref);
+    } else {
         g_hash_table_unref((GHashTable *)ref);
     }
 }
-- 
2.48.1

Re: [PATCH 1/2] hw/riscv: Don't insert DDT cache in Bare mode

[Daniel Henrique Barboza]

On 12/10/25 11:56 PM, Jay Chang wrote:
> In Bare mode the IOMMU does not perform DDT look-ups, therefore
> caching DDT entries is unnecessary.
> 
> Signed-off-by: Jay Chang <jay.chang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   hw/riscv/riscv-iommu.c | 23 +++++++++++++++--------
>   1 file changed, 15 insertions(+), 8 deletions(-)
> 
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 69852f4f13..79eee2e85e 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -1312,16 +1312,23 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
>   
>       int fault = riscv_iommu_ctx_fetch(s, ctx);
>       if (!fault) {
> -        if (g_hash_table_size(ctx_cache) >= LIMIT_CACHE_CTX) {
> +        if (mode != RISCV_IOMMU_DDTP_MODE_BARE) {
> +            if (g_hash_table_size(ctx_cache) >= LIMIT_CACHE_CTX) {
> +                g_hash_table_unref(ctx_cache);
> +                ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
> +                                                  riscv_iommu_ctx_equal,
> +                                                  g_free, NULL);
> +                g_hash_table_ref(ctx_cache);
> +                g_hash_table_unref(qatomic_xchg(&s->ctx_cache, ctx_cache));
> +            }
> +
> +            g_hash_table_add(ctx_cache, ctx);
> +            *ref = ctx_cache;
> +        } else {
>               g_hash_table_unref(ctx_cache);
> -            ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
> -                                              riscv_iommu_ctx_equal,
> -                                              g_free, NULL);
> -            g_hash_table_ref(ctx_cache);
> -            g_hash_table_unref(qatomic_xchg(&s->ctx_cache, ctx_cache));
> +            /* Remember ctx so it can be freed */
> +            *ref = ctx;
>           }
> -        g_hash_table_add(ctx_cache, ctx);
> -        *ref = ctx_cache;
>           return ctx;
>       }
>   

Re: [PATCH 2/2] hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling

[Daniel Henrique Barboza]

On 12/10/25 11:56 PM, Jay Chang wrote:
> Align SPEC: Bare mode contexts are not cached, so they require
> direct memory deallocation via g_free instead of hash table cleanup.
> 
> Signed-off-by: Jay Chang <jay.chang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---


Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   hw/riscv/riscv-iommu.c | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 79eee2e85e..fca5763858 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -1344,7 +1344,16 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
>   
>   static void riscv_iommu_ctx_put(RISCVIOMMUState *s, void *ref)
>   {
> -    if (ref) {
> +    unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
> +
> +    if (!ref) {
> +        return;
> +    }
> +
> +    /* ref is pointing to ctx in Bare mode. Bare mode ctx is not cached */
> +    if (mode == RISCV_IOMMU_DDTP_MODE_BARE) {
> +        g_free(ref);
> +    } else {
>           g_hash_table_unref((GHashTable *)ref);
>       }
>   }

Re: [PATCH 1/2] hw/riscv: Don't insert DDT cache in Bare mode

[Nutty.Liu]

On 12/11/2025 10:56 AM, Jay Chang wrote:
> In Bare mode the IOMMU does not perform DDT look-ups, therefore
> caching DDT entries is unnecessary.
>
> Signed-off-by: Jay Chang <jay.chang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>

Thanks,
Nutty
>   hw/riscv/riscv-iommu.c | 23 +++++++++++++++--------
>   1 file changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 69852f4f13..79eee2e85e 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -1312,16 +1312,23 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
>   
>       int fault = riscv_iommu_ctx_fetch(s, ctx);
>       if (!fault) {
> -        if (g_hash_table_size(ctx_cache) >= LIMIT_CACHE_CTX) {
> +        if (mode != RISCV_IOMMU_DDTP_MODE_BARE) {
> +            if (g_hash_table_size(ctx_cache) >= LIMIT_CACHE_CTX) {
> +                g_hash_table_unref(ctx_cache);
> +                ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
> +                                                  riscv_iommu_ctx_equal,
> +                                                  g_free, NULL);
> +                g_hash_table_ref(ctx_cache);
> +                g_hash_table_unref(qatomic_xchg(&s->ctx_cache, ctx_cache));
> +            }
> +
> +            g_hash_table_add(ctx_cache, ctx);
> +            *ref = ctx_cache;
> +        } else {
>               g_hash_table_unref(ctx_cache);
> -            ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
> -                                              riscv_iommu_ctx_equal,
> -                                              g_free, NULL);
> -            g_hash_table_ref(ctx_cache);
> -            g_hash_table_unref(qatomic_xchg(&s->ctx_cache, ctx_cache));
> +            /* Remember ctx so it can be freed */
> +            *ref = ctx;
>           }
> -        g_hash_table_add(ctx_cache, ctx);
> -        *ref = ctx_cache;
>           return ctx;
>       }
>   

Re: [PATCH 2/2] hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling

[Nutty.Liu]

On 12/11/2025 10:56 AM, Jay Chang wrote:
> Align SPEC: Bare mode contexts are not cached, so they require
> direct memory deallocation via g_free instead of hash table cleanup.
>
> Signed-off-by: Jay Chang <jay.chang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>

Thanks,
Nutty
>   hw/riscv/riscv-iommu.c | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 79eee2e85e..fca5763858 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -1344,7 +1344,16 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
>   
>   static void riscv_iommu_ctx_put(RISCVIOMMUState *s, void *ref)
>   {
> -    if (ref) {
> +    unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
> +
> +    if (!ref) {
> +        return;
> +    }
> +
> +    /* ref is pointing to ctx in Bare mode. Bare mode ctx is not cached */
> +    if (mode == RISCV_IOMMU_DDTP_MODE_BARE) {
> +        g_free(ref);
> +    } else {
>           g_hash_table_unref((GHashTable *)ref);
>       }
>   }

Re: [PATCH 0/2] Don't insert DDT cache in Bare mode

[Jay Chang]

[-- Attachment #1: Type: text/plain, Size: 675 bytes --]

Hi,

Gentle ping on this patch.

Thanks,
Jay Chang

On Thu, Dec 11, 2025 at 10:56 AM Jay Chang <jay.chang@sifive.com> wrote:

> When IOMMU is in Bare mode, DDT (Device Directory Table) lookup is not
> performed. This series fixes two issues:
>
> 1. Avoid inserting unnecessary DDT cache entries in Bare mode
> 2. Properly free Bare mode contexts to prevent memory leaks
>
> Jay Chang (2):
>   hw/riscv: Don't insert DDT cache in Bare mode
>   hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling
>
>  hw/riscv/riscv-iommu.c | 34 +++++++++++++++++++++++++---------
>  1 file changed, 25 insertions(+), 9 deletions(-)
>
> --
> 2.48.1
>
>

[-- Attachment #2: Type: text/html, Size: 1058 bytes --]

Re: [PATCH 0/2] Don't insert DDT cache in Bare mode

[Alistair Francis]

On Mon, May 18, 2026 at 12:38 PM Jay Chang <jay.chang@sifive.com> wrote:
>
> Hi,
>
> Gentle ping on this patch.

Can you please resend the series, I lost this the first time around

Alistair

>
> Thanks,
> Jay Chang
>
> On Thu, Dec 11, 2025 at 10:56 AM Jay Chang <jay.chang@sifive.com> wrote:
>>
>> When IOMMU is in Bare mode, DDT (Device Directory Table) lookup is not
>> performed. This series fixes two issues:
>>
>> 1. Avoid inserting unnecessary DDT cache entries in Bare mode
>> 2. Properly free Bare mode contexts to prevent memory leaks
>>
>> Jay Chang (2):
>>   hw/riscv: Don't insert DDT cache in Bare mode
>>   hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling
>>
>>  hw/riscv/riscv-iommu.c | 34 +++++++++++++++++++++++++---------
>>  1 file changed, 25 insertions(+), 9 deletions(-)
>>
>> --
>> 2.48.1
>>