[PATCH 0/4] Power10 PowerVM bringup fixes

[PATCH 0/4] Power10 PowerVM bringup fixes

[Caleb Schlossin]

Additional fixes for bringing up PowerVM on Power10 ranging from
chiptod, security, core, and OCC.

Tested:
passed make check

Glenn Miles (2):
  ppc/pnv: Suppress some "pnv_chiptod unimplemented register" messages
  ppc/pnv: Support for SECURITY_SWITCH XSCOM register access

Chalapathi V (2):
  ppc/pnv: Add unimplemented quad and core regs
  ppc/pnv: Add OCC FLAG registers

 hw/ppc/pnv_chiptod.c     | 18 +++++++++
 hw/ppc/pnv_core.c        | 81 ++++++++++++++++++++++++++++++++++++++++
 hw/ppc/pnv_occ.c         | 55 +++++++++++++++++++++++++--
 hw/ppc/pnv_xscom.c       |  2 +
 include/hw/ppc/pnv_occ.h |  4 ++
 5 files changed, 157 insertions(+), 3 deletions(-)

-- 
2.47.3

[PATCH 1/4] ppc/pnv: Suppress some "pnv_chiptod unimplemented register" messages

[Caleb Schlossin]

This commit suppresses the following informational messages
regarding unimplemented pnv_chiptod registers:

pnv_chiptod: unimplemented register: Ox0
pnv_chiptod: unimplemented register: Ox1
pnv_chiptod: unimplemented register: Ox2
pnv_chiptod: unimplemented register: Ox3
pnv_chiptod: unimplemented register: Ox4
pnv_chiptod: unimplemented register: Ox5
pnv_chiptod: unimplemented register: Ox13

Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
 hw/ppc/pnv_chiptod.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c
index f887a18cde..cd9b8ee348 100644
--- a/hw/ppc/pnv_chiptod.c
+++ b/hw/ppc/pnv_chiptod.c
@@ -145,6 +145,15 @@ static uint64_t pnv_chiptod_xscom_read(void *opaque, hwaddr addr,
             val |= PPC_BIT(4);
         }
         break;
+    case TOD_M_PATH_CTRL_REG:
+    case TOD_PRI_PORT_0_CTRL_REG:
+    case TOD_PRI_PORT_1_CTRL_REG:
+    case TOD_SEC_PORT_0_CTRL_REG:
+    case TOD_SEC_PORT_1_CTRL_REG:
+    case TOD_S_PATH_CTRL_REG:
+    case TOD_TX_TTYPE_2_REG:
+        /* unimplemented, but suppressing logging for now */
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
                       HWADDR_PRIx "\n", addr >> 3);
@@ -420,6 +429,15 @@ static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
     case TOD_TX_TTYPE_5_REG:
         pctc->broadcast_ttype(chiptod, offset);
         break;
+    case TOD_M_PATH_CTRL_REG:
+    case TOD_PRI_PORT_0_CTRL_REG:
+    case TOD_PRI_PORT_1_CTRL_REG:
+    case TOD_SEC_PORT_0_CTRL_REG:
+    case TOD_SEC_PORT_1_CTRL_REG:
+    case TOD_S_PATH_CTRL_REG:
+    case TOD_TX_TTYPE_2_REG:
+        /* unimplemented, but suppressing logging for now */
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
                       HWADDR_PRIx "\n", addr >> 3);
-- 
2.47.3

Re: [PATCH 1/4] ppc/pnv: Suppress some "pnv_chiptod unimplemented register" messages

[Chalapathi V]

[-- Attachment #1: Type: text/plain, Size: 2212 bytes --]

Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com> 
<mailto:milesg@linux.ibm.com>


On 19/12/25 1:33 am, Caleb Schlossin wrote:
> This commit suppresses the following informational messages
> regarding unimplemented pnv_chiptod registers:
>
> pnv_chiptod: unimplemented register: Ox0
> pnv_chiptod: unimplemented register: Ox1
> pnv_chiptod: unimplemented register: Ox2
> pnv_chiptod: unimplemented register: Ox3
> pnv_chiptod: unimplemented register: Ox4
> pnv_chiptod: unimplemented register: Ox5
> pnv_chiptod: unimplemented register: Ox13
>
> Signed-off-by: Glenn Miles<milesg@linux.ibm.com>
> Signed-off-by: Caleb Schlossin<calebs@linux.ibm.com>
> ---
>   hw/ppc/pnv_chiptod.c | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
>
> diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c
> index f887a18cde..cd9b8ee348 100644
> --- a/hw/ppc/pnv_chiptod.c
> +++ b/hw/ppc/pnv_chiptod.c
> @@ -145,6 +145,15 @@ static uint64_t pnv_chiptod_xscom_read(void *opaque, hwaddr addr,
>               val |= PPC_BIT(4);
>           }
>           break;
> +    case TOD_M_PATH_CTRL_REG:
> +    case TOD_PRI_PORT_0_CTRL_REG:
> +    case TOD_PRI_PORT_1_CTRL_REG:
> +    case TOD_SEC_PORT_0_CTRL_REG:
> +    case TOD_SEC_PORT_1_CTRL_REG:
> +    case TOD_S_PATH_CTRL_REG:
> +    case TOD_TX_TTYPE_2_REG:
> +        /* unimplemented, but suppressing logging for now */
> +        break;
>       default:
>           qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
>                         HWADDR_PRIx "\n", addr >> 3);
> @@ -420,6 +429,15 @@ static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
>       case TOD_TX_TTYPE_5_REG:
>           pctc->broadcast_ttype(chiptod, offset);
>           break;
> +    case TOD_M_PATH_CTRL_REG:
> +    case TOD_PRI_PORT_0_CTRL_REG:
> +    case TOD_PRI_PORT_1_CTRL_REG:
> +    case TOD_SEC_PORT_0_CTRL_REG:
> +    case TOD_SEC_PORT_1_CTRL_REG:
> +    case TOD_S_PATH_CTRL_REG:
> +    case TOD_TX_TTYPE_2_REG:
> +        /* unimplemented, but suppressing logging for now */
> +        break;
>       default:
>           qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
>                         HWADDR_PRIx "\n", addr >> 3);

[-- Attachment #2: Type: text/html, Size: 2841 bytes --]

Re: [PATCH 1/4] ppc/pnv: Suppress some "pnv_chiptod unimplemented register" messages

[Miles Glenn]

Hi Caleb.  I wonder if it makes sense to upstream this commit since I
suspect that most upstream users will not have the "unimp" log messages
enabled unless they are debugging a problem and in that case, we would
be erroneously masking these unimplemented registers from the logged
output.

Thanks,

Glenn

On Thu, 2025-12-18 at 14:03 -0600, Caleb Schlossin wrote:
> This commit suppresses the following informational messages
> regarding unimplemented pnv_chiptod registers:
> 
> pnv_chiptod: unimplemented register: Ox0
> pnv_chiptod: unimplemented register: Ox1
> pnv_chiptod: unimplemented register: Ox2
> pnv_chiptod: unimplemented register: Ox3
> pnv_chiptod: unimplemented register: Ox4
> pnv_chiptod: unimplemented register: Ox5
> pnv_chiptod: unimplemented register: Ox13
> 
> Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
>  hw/ppc/pnv_chiptod.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c
> index f887a18cde..cd9b8ee348 100644
> --- a/hw/ppc/pnv_chiptod.c
> +++ b/hw/ppc/pnv_chiptod.c
> @@ -145,6 +145,15 @@ static uint64_t pnv_chiptod_xscom_read(void *opaque, hwaddr addr,
>              val |= PPC_BIT(4);
>          }
>          break;
> +    case TOD_M_PATH_CTRL_REG:
> +    case TOD_PRI_PORT_0_CTRL_REG:
> +    case TOD_PRI_PORT_1_CTRL_REG:
> +    case TOD_SEC_PORT_0_CTRL_REG:
> +    case TOD_SEC_PORT_1_CTRL_REG:
> +    case TOD_S_PATH_CTRL_REG:
> +    case TOD_TX_TTYPE_2_REG:
> +        /* unimplemented, but suppressing logging for now */
> +        break;
>      default:
>          qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
>                        HWADDR_PRIx "\n", addr >> 3);
> @@ -420,6 +429,15 @@ static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
>      case TOD_TX_TTYPE_5_REG:
>          pctc->broadcast_ttype(chiptod, offset);
>          break;
> +    case TOD_M_PATH_CTRL_REG:
> +    case TOD_PRI_PORT_0_CTRL_REG:
> +    case TOD_PRI_PORT_1_CTRL_REG:
> +    case TOD_SEC_PORT_0_CTRL_REG:
> +    case TOD_SEC_PORT_1_CTRL_REG:
> +    case TOD_S_PATH_CTRL_REG:
> +    case TOD_TX_TTYPE_2_REG:
> +        /* unimplemented, but suppressing logging for now */
> +        break;
>      default:
>          qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
>                        HWADDR_PRIx "\n", addr >> 3);

Re: [PATCH 1/4] ppc/pnv: Suppress some "pnv_chiptod unimplemented register" messages

[Caleb Schlossin]

On 1/6/26 10:49 AM, Miles Glenn wrote:
> Hi Caleb.  I wonder if it makes sense to upstream this commit since I
> suspect that most upstream users will not have the "unimp" log messages
> enabled unless they are debugging a problem and in that case, we would
> be erroneously masking these unimplemented registers from the logged
> output.
> 
> Thanks,
> 
> Glenn

I understand your point. Here are my thoughts:
- Cleaning up these logs for valid accesses (PowerVM bringup and development) reduces the overall log output and helps find real errors
- In the future, there may be a customer that wants to run PowerVM with upstream QEMU. The more we upstream, the easier that will be.
- In the future, we are going to have a number of cases like this where we accept accesses and don't log for every unimp access (to clean up log output). If we choose to keep those patches private and don't upstream them it's going to increase the number of private patches we keep, making future rebasing more difficult.
- I'd prefer to upstream more patches, and focus on keeping only the patches we need to private (for confidentiality or other reasons). To make future rebasing easier.

Feel free to contact me offline, if you'd like to discuss this further.

Thanks,
Caleb

> 
> On Thu, 2025-12-18 at 14:03 -0600, Caleb Schlossin wrote:
>> This commit suppresses the following informational messages
>> regarding unimplemented pnv_chiptod registers:
>>
>> pnv_chiptod: unimplemented register: Ox0
>> pnv_chiptod: unimplemented register: Ox1
>> pnv_chiptod: unimplemented register: Ox2
>> pnv_chiptod: unimplemented register: Ox3
>> pnv_chiptod: unimplemented register: Ox4
>> pnv_chiptod: unimplemented register: Ox5
>> pnv_chiptod: unimplemented register: Ox13
>>
>> Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
>> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
>> ---
>>  hw/ppc/pnv_chiptod.c | 18 ++++++++++++++++++
>>  1 file changed, 18 insertions(+)
>>
>> diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c
>> index f887a18cde..cd9b8ee348 100644
>> --- a/hw/ppc/pnv_chiptod.c
>> +++ b/hw/ppc/pnv_chiptod.c
>> @@ -145,6 +145,15 @@ static uint64_t pnv_chiptod_xscom_read(void *opaque, hwaddr addr,
>>              val |= PPC_BIT(4);
>>          }
>>          break;
>> +    case TOD_M_PATH_CTRL_REG:
>> +    case TOD_PRI_PORT_0_CTRL_REG:
>> +    case TOD_PRI_PORT_1_CTRL_REG:
>> +    case TOD_SEC_PORT_0_CTRL_REG:
>> +    case TOD_SEC_PORT_1_CTRL_REG:
>> +    case TOD_S_PATH_CTRL_REG:
>> +    case TOD_TX_TTYPE_2_REG:
>> +        /* unimplemented, but suppressing logging for now */
>> +        break;
>>      default:
>>          qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
>>                        HWADDR_PRIx "\n", addr >> 3);
>> @@ -420,6 +429,15 @@ static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
>>      case TOD_TX_TTYPE_5_REG:
>>          pctc->broadcast_ttype(chiptod, offset);
>>          break;
>> +    case TOD_M_PATH_CTRL_REG:
>> +    case TOD_PRI_PORT_0_CTRL_REG:
>> +    case TOD_PRI_PORT_1_CTRL_REG:
>> +    case TOD_SEC_PORT_0_CTRL_REG:
>> +    case TOD_SEC_PORT_1_CTRL_REG:
>> +    case TOD_S_PATH_CTRL_REG:
>> +    case TOD_TX_TTYPE_2_REG:
>> +        /* unimplemented, but suppressing logging for now */
>> +        break;
>>      default:
>>          qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
>>                        HWADDR_PRIx "\n", addr >> 3);
> 

Re: [PATCH 1/4] ppc/pnv: Suppress some "pnv_chiptod unimplemented register" messages

[Miles Glenn]

Ok, I can't say I have a strong opinion on this either way, so...

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>

Thanks,

Glenn

On Tue, 2026-01-06 at 11:07 -0600, Caleb Schlossin wrote:
> 
> On 1/6/26 10:49 AM, Miles Glenn wrote:
> > Hi Caleb.  I wonder if it makes sense to upstream this commit since I
> > suspect that most upstream users will not have the "unimp" log messages
> > enabled unless they are debugging a problem and in that case, we would
> > be erroneously masking these unimplemented registers from the logged
> > output.
> > 
> > Thanks,
> > 
> > Glenn
> 
> I understand your point. Here are my thoughts:
> - Cleaning up these logs for valid accesses (PowerVM bringup and development) reduces the overall log output and helps find real errors
> - In the future, there may be a customer that wants to run PowerVM with upstream QEMU. The more we upstream, the easier that will be.
> - In the future, we are going to have a number of cases like this where we accept accesses and don't log for every unimp access (to clean up log output). If we choose to keep those patches private and don't upstream them it's going to increase the number of private patches we keep, making future rebasing more difficult.
> - I'd prefer to upstream more patches, and focus on keeping only the patches we need to private (for confidentiality or other reasons). To make future rebasing easier.
> 
> Feel free to contact me offline, if you'd like to discuss this further.
> 
> Thanks,
> Caleb
> 
> > On Thu, 2025-12-18 at 14:03 -0600, Caleb Schlossin wrote:
> > > This commit suppresses the following informational messages
> > > regarding unimplemented pnv_chiptod registers:
> > > 
> > > pnv_chiptod: unimplemented register: Ox0
> > > pnv_chiptod: unimplemented register: Ox1
> > > pnv_chiptod: unimplemented register: Ox2
> > > pnv_chiptod: unimplemented register: Ox3
> > > pnv_chiptod: unimplemented register: Ox4
> > > pnv_chiptod: unimplemented register: Ox5
> > > pnv_chiptod: unimplemented register: Ox13
> > > 
> > > Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
> > > Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> > > ---
> > >  hw/ppc/pnv_chiptod.c | 18 ++++++++++++++++++
> > >  1 file changed, 18 insertions(+)
> > > 
> > > diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c
> > > index f887a18cde..cd9b8ee348 100644
> > > --- a/hw/ppc/pnv_chiptod.c
> > > +++ b/hw/ppc/pnv_chiptod.c
> > > @@ -145,6 +145,15 @@ static uint64_t pnv_chiptod_xscom_read(void *opaque, hwaddr addr,
> > >              val |= PPC_BIT(4);
> > >          }
> > >          break;
> > > +    case TOD_M_PATH_CTRL_REG:
> > > +    case TOD_PRI_PORT_0_CTRL_REG:
> > > +    case TOD_PRI_PORT_1_CTRL_REG:
> > > +    case TOD_SEC_PORT_0_CTRL_REG:
> > > +    case TOD_SEC_PORT_1_CTRL_REG:
> > > +    case TOD_S_PATH_CTRL_REG:
> > > +    case TOD_TX_TTYPE_2_REG:
> > > +        /* unimplemented, but suppressing logging for now */
> > > +        break;
> > >      default:
> > >          qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
> > >                        HWADDR_PRIx "\n", addr >> 3);
> > > @@ -420,6 +429,15 @@ static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
> > >      case TOD_TX_TTYPE_5_REG:
> > >          pctc->broadcast_ttype(chiptod, offset);
> > >          break;
> > > +    case TOD_M_PATH_CTRL_REG:
> > > +    case TOD_PRI_PORT_0_CTRL_REG:
> > > +    case TOD_PRI_PORT_1_CTRL_REG:
> > > +    case TOD_SEC_PORT_0_CTRL_REG:
> > > +    case TOD_SEC_PORT_1_CTRL_REG:
> > > +    case TOD_S_PATH_CTRL_REG:
> > > +    case TOD_TX_TTYPE_2_REG:
> > > +        /* unimplemented, but suppressing logging for now */
> > > +        break;
> > >      default:
> > >          qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
> > >                        HWADDR_PRIx "\n", addr >> 3);

Re: [PATCH 1/4] ppc/pnv: Suppress some "pnv_chiptod unimplemented register" messages

[Aditya Gupta]

On 26/01/06 11:07AM, Caleb Schlossin wrote:
> 
> 
> On 1/6/26 10:49 AM, Miles Glenn wrote:
> > Hi Caleb.  I wonder if it makes sense to upstream this commit since I
> > suspect that most upstream users will not have the "unimp" log messages
> > enabled unless they are debugging a problem and in that case, we would
> > be erroneously masking these unimplemented registers from the logged
> > output.
> > 
> > Thanks,
> > 
> > Glenn
> 
> I understand your point. Here are my thoughts:
> - Cleaning up these logs for valid accesses (PowerVM bringup and development) reduces the overall log output and helps find real errors
> - In the future, there may be a customer that wants to run PowerVM with upstream QEMU. The more we upstream, the easier that will be.
> - In the future, we are going to have a number of cases like this where we accept accesses and don't log for every unimp access (to clean up log output). If we choose to keep those patches private and don't upstream them it's going to increase the number of private patches we keep, making future rebasing more difficult.
> - I'd prefer to upstream more patches, and focus on keeping only the patches we need to private (for confidentiality or other reasons). To make future rebasing easier.

I agree with Glenn that we shouldn't mask these warnings for everyone.

Since a warning saying a feature is unimplemented is better than
silently not doing anything without any warnings.

Maybe the excessive warnings should only be masked for PowerMV
development work, rather than upstreaming, or we can always upstream
once those are implemented.

- Aditya G

Re: [PATCH 1/4] ppc/pnv: Suppress some "pnv_chiptod unimplemented register" messages

[Caleb Schlossin]

On 1/19/26 4:18 AM, Aditya Gupta wrote:
> On 26/01/06 11:07AM, Caleb Schlossin wrote:
>>
>>
>> On 1/6/26 10:49 AM, Miles Glenn wrote:
>>> Hi Caleb.  I wonder if it makes sense to upstream this commit since I
>>> suspect that most upstream users will not have the "unimp" log messages
>>> enabled unless they are debugging a problem and in that case, we would
>>> be erroneously masking these unimplemented registers from the logged
>>> output.
>>>
>>> Thanks,
>>>
>>> Glenn
>>
>> I understand your point. Here are my thoughts:
>> - Cleaning up these logs for valid accesses (PowerVM bringup and development) reduces the overall log output and helps find real errors
>> - In the future, there may be a customer that wants to run PowerVM with upstream QEMU. The more we upstream, the easier that will be.
>> - In the future, we are going to have a number of cases like this where we accept accesses and don't log for every unimp access (to clean up log output). If we choose to keep those patches private and don't upstream them it's going to increase the number of private patches we keep, making future rebasing more difficult.
>> - I'd prefer to upstream more patches, and focus on keeping only the patches we need to private (for confidentiality or other reasons). To make future rebasing easier.
> 
> I agree with Glenn that we shouldn't mask these warnings for everyone.
> 
> Since a warning saying a feature is unimplemented is better than
> silently not doing anything without any warnings.
> 
> Maybe the excessive warnings should only be masked for PowerMV
> development work, rather than upstreaming, or we can always upstream
> once those are implemented.
> 
> - Aditya G
> 

Ok. Would you like me to pull out this patch from the series and send out v2 containing only the approved patches?

Thanks,
Caleb

Re: [PATCH 1/4] ppc/pnv: Suppress some "pnv_chiptod unimplemented register" messages

[Aditya Gupta]

On 26/01/20 08:31AM, Caleb Schlossin wrote:
> 
> 
> On 1/19/26 4:18 AM, Aditya Gupta wrote:
> > On 26/01/06 11:07AM, Caleb Schlossin wrote:
> >>
> >>
> >> On 1/6/26 10:49 AM, Miles Glenn wrote:
> >>> Hi Caleb.  I wonder if it makes sense to upstream this commit since I
> >>> suspect that most upstream users will not have the "unimp" log messages
> >>> enabled unless they are debugging a problem and in that case, we would
> >>> be erroneously masking these unimplemented registers from the logged
> >>> output.
> >>>
> >>> Thanks,
> >>>
> >>> Glenn
> >>
> >> I understand your point. Here are my thoughts:
> >> - Cleaning up these logs for valid accesses (PowerVM bringup and development) reduces the overall log output and helps find real errors
> >> - In the future, there may be a customer that wants to run PowerVM with upstream QEMU. The more we upstream, the easier that will be.
> >> - In the future, we are going to have a number of cases like this where we accept accesses and don't log for every unimp access (to clean up log output). If we choose to keep those patches private and don't upstream them it's going to increase the number of private patches we keep, making future rebasing more difficult.
> >> - I'd prefer to upstream more patches, and focus on keeping only the patches we need to private (for confidentiality or other reasons). To make future rebasing easier.
> > 
> > I agree with Glenn that we shouldn't mask these warnings for everyone.
> > 
> > Since a warning saying a feature is unimplemented is better than
> > silently not doing anything without any warnings.
> > 
> > Maybe the excessive warnings should only be masked for PowerMV
> > development work, rather than upstreaming, or we can always upstream
> > once those are implemented.
> > 
> > - Aditya G
> > 
> 
> Ok. Would you like me to pull out this patch from the series and send out v2 containing only the approved patches?

Yes Caleb, thanks for understanding.

- Aditya G

> 
> Thanks,
> Caleb
> 

[PATCH 2/4] ppc/pnv: Support for SECURITY_SWITCH XSCOM register access

[Caleb Schlossin]

Power Hypervisor code requires access to the SECURITY_SWITCH
XSCOM register at MMIO address 0x80028 (scom address 0x10005).
Adding basic read support for now so that is doesn't cause
error messages to be posted.

Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
 hw/ppc/pnv_xscom.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index fbfec829d5..308430def7 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -61,6 +61,8 @@ static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
 static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
 {
     switch (pcba) {
+    case 0x10005:       /* SECURITY SWITCH */
+        return 0;
     case 0xf000f:
         return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
     case 0x18002:       /* ECID2 */
-- 
2.47.3

Re: [PATCH 2/4] ppc/pnv: Support for SECURITY_SWITCH XSCOM register access

[Chalapathi V]

[-- Attachment #1: Type: text/plain, Size: 1051 bytes --]

Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com> 
<mailto:milesg@linux.ibm.com>


On 19/12/25 1:33 am, Caleb Schlossin wrote:
> Power Hypervisor code requires access to the SECURITY_SWITCH
> XSCOM register at MMIO address 0x80028 (scom address 0x10005).
> Adding basic read support for now so that is doesn't cause
> error messages to be posted.
>
> Signed-off-by: Glenn Miles<milesg@linux.ibm.com>
> Signed-off-by: Caleb Schlossin<calebs@linux.ibm.com>
> ---
>   hw/ppc/pnv_xscom.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
> index fbfec829d5..308430def7 100644
> --- a/hw/ppc/pnv_xscom.c
> +++ b/hw/ppc/pnv_xscom.c
> @@ -61,6 +61,8 @@ static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
>   static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
>   {
>       switch (pcba) {
> +    case 0x10005:       /* SECURITY SWITCH */
> +        return 0;
>       case 0xf000f:
>           return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
>       case 0x18002:       /* ECID2 */

[-- Attachment #2: Type: text/html, Size: 1731 bytes --]

Re: [PATCH 2/4] ppc/pnv: Support for SECURITY_SWITCH XSCOM register access

[Miles Glenn]

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>

Thanks,

Glenn

On Thu, 2025-12-18 at 14:03 -0600, Caleb Schlossin wrote:
> Power Hypervisor code requires access to the SECURITY_SWITCH
> XSCOM register at MMIO address 0x80028 (scom address 0x10005).
> Adding basic read support for now so that is doesn't cause
> error messages to be posted.
> 
> Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
>  hw/ppc/pnv_xscom.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
> index fbfec829d5..308430def7 100644
> --- a/hw/ppc/pnv_xscom.c
> +++ b/hw/ppc/pnv_xscom.c
> @@ -61,6 +61,8 @@ static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
>  static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
>  {
>      switch (pcba) {
> +    case 0x10005:       /* SECURITY SWITCH */
> +        return 0;
>      case 0xf000f:
>          return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
>      case 0x18002:       /* ECID2 */

Re: [PATCH 2/4] ppc/pnv: Support for SECURITY_SWITCH XSCOM register access

[Aditya Gupta]

On 25/12/18 02:03PM, Caleb Schlossin wrote:
> Power Hypervisor code requires access to the SECURITY_SWITCH
> XSCOM register at MMIO address 0x80028 (scom address 0x10005).
> Adding basic read support for now so that is doesn't cause
> error messages to be posted.
> 
> Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
>  hw/ppc/pnv_xscom.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
> index fbfec829d5..308430def7 100644
> --- a/hw/ppc/pnv_xscom.c
> +++ b/hw/ppc/pnv_xscom.c
> @@ -61,6 +61,8 @@ static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
>  static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
>  {
>      switch (pcba) {
> +    case 0x10005:       /* SECURITY SWITCH */
> +        return 0;

Looks okay to me, and returning 0 here makes sense.

Reviewed-by: Aditya Gupta <adityag@linux.ibm.com>

Thanks,
- Aditya G

>      case 0xf000f:
>          return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
>      case 0x18002:       /* ECID2 */
> -- 
> 2.47.3
> 

[PATCH 3/4] ppc/pnv: Add unimplemented quad and core regs

[Caleb Schlossin]

This commit adds the read/write functionality for few core and
quad registers.

Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
 hw/ppc/pnv_core.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index fb2dfc7ba2..84a2fa6364 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -184,10 +184,18 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
  * POWER10 core controls
  */
 
+#define PNV10_XSCOM_EC_IMA_EVENT_MASK       0x400
 #define PNV10_XSCOM_EC_CORE_THREAD_STATE    0x412
 #define PNV10_XSCOM_EC_CORE_THREAD_INFO     0x413
+#define PNV10_XSCOM_EC_CORE_FIRMASK         0x443
+#define PNV10_XSCOM_EC_CORE_FIRMASK_AND     0x444
+#define PNV10_XSCOM_EC_CORE_FIRMASK_OR      0x445
 #define PNV10_XSCOM_EC_CORE_DIRECT_CONTROLS 0x449
 #define PNV10_XSCOM_EC_CORE_RAS_STATUS      0x454
+#define PNV10_XSCOM_EC_SPATTN_OR            0x497
+#define PNV10_XSCOM_EC_SPATTN_AND           0x498
+#define PNV10_XSCOM_EC_SPATTN               0x499
+#define PNV10_XSCOM_EC_SPATTN_MASK          0x49A
 
 static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
                                            unsigned int width)
@@ -223,6 +231,19 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
             }
         }
         break;
+    case PNV10_XSCOM_EC_IMA_EVENT_MASK:
+    case PNV10_XSCOM_EC_CORE_FIRMASK:
+        return 0;
+    case PNV10_XSCOM_EC_CORE_FIRMASK_OR:
+    case PNV10_XSCOM_EC_CORE_FIRMASK_AND:
+    case PNV10_XSCOM_EC_SPATTN_OR:
+    case PNV10_XSCOM_EC_SPATTN_AND:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
+                              "xscom read at 0x%08x\n", __func__, offset);
+        break;
+    case PNV10_XSCOM_EC_SPATTN:
+    case PNV10_XSCOM_EC_SPATTN_MASK:
+        return 0;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
                       offset);
@@ -283,6 +304,15 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
         }
         break;
 
+    case PNV10_XSCOM_EC_IMA_EVENT_MASK:
+    case PNV10_XSCOM_EC_CORE_FIRMASK:
+    case PNV10_XSCOM_EC_CORE_FIRMASK_OR:
+    case PNV10_XSCOM_EC_CORE_FIRMASK_AND:
+    case PNV10_XSCOM_EC_SPATTN_OR:
+    case PNV10_XSCOM_EC_SPATTN_AND:
+    case PNV10_XSCOM_EC_SPATTN:
+    case PNV10_XSCOM_EC_SPATTN_MASK:
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
                       offset);
@@ -568,6 +598,23 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
  * POWER10 Quads
  */
 
+#define P10_XSCOM_EQ3_MODE_REG1         0x1160a
+#define P10_XSCOM_EQ3_NCU_SPEC_BAR_REG  0x11650
+#define P10_XSCOM_EQ3_HTM_MODE          0x11680
+#define P10_XSCOM_EQ3_HTM_IMA_PDBAR     0x1168b
+#define P10_XSCOM_EQ2_MODE_REG1         0x1260a
+#define P10_XSCOM_EQ2_NCU_SPEC_BAR_REG  0x12650
+#define P10_XSCOM_EQ2_HTM_MODE          0x12680
+#define P10_XSCOM_EQ2_HTM_IMA_PDBAR     0x1268b
+#define P10_XSCOM_EQ1_MODE_REG1         0x1460a
+#define P10_XSCOM_EQ1_NCU_SPEC_BAR_REG  0x14650
+#define P10_XSCOM_EQ1_HTM_MODE          0x14680
+#define P10_XSCOM_EQ1_HTM_IMA_PDBAR     0x1468b
+#define P10_XSCOM_EQ0_MODE_REG1         0x1860a
+#define P10_XSCOM_EQ0_NCU_SPEC_BAR_REG  0x18650
+#define P10_XSCOM_EQ0_HTM_MODE          0x18680
+#define P10_XSCOM_EQ0_HTM_IMA_PDBAR     0x1868b
+
 static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
                                             unsigned int width)
 {
@@ -575,6 +622,23 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
     uint64_t val = -1;
 
     switch (offset) {
+    case P10_XSCOM_EQ0_MODE_REG1:
+    case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:
+    case P10_XSCOM_EQ0_HTM_MODE:
+    case P10_XSCOM_EQ0_HTM_IMA_PDBAR:
+    case P10_XSCOM_EQ1_MODE_REG1:
+    case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:
+    case P10_XSCOM_EQ1_HTM_MODE:
+    case P10_XSCOM_EQ1_HTM_IMA_PDBAR:
+    case P10_XSCOM_EQ2_MODE_REG1:
+    case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:
+    case P10_XSCOM_EQ2_HTM_MODE:
+    case P10_XSCOM_EQ2_HTM_IMA_PDBAR:
+    case P10_XSCOM_EQ3_MODE_REG1:
+    case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:
+    case P10_XSCOM_EQ3_HTM_MODE:
+    case P10_XSCOM_EQ3_HTM_IMA_PDBAR:
+        return 0;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
                       offset);
@@ -589,6 +653,23 @@ static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,
     uint32_t offset = addr >> 3;
 
     switch (offset) {
+    case P10_XSCOM_EQ0_MODE_REG1:
+    case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:
+    case P10_XSCOM_EQ0_HTM_MODE:
+    case P10_XSCOM_EQ0_HTM_IMA_PDBAR:
+    case P10_XSCOM_EQ1_MODE_REG1:
+    case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:
+    case P10_XSCOM_EQ1_HTM_MODE:
+    case P10_XSCOM_EQ1_HTM_IMA_PDBAR:
+    case P10_XSCOM_EQ2_MODE_REG1:
+    case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:
+    case P10_XSCOM_EQ2_HTM_MODE:
+    case P10_XSCOM_EQ2_HTM_IMA_PDBAR:
+    case P10_XSCOM_EQ3_MODE_REG1:
+    case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:
+    case P10_XSCOM_EQ3_HTM_MODE:
+    case P10_XSCOM_EQ3_HTM_IMA_PDBAR:
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
                       offset);
-- 
2.47.3

Re: [PATCH 3/4] ppc/pnv: Add unimplemented quad and core regs

[Chalapathi V]

[-- Attachment #1: Type: text/plain, Size: 5867 bytes --]

Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com 
<mailto:milesg@linux.ibm.com>


On 19/12/25 1:33 am, Caleb Schlossin wrote:
> This commit adds the read/write functionality for few core and
> quad registers.
>
> Signed-off-by: Chalapathi V<chalapathi.v@linux.ibm.com>
> Signed-off-by: Caleb Schlossin<calebs@linux.ibm.com>
> ---
>   hw/ppc/pnv_core.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 81 insertions(+)
>
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index fb2dfc7ba2..84a2fa6364 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -184,10 +184,18 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
>    * POWER10 core controls
>    */
>   
> +#define PNV10_XSCOM_EC_IMA_EVENT_MASK       0x400
>   #define PNV10_XSCOM_EC_CORE_THREAD_STATE    0x412
>   #define PNV10_XSCOM_EC_CORE_THREAD_INFO     0x413
> +#define PNV10_XSCOM_EC_CORE_FIRMASK         0x443
> +#define PNV10_XSCOM_EC_CORE_FIRMASK_AND     0x444
> +#define PNV10_XSCOM_EC_CORE_FIRMASK_OR      0x445
>   #define PNV10_XSCOM_EC_CORE_DIRECT_CONTROLS 0x449
>   #define PNV10_XSCOM_EC_CORE_RAS_STATUS      0x454
> +#define PNV10_XSCOM_EC_SPATTN_OR            0x497
> +#define PNV10_XSCOM_EC_SPATTN_AND           0x498
> +#define PNV10_XSCOM_EC_SPATTN               0x499
> +#define PNV10_XSCOM_EC_SPATTN_MASK          0x49A
>   
>   static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
>                                              unsigned int width)
> @@ -223,6 +231,19 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
>               }
>           }
>           break;
> +    case PNV10_XSCOM_EC_IMA_EVENT_MASK:
> +    case PNV10_XSCOM_EC_CORE_FIRMASK:
> +        return 0;
> +    case PNV10_XSCOM_EC_CORE_FIRMASK_OR:
> +    case PNV10_XSCOM_EC_CORE_FIRMASK_AND:
> +    case PNV10_XSCOM_EC_SPATTN_OR:
> +    case PNV10_XSCOM_EC_SPATTN_AND:
> +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
> +                              "xscom read at 0x%08x\n", __func__, offset);
> +        break;
> +    case PNV10_XSCOM_EC_SPATTN:
> +    case PNV10_XSCOM_EC_SPATTN_MASK:
> +        return 0;
>       default:
>           qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
>                         offset);
> @@ -283,6 +304,15 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
>           }
>           break;
>   
> +    case PNV10_XSCOM_EC_IMA_EVENT_MASK:
> +    case PNV10_XSCOM_EC_CORE_FIRMASK:
> +    case PNV10_XSCOM_EC_CORE_FIRMASK_OR:
> +    case PNV10_XSCOM_EC_CORE_FIRMASK_AND:
> +    case PNV10_XSCOM_EC_SPATTN_OR:
> +    case PNV10_XSCOM_EC_SPATTN_AND:
> +    case PNV10_XSCOM_EC_SPATTN:
> +    case PNV10_XSCOM_EC_SPATTN_MASK:
> +        break;
>       default:
>           qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
>                         offset);
> @@ -568,6 +598,23 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
>    * POWER10 Quads
>    */
>   
> +#define P10_XSCOM_EQ3_MODE_REG1         0x1160a
> +#define P10_XSCOM_EQ3_NCU_SPEC_BAR_REG  0x11650
> +#define P10_XSCOM_EQ3_HTM_MODE          0x11680
> +#define P10_XSCOM_EQ3_HTM_IMA_PDBAR     0x1168b
> +#define P10_XSCOM_EQ2_MODE_REG1         0x1260a
> +#define P10_XSCOM_EQ2_NCU_SPEC_BAR_REG  0x12650
> +#define P10_XSCOM_EQ2_HTM_MODE          0x12680
> +#define P10_XSCOM_EQ2_HTM_IMA_PDBAR     0x1268b
> +#define P10_XSCOM_EQ1_MODE_REG1         0x1460a
> +#define P10_XSCOM_EQ1_NCU_SPEC_BAR_REG  0x14650
> +#define P10_XSCOM_EQ1_HTM_MODE          0x14680
> +#define P10_XSCOM_EQ1_HTM_IMA_PDBAR     0x1468b
> +#define P10_XSCOM_EQ0_MODE_REG1         0x1860a
> +#define P10_XSCOM_EQ0_NCU_SPEC_BAR_REG  0x18650
> +#define P10_XSCOM_EQ0_HTM_MODE          0x18680
> +#define P10_XSCOM_EQ0_HTM_IMA_PDBAR     0x1868b
> +
>   static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
>                                               unsigned int width)
>   {
> @@ -575,6 +622,23 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
>       uint64_t val = -1;
>   
>       switch (offset) {
> +    case P10_XSCOM_EQ0_MODE_REG1:
> +    case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ0_HTM_MODE:
> +    case P10_XSCOM_EQ0_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ1_MODE_REG1:
> +    case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ1_HTM_MODE:
> +    case P10_XSCOM_EQ1_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ2_MODE_REG1:
> +    case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ2_HTM_MODE:
> +    case P10_XSCOM_EQ2_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ3_MODE_REG1:
> +    case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ3_HTM_MODE:
> +    case P10_XSCOM_EQ3_HTM_IMA_PDBAR:
> +        return 0;
>       default:
>           qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
>                         offset);
> @@ -589,6 +653,23 @@ static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,
>       uint32_t offset = addr >> 3;
>   
>       switch (offset) {
> +    case P10_XSCOM_EQ0_MODE_REG1:
> +    case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ0_HTM_MODE:
> +    case P10_XSCOM_EQ0_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ1_MODE_REG1:
> +    case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ1_HTM_MODE:
> +    case P10_XSCOM_EQ1_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ2_MODE_REG1:
> +    case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ2_HTM_MODE:
> +    case P10_XSCOM_EQ2_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ3_MODE_REG1:
> +    case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ3_HTM_MODE:
> +    case P10_XSCOM_EQ3_HTM_IMA_PDBAR:
> +        break;
>       default:
>           qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
>                         offset);

[-- Attachment #2: Type: text/html, Size: 6287 bytes --]

Re: [PATCH 3/4] ppc/pnv: Add unimplemented quad and core regs

[Miles Glenn]

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>

Thanks,

Glenn

On Thu, 2025-12-18 at 14:03 -0600, Caleb Schlossin wrote:
> This commit adds the read/write functionality for few core and
> quad registers.
> 
> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
>  hw/ppc/pnv_core.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 81 insertions(+)
> 
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index fb2dfc7ba2..84a2fa6364 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -184,10 +184,18 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
>   * POWER10 core controls
>   */
>  
> +#define PNV10_XSCOM_EC_IMA_EVENT_MASK       0x400
>  #define PNV10_XSCOM_EC_CORE_THREAD_STATE    0x412
>  #define PNV10_XSCOM_EC_CORE_THREAD_INFO     0x413
> +#define PNV10_XSCOM_EC_CORE_FIRMASK         0x443
> +#define PNV10_XSCOM_EC_CORE_FIRMASK_AND     0x444
> +#define PNV10_XSCOM_EC_CORE_FIRMASK_OR      0x445
>  #define PNV10_XSCOM_EC_CORE_DIRECT_CONTROLS 0x449
>  #define PNV10_XSCOM_EC_CORE_RAS_STATUS      0x454
> +#define PNV10_XSCOM_EC_SPATTN_OR            0x497
> +#define PNV10_XSCOM_EC_SPATTN_AND           0x498
> +#define PNV10_XSCOM_EC_SPATTN               0x499
> +#define PNV10_XSCOM_EC_SPATTN_MASK          0x49A
>  
>  static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
>                                             unsigned int width)
> @@ -223,6 +231,19 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
>              }
>          }
>          break;
> +    case PNV10_XSCOM_EC_IMA_EVENT_MASK:
> +    case PNV10_XSCOM_EC_CORE_FIRMASK:
> +        return 0;
> +    case PNV10_XSCOM_EC_CORE_FIRMASK_OR:
> +    case PNV10_XSCOM_EC_CORE_FIRMASK_AND:
> +    case PNV10_XSCOM_EC_SPATTN_OR:
> +    case PNV10_XSCOM_EC_SPATTN_AND:
> +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
> +                              "xscom read at 0x%08x\n", __func__, offset);
> +        break;
> +    case PNV10_XSCOM_EC_SPATTN:
> +    case PNV10_XSCOM_EC_SPATTN_MASK:
> +        return 0;
>      default:
>          qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
>                        offset);
> @@ -283,6 +304,15 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
>          }
>          break;
>  
> +    case PNV10_XSCOM_EC_IMA_EVENT_MASK:
> +    case PNV10_XSCOM_EC_CORE_FIRMASK:
> +    case PNV10_XSCOM_EC_CORE_FIRMASK_OR:
> +    case PNV10_XSCOM_EC_CORE_FIRMASK_AND:
> +    case PNV10_XSCOM_EC_SPATTN_OR:
> +    case PNV10_XSCOM_EC_SPATTN_AND:
> +    case PNV10_XSCOM_EC_SPATTN:
> +    case PNV10_XSCOM_EC_SPATTN_MASK:
> +        break;
>      default:
>          qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
>                        offset);
> @@ -568,6 +598,23 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
>   * POWER10 Quads
>   */
>  
> +#define P10_XSCOM_EQ3_MODE_REG1         0x1160a
> +#define P10_XSCOM_EQ3_NCU_SPEC_BAR_REG  0x11650
> +#define P10_XSCOM_EQ3_HTM_MODE          0x11680
> +#define P10_XSCOM_EQ3_HTM_IMA_PDBAR     0x1168b
> +#define P10_XSCOM_EQ2_MODE_REG1         0x1260a
> +#define P10_XSCOM_EQ2_NCU_SPEC_BAR_REG  0x12650
> +#define P10_XSCOM_EQ2_HTM_MODE          0x12680
> +#define P10_XSCOM_EQ2_HTM_IMA_PDBAR     0x1268b
> +#define P10_XSCOM_EQ1_MODE_REG1         0x1460a
> +#define P10_XSCOM_EQ1_NCU_SPEC_BAR_REG  0x14650
> +#define P10_XSCOM_EQ1_HTM_MODE          0x14680
> +#define P10_XSCOM_EQ1_HTM_IMA_PDBAR     0x1468b
> +#define P10_XSCOM_EQ0_MODE_REG1         0x1860a
> +#define P10_XSCOM_EQ0_NCU_SPEC_BAR_REG  0x18650
> +#define P10_XSCOM_EQ0_HTM_MODE          0x18680
> +#define P10_XSCOM_EQ0_HTM_IMA_PDBAR     0x1868b
> +
>  static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
>                                              unsigned int width)
>  {
> @@ -575,6 +622,23 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
>      uint64_t val = -1;
>  
>      switch (offset) {
> +    case P10_XSCOM_EQ0_MODE_REG1:
> +    case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ0_HTM_MODE:
> +    case P10_XSCOM_EQ0_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ1_MODE_REG1:
> +    case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ1_HTM_MODE:
> +    case P10_XSCOM_EQ1_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ2_MODE_REG1:
> +    case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ2_HTM_MODE:
> +    case P10_XSCOM_EQ2_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ3_MODE_REG1:
> +    case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ3_HTM_MODE:
> +    case P10_XSCOM_EQ3_HTM_IMA_PDBAR:
> +        return 0;
>      default:
>          qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
>                        offset);
> @@ -589,6 +653,23 @@ static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,
>      uint32_t offset = addr >> 3;
>  
>      switch (offset) {
> +    case P10_XSCOM_EQ0_MODE_REG1:
> +    case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ0_HTM_MODE:
> +    case P10_XSCOM_EQ0_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ1_MODE_REG1:
> +    case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ1_HTM_MODE:
> +    case P10_XSCOM_EQ1_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ2_MODE_REG1:
> +    case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ2_HTM_MODE:
> +    case P10_XSCOM_EQ2_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ3_MODE_REG1:
> +    case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ3_HTM_MODE:
> +    case P10_XSCOM_EQ3_HTM_IMA_PDBAR:
> +        break;
>      default:
>          qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
>                        offset);

Re: [PATCH 3/4] ppc/pnv: Add unimplemented quad and core regs

[Aditya Gupta]

On 25/12/18 02:03PM, Caleb Schlossin wrote:
> This commit adds the read/write functionality for few core and
> quad registers.
> 
> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
>  hw/ppc/pnv_core.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 81 insertions(+)
> 
> > <...snip...>
> 
> @@ -589,6 +653,23 @@ static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,
>      uint32_t offset = addr >> 3;
>  
>      switch (offset) {
> +    case P10_XSCOM_EQ0_MODE_REG1:
> +    case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ0_HTM_MODE:
> +    case P10_XSCOM_EQ0_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ1_MODE_REG1:
> +    case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ1_HTM_MODE:
> +    case P10_XSCOM_EQ1_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ2_MODE_REG1:
> +    case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ2_HTM_MODE:
> +    case P10_XSCOM_EQ2_HTM_IMA_PDBAR:
> +    case P10_XSCOM_EQ3_MODE_REG1:
> +    case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:
> +    case P10_XSCOM_EQ3_HTM_MODE:
> +    case P10_XSCOM_EQ3_HTM_IMA_PDBAR:
> +        break;
>      default:
>          qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
>                        offset);

Similar to patch 1, we are masking a warning. Though I don't have strong
opposition here, as many of these regs will likely never be implemented
in qemu, like the fir and those eq xscoms etc.
Hence, looks good to me:

Reviewed-by: Aditya Gupta <adityag@linux.ibm.com>

Thanks,
- Aditya G

[PATCH 4/4] ppc/pnv: Add OCC FLAG registers

[Caleb Schlossin]

OCCFLG are scratch registers that can be shared with OCC firmware.
Log reads and writes to the registers as a reminder when we run
into more OCC code.

Add RW, WO_CLEAR and WO_OR SCOM Type enums in pnv_occ.c

Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
 hw/ppc/pnv_occ.c         | 55 +++++++++++++++++++++++++++++++++++++---
 include/hw/ppc/pnv_occ.h |  4 +++
 2 files changed, 56 insertions(+), 3 deletions(-)

diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 24b789c191..e605ae0fbc 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -195,6 +195,49 @@ static const TypeInfo pnv_occ_power8_type_info = {
 #define P9_OCB_OCI_OCCMISC_CLEAR        0x6081
 #define P9_OCB_OCI_OCCMISC_OR           0x6082
 
+/* OCC scratch registers for flag setting */
+#define P9_OCCFLG0                      0x60ac
+#define P9_OCCFLG7_OR                   0x60c3
+
+enum ScomType {
+    SCOM_TYPE_RW          = 0,
+    SCOM_TYPE_WO_CLEAR    = 1,
+    SCOM_TYPE_WO_OR       = 2,
+};
+
+static void rw_occ_flag_regs(PnvOCC *occ, uint32_t offset, bool read,
+        uint64_t *val)
+{
+    int flag_num;
+    int flag_type;
+
+    /*
+     * Each OCCFLG register has SCOM0 - RW, SCOM1 - WO_CLEAR, SCOM2 - WO_OR
+     * hence devide by 3 to get flag index and mod 3 to get SCOM type.
+     */
+    flag_num = (offset - P9_OCCFLG0) / 3;
+    flag_type = (offset - P9_OCCFLG0) % 3;
+
+    if (read) {
+        if (flag_type) {
+            qemu_log_mask(LOG_GUEST_ERROR, "OCC: Write only register: Ox%"
+                      PRIx32 "\n", offset);
+            return;
+        }
+        *val = occ->occflags[flag_num];
+    } else {
+        switch (flag_type) {
+        case SCOM_TYPE_RW:
+            occ->occflags[flag_num] = *val;
+            break;
+        case SCOM_TYPE_WO_CLEAR:
+            occ->occflags[flag_num] &= ~(*val);
+            break;
+        case SCOM_TYPE_WO_OR:
+            occ->occflags[flag_num] |= *val;
+        }
+    }
+}
 
 static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
                                           unsigned size)
@@ -207,8 +250,11 @@ static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
     case P9_OCB_OCI_OCCMISC:
         val = occ->occmisc;
         break;
+    case P9_OCCFLG0 ... P9_OCCFLG7_OR:
+        rw_occ_flag_regs(occ, offset, 1, &val);
+        break;
     default:
-        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
+        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register read: Ox%"
                       HWADDR_PRIx "\n", addr >> 3);
     }
     return val;
@@ -229,9 +275,12 @@ static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,
         break;
     case P9_OCB_OCI_OCCMISC:
         pnv_occ_set_misc(occ, val);
-       break;
+        break;
+    case P9_OCCFLG0 ... P9_OCCFLG7_OR:
+        rw_occ_flag_regs(occ, offset, 0, &val);
+        break;
     default:
-        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
+        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register write: Ox%"
                       HWADDR_PRIx "\n", addr >> 3);
     }
 }
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index 013ea2e53e..8c9f1416eb 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -47,6 +47,10 @@ struct PnvOCC {
     /* OCC Misc interrupt */
     uint64_t occmisc;
 
+    /* OCC Flags */
+#define NR_FLAG_REGS 8
+    uint32_t occflags[NR_FLAG_REGS];
+
     qemu_irq psi_irq;
 
     /* OCCs operate on regions of HOMER memory */
-- 
2.47.3

Re: [PATCH 4/4] ppc/pnv: Add OCC FLAG registers

[Chalapathi V]

[-- Attachment #1: Type: text/plain, Size: 3961 bytes --]

Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com 
<mailto:milesg@linux.ibm.com>


On 19/12/25 1:33 am, Caleb Schlossin wrote:
> OCCFLG are scratch registers that can be shared with OCC firmware.
> Log reads and writes to the registers as a reminder when we run
> into more OCC code.
>
> Add RW, WO_CLEAR and WO_OR SCOM Type enums in pnv_occ.c
>
> Signed-off-by: Chalapathi V<chalapathi.v@linux.ibm.com>
> Signed-off-by: Caleb Schlossin<calebs@linux.ibm.com>
> ---
>   hw/ppc/pnv_occ.c         | 55 +++++++++++++++++++++++++++++++++++++---
>   include/hw/ppc/pnv_occ.h |  4 +++
>   2 files changed, 56 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
> index 24b789c191..e605ae0fbc 100644
> --- a/hw/ppc/pnv_occ.c
> +++ b/hw/ppc/pnv_occ.c
> @@ -195,6 +195,49 @@ static const TypeInfo pnv_occ_power8_type_info = {
>   #define P9_OCB_OCI_OCCMISC_CLEAR        0x6081
>   #define P9_OCB_OCI_OCCMISC_OR           0x6082
>   
> +/* OCC scratch registers for flag setting */
> +#define P9_OCCFLG0                      0x60ac
> +#define P9_OCCFLG7_OR                   0x60c3
> +
> +enum ScomType {
> +    SCOM_TYPE_RW          = 0,
> +    SCOM_TYPE_WO_CLEAR    = 1,
> +    SCOM_TYPE_WO_OR       = 2,
> +};
> +
> +static void rw_occ_flag_regs(PnvOCC *occ, uint32_t offset, bool read,
> +        uint64_t *val)
> +{
> +    int flag_num;
> +    int flag_type;
> +
> +    /*
> +     * Each OCCFLG register has SCOM0 - RW, SCOM1 - WO_CLEAR, SCOM2 - WO_OR
> +     * hence devide by 3 to get flag index and mod 3 to get SCOM type.
> +     */
> +    flag_num = (offset - P9_OCCFLG0) / 3;
> +    flag_type = (offset - P9_OCCFLG0) % 3;
> +
> +    if (read) {
> +        if (flag_type) {
> +            qemu_log_mask(LOG_GUEST_ERROR, "OCC: Write only register: Ox%"
> +                      PRIx32 "\n", offset);
> +            return;
> +        }
> +        *val = occ->occflags[flag_num];
> +    } else {
> +        switch (flag_type) {
> +        case SCOM_TYPE_RW:
> +            occ->occflags[flag_num] = *val;
> +            break;
> +        case SCOM_TYPE_WO_CLEAR:
> +            occ->occflags[flag_num] &= ~(*val);
> +            break;
> +        case SCOM_TYPE_WO_OR:
> +            occ->occflags[flag_num] |= *val;
> +        }
> +    }
> +}
>   
>   static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
>                                             unsigned size)
> @@ -207,8 +250,11 @@ static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
>       case P9_OCB_OCI_OCCMISC:
>           val = occ->occmisc;
>           break;
> +    case P9_OCCFLG0 ... P9_OCCFLG7_OR:
> +        rw_occ_flag_regs(occ, offset, 1, &val);
> +        break;
>       default:
> -        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
> +        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register read: Ox%"
>                         HWADDR_PRIx "\n", addr >> 3);
>       }
>       return val;
> @@ -229,9 +275,12 @@ static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,
>           break;
>       case P9_OCB_OCI_OCCMISC:
>           pnv_occ_set_misc(occ, val);
> -       break;
> +        break;
> +    case P9_OCCFLG0 ... P9_OCCFLG7_OR:
> +        rw_occ_flag_regs(occ, offset, 0, &val);
> +        break;
>       default:
> -        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
> +        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register write: Ox%"
>                         HWADDR_PRIx "\n", addr >> 3);
>       }
>   }
> diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
> index 013ea2e53e..8c9f1416eb 100644
> --- a/include/hw/ppc/pnv_occ.h
> +++ b/include/hw/ppc/pnv_occ.h
> @@ -47,6 +47,10 @@ struct PnvOCC {
>       /* OCC Misc interrupt */
>       uint64_t occmisc;
>   
> +    /* OCC Flags */
> +#define NR_FLAG_REGS 8
> +    uint32_t occflags[NR_FLAG_REGS];
> +
>       qemu_irq psi_irq;
>   
>       /* OCCs operate on regions of HOMER memory */

[-- Attachment #2: Type: text/html, Size: 4488 bytes --]

Re: [PATCH 4/4] ppc/pnv: Add OCC FLAG registers

[Miles Glenn]

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>

Thanks,

Glenn

On Thu, 2025-12-18 at 14:03 -0600, Caleb Schlossin wrote:
> OCCFLG are scratch registers that can be shared with OCC firmware.
> Log reads and writes to the registers as a reminder when we run
> into more OCC code.
> 
> Add RW, WO_CLEAR and WO_OR SCOM Type enums in pnv_occ.c
> 
> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
>  hw/ppc/pnv_occ.c         | 55 +++++++++++++++++++++++++++++++++++++---
>  include/hw/ppc/pnv_occ.h |  4 +++
>  2 files changed, 56 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
> index 24b789c191..e605ae0fbc 100644
> --- a/hw/ppc/pnv_occ.c
> +++ b/hw/ppc/pnv_occ.c
> @@ -195,6 +195,49 @@ static const TypeInfo pnv_occ_power8_type_info = {
>  #define P9_OCB_OCI_OCCMISC_CLEAR        0x6081
>  #define P9_OCB_OCI_OCCMISC_OR           0x6082
>  
> +/* OCC scratch registers for flag setting */
> +#define P9_OCCFLG0                      0x60ac
> +#define P9_OCCFLG7_OR                   0x60c3
> +
> +enum ScomType {
> +    SCOM_TYPE_RW          = 0,
> +    SCOM_TYPE_WO_CLEAR    = 1,
> +    SCOM_TYPE_WO_OR       = 2,
> +};
> +
> +static void rw_occ_flag_regs(PnvOCC *occ, uint32_t offset, bool read,
> +        uint64_t *val)
> +{
> +    int flag_num;
> +    int flag_type;
> +
> +    /*
> +     * Each OCCFLG register has SCOM0 - RW, SCOM1 - WO_CLEAR, SCOM2 - WO_OR
> +     * hence devide by 3 to get flag index and mod 3 to get SCOM type.
> +     */
> +    flag_num = (offset - P9_OCCFLG0) / 3;
> +    flag_type = (offset - P9_OCCFLG0) % 3;
> +
> +    if (read) {
> +        if (flag_type) {
> +            qemu_log_mask(LOG_GUEST_ERROR, "OCC: Write only register: Ox%"
> +                      PRIx32 "\n", offset);
> +            return;
> +        }
> +        *val = occ->occflags[flag_num];
> +    } else {
> +        switch (flag_type) {
> +        case SCOM_TYPE_RW:
> +            occ->occflags[flag_num] = *val;
> +            break;
> +        case SCOM_TYPE_WO_CLEAR:
> +            occ->occflags[flag_num] &= ~(*val);
> +            break;
> +        case SCOM_TYPE_WO_OR:
> +            occ->occflags[flag_num] |= *val;
> +        }
> +    }
> +}
>  
>  static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
>                                            unsigned size)
> @@ -207,8 +250,11 @@ static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
>      case P9_OCB_OCI_OCCMISC:
>          val = occ->occmisc;
>          break;
> +    case P9_OCCFLG0 ... P9_OCCFLG7_OR:
> +        rw_occ_flag_regs(occ, offset, 1, &val);
> +        break;
>      default:
> -        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
> +        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register read: Ox%"
>                        HWADDR_PRIx "\n", addr >> 3);
>      }
>      return val;
> @@ -229,9 +275,12 @@ static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,
>          break;
>      case P9_OCB_OCI_OCCMISC:
>          pnv_occ_set_misc(occ, val);
> -       break;
> +        break;
> +    case P9_OCCFLG0 ... P9_OCCFLG7_OR:
> +        rw_occ_flag_regs(occ, offset, 0, &val);
> +        break;
>      default:
> -        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
> +        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register write: Ox%"
>                        HWADDR_PRIx "\n", addr >> 3);
>      }
>  }
> diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
> index 013ea2e53e..8c9f1416eb 100644
> --- a/include/hw/ppc/pnv_occ.h
> +++ b/include/hw/ppc/pnv_occ.h
> @@ -47,6 +47,10 @@ struct PnvOCC {
>      /* OCC Misc interrupt */
>      uint64_t occmisc;
>  
> +    /* OCC Flags */
> +#define NR_FLAG_REGS 8
> +    uint32_t occflags[NR_FLAG_REGS];
> +
>      qemu_irq psi_irq;
>  
>      /* OCCs operate on regions of HOMER memory */

Re: [PATCH 4/4] ppc/pnv: Add OCC FLAG registers

[Aditya Gupta]

On 25/12/18 02:03PM, Caleb Schlossin wrote:
> OCCFLG are scratch registers that can be shared with OCC firmware.
> Log reads and writes to the registers as a reminder when we run
> into more OCC code.
> 
> Add RW, WO_CLEAR and WO_OR SCOM Type enums in pnv_occ.c
> 
> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
>  hw/ppc/pnv_occ.c         | 55 +++++++++++++++++++++++++++++++++++++---
>  include/hw/ppc/pnv_occ.h |  4 +++
>  2 files changed, 56 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
> index 24b789c191..e605ae0fbc 100644
> --- a/hw/ppc/pnv_occ.c
> +++ b/hw/ppc/pnv_occ.c
> @@ -195,6 +195,49 @@ static const TypeInfo pnv_occ_power8_type_info = {
>  #define P9_OCB_OCI_OCCMISC_CLEAR        0x6081
>  #define P9_OCB_OCI_OCCMISC_OR           0x6082
>  
> +/* OCC scratch registers for flag setting */
> +#define P9_OCCFLG0                      0x60ac
> +#define P9_OCCFLG7_OR                   0x60c3
> +
> +enum ScomType {
> +    SCOM_TYPE_RW          = 0,
> +    SCOM_TYPE_WO_CLEAR    = 1,
> +    SCOM_TYPE_WO_OR       = 2,
> +};
> +
> +static void rw_occ_flag_regs(PnvOCC *occ, uint32_t offset, bool read,
> +        uint64_t *val)
> +{
> +    int flag_num;
> +    int flag_type;
> +
> +    /*
> +     * Each OCCFLG register has SCOM0 - RW, SCOM1 - WO_CLEAR, SCOM2 - WO_OR
> +     * hence devide by 3 to get flag index and mod 3 to get SCOM type.

nitpick: s/devide/divide

> +     */
> +    flag_num = (offset - P9_OCCFLG0) / 3;
> +    flag_type = (offset - P9_OCCFLG0) % 3;

flag_num can be negative if offset is invalid, but since the function
is static, the current usage ensure that never happens. So, it's okay
with me.

Reviewed-by: Aditya Gupta <adityag@linux.ibm.com>

Thanks,
- Aditya G