* [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API
@ 2025-12-24 16:20 Philippe Mathieu-Daudé
2025-12-24 16:20 ` [PATCH 1/8] hw/s390x: " Philippe Mathieu-Daudé
` (9 more replies)
0 siblings, 10 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-12-24 16:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier,
David Hildenbrand, Thomas Huth, Ilya Leoshkevich,
Manos Pitsidianakis, Halil Pasic, Richard Henderson,
Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck,
Anton Johansson, Michael S. Tsirkin, Philippe Mathieu-Daudé
S390x is big-endian. Use the explicit 'big'
endianness instead of the 'native' one.
Forbid further uses of legacy APIs.
tag: https://gitlab.com/philmd/qemu/-/tags/endian_s390x-v1
CI: https://gitlab.com/philmd/qemu/-/pipelines/2231223066
Philippe Mathieu-Daudé (8):
hw/s390x: Use explicit big-endian LD/ST API
target/s390x: Use explicit big-endian LD/ST API
target/s390x: Replace gdb_get_regl() -> gdb_get_reg64()
target/s390x: Replace MO_TE -> MO_BE
target/s390x: Inline cpu_ld{uw,l}_code() calls in EX opcode helper
target/s390x: Use big-endian variant of cpu_ld/st_data*()
target/s390x: Inline translator_lduw() and translator_ldl()
configs/targets: Forbid S390x to use legacy native endianness APIs
configs/targets/s390x-linux-user.mak | 1 +
configs/targets/s390x-softmmu.mak | 1 +
target/s390x/tcg/insn-data.h.inc | 54 +++++-----
hw/s390x/css.c | 24 ++---
hw/s390x/s390-pci-bus.c | 4 +-
hw/s390x/virtio-ccw.c | 24 ++---
target/s390x/cpu-system.c | 2 +-
target/s390x/gdbstub.c | 26 ++---
target/s390x/kvm/kvm.c | 8 +-
target/s390x/mmu_helper.c | 3 +-
target/s390x/tcg/excp_helper.c | 16 +--
target/s390x/tcg/mem_helper.c | 71 +++++++------
target/s390x/tcg/translate.c | 144 +++++++++++++--------------
target/s390x/tcg/vec_helper.c | 8 +-
target/s390x/tcg/translate_vx.c.inc | 38 +++----
15 files changed, 215 insertions(+), 209 deletions(-)
--
2.52.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 1/8] hw/s390x: Use explicit big-endian LD/ST API 2025-12-24 16:20 [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Philippe Mathieu-Daudé @ 2025-12-24 16:20 ` Philippe Mathieu-Daudé 2025-12-24 19:55 ` Halil Pasic 2025-12-29 11:27 ` Manos Pitsidianakis 2025-12-24 16:20 ` [PATCH 2/8] target/s390x: " Philippe Mathieu-Daudé ` (8 subsequent siblings) 9 siblings, 2 replies; 23+ messages in thread From: Philippe Mathieu-Daudé @ 2025-12-24 16:20 UTC (permalink / raw) To: qemu-devel Cc: qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin, Philippe Mathieu-Daudé The S390x architecture uses big endianness. Directly use the big-endian LD/ST API. Mechanical change running: $ for a in uw w l q; do \ sed -i -e "s/ld${a}_p(/ld${a}_be_p(/" \ $(git grep -wlE '(ld|st)u?[wlq]_p' hw/s390x/); done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/s390x/css.c | 24 +++++++++++------------- hw/s390x/s390-pci-bus.c | 4 ++-- hw/s390x/virtio-ccw.c | 24 ++++++++++++------------ 3 files changed, 25 insertions(+), 27 deletions(-) diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 53444f68288..4bc2253c182 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -1582,27 +1582,25 @@ static void css_update_chnmon(SubchDev *sch) /* Format 1, per-subchannel area. */ uint32_t count; - count = address_space_ldl(&address_space_memory, - sch->curr_status.mba, - MEMTXATTRS_UNSPECIFIED, - NULL); + count = address_space_ldl_be(&address_space_memory, + sch->curr_status.mba, + MEMTXATTRS_UNSPECIFIED, NULL); count++; - address_space_stl(&address_space_memory, sch->curr_status.mba, count, - MEMTXATTRS_UNSPECIFIED, NULL); + address_space_stl_be(&address_space_memory, sch->curr_status.mba, count, + MEMTXATTRS_UNSPECIFIED, NULL); } else { /* Format 0, global area. */ uint32_t offset; uint16_t count; offset = sch->curr_status.pmcw.mbi << 5; - count = address_space_lduw(&address_space_memory, - channel_subsys.chnmon_area + offset, - MEMTXATTRS_UNSPECIFIED, - NULL); + count = address_space_lduw_be(&address_space_memory, + channel_subsys.chnmon_area + offset, + MEMTXATTRS_UNSPECIFIED, NULL); count++; - address_space_stw(&address_space_memory, - channel_subsys.chnmon_area + offset, count, - MEMTXATTRS_UNSPECIFIED, NULL); + address_space_stw_be(&address_space_memory, + channel_subsys.chnmon_area + offset, count, + MEMTXATTRS_UNSPECIFIED, NULL); } } diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 52820894fa1..aeeed82955a 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -461,8 +461,8 @@ static uint64_t table_translate(S390IOTLBEntry *entry, uint64_t to, int8_t ett, uint16_t err = 0; tx = get_table_index(entry->iova, ett); - te = address_space_ldq(&address_space_memory, to + tx * sizeof(uint64_t), - MEMTXATTRS_UNSPECIFIED, NULL); + te = address_space_ldq_be(&address_space_memory, to + tx * sizeof(uint64_t), + MEMTXATTRS_UNSPECIFIED, NULL); if (!te) { err = ERR_EVENT_INVALTE; diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index 4a3ffb84f8f..9dd838c61e4 100644 --- a/hw/s390x/virtio-ccw.c +++ b/hw/s390x/virtio-ccw.c @@ -889,26 +889,26 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector) } } else { assert(vector < NR_CLASSIC_INDICATOR_BITS); - indicators = address_space_ldq(&address_space_memory, - dev->indicators->addr, - MEMTXATTRS_UNSPECIFIED, - NULL); + indicators = address_space_ldq_be(&address_space_memory, + dev->indicators->addr, + MEMTXATTRS_UNSPECIFIED, + NULL); indicators |= 1ULL << vector; - address_space_stq(&address_space_memory, dev->indicators->addr, - indicators, MEMTXATTRS_UNSPECIFIED, NULL); + address_space_stq_be(&address_space_memory, dev->indicators->addr, + indicators, MEMTXATTRS_UNSPECIFIED, NULL); css_conditional_io_interrupt(sch); } } else { if (!dev->indicators2) { return; } - indicators = address_space_ldq(&address_space_memory, - dev->indicators2->addr, - MEMTXATTRS_UNSPECIFIED, - NULL); + indicators = address_space_ldq_be(&address_space_memory, + dev->indicators2->addr, + MEMTXATTRS_UNSPECIFIED, + NULL); indicators |= 1ULL; - address_space_stq(&address_space_memory, dev->indicators2->addr, - indicators, MEMTXATTRS_UNSPECIFIED, NULL); + address_space_stq_be(&address_space_memory, dev->indicators2->addr, + indicators, MEMTXATTRS_UNSPECIFIED, NULL); css_conditional_io_interrupt(sch); } } -- 2.52.0 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 1/8] hw/s390x: Use explicit big-endian LD/ST API 2025-12-24 16:20 ` [PATCH 1/8] hw/s390x: " Philippe Mathieu-Daudé @ 2025-12-24 19:55 ` Halil Pasic 2025-12-29 11:27 ` Manos Pitsidianakis 1 sibling, 0 replies; 23+ messages in thread From: Halil Pasic @ 2025-12-24 19:55 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin, Halil Pasic On Wed, 24 Dec 2025 17:20:28 +0100 Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > The S390x architecture uses big endianness. Directly use > the big-endian LD/ST API. > > Mechanical change running: > > $ for a in uw w l q; do \ > sed -i -e "s/ld${a}_p(/ld${a}_be_p(/" \ > $(git grep -wlE '(ld|st)u?[wlq]_p' hw/s390x/); > done > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Halil Pasic <pasic@linux.ibm.com> ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/8] hw/s390x: Use explicit big-endian LD/ST API 2025-12-24 16:20 ` [PATCH 1/8] hw/s390x: " Philippe Mathieu-Daudé 2025-12-24 19:55 ` Halil Pasic @ 2025-12-29 11:27 ` Manos Pitsidianakis 1 sibling, 0 replies; 23+ messages in thread From: Manos Pitsidianakis @ 2025-12-29 11:27 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On Wed, Dec 24, 2025 at 6:20 PM Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > The S390x architecture uses big endianness. Directly use > the big-endian LD/ST API. > > Mechanical change running: > > $ for a in uw w l q; do \ > sed -i -e "s/ld${a}_p(/ld${a}_be_p(/" \ > $(git grep -wlE '(ld|st)u?[wlq]_p' hw/s390x/); > done > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> > hw/s390x/css.c | 24 +++++++++++------------- > hw/s390x/s390-pci-bus.c | 4 ++-- > hw/s390x/virtio-ccw.c | 24 ++++++++++++------------ > 3 files changed, 25 insertions(+), 27 deletions(-) > > diff --git a/hw/s390x/css.c b/hw/s390x/css.c > index 53444f68288..4bc2253c182 100644 > --- a/hw/s390x/css.c > +++ b/hw/s390x/css.c > @@ -1582,27 +1582,25 @@ static void css_update_chnmon(SubchDev *sch) > /* Format 1, per-subchannel area. */ > uint32_t count; > > - count = address_space_ldl(&address_space_memory, > - sch->curr_status.mba, > - MEMTXATTRS_UNSPECIFIED, > - NULL); > + count = address_space_ldl_be(&address_space_memory, > + sch->curr_status.mba, > + MEMTXATTRS_UNSPECIFIED, NULL); > count++; > - address_space_stl(&address_space_memory, sch->curr_status.mba, count, > - MEMTXATTRS_UNSPECIFIED, NULL); > + address_space_stl_be(&address_space_memory, sch->curr_status.mba, count, > + MEMTXATTRS_UNSPECIFIED, NULL); > } else { > /* Format 0, global area. */ > uint32_t offset; > uint16_t count; > > offset = sch->curr_status.pmcw.mbi << 5; > - count = address_space_lduw(&address_space_memory, > - channel_subsys.chnmon_area + offset, > - MEMTXATTRS_UNSPECIFIED, > - NULL); > + count = address_space_lduw_be(&address_space_memory, > + channel_subsys.chnmon_area + offset, > + MEMTXATTRS_UNSPECIFIED, NULL); > count++; > - address_space_stw(&address_space_memory, > - channel_subsys.chnmon_area + offset, count, > - MEMTXATTRS_UNSPECIFIED, NULL); > + address_space_stw_be(&address_space_memory, > + channel_subsys.chnmon_area + offset, count, > + MEMTXATTRS_UNSPECIFIED, NULL); > } > } > > diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c > index 52820894fa1..aeeed82955a 100644 > --- a/hw/s390x/s390-pci-bus.c > +++ b/hw/s390x/s390-pci-bus.c > @@ -461,8 +461,8 @@ static uint64_t table_translate(S390IOTLBEntry *entry, uint64_t to, int8_t ett, > uint16_t err = 0; > > tx = get_table_index(entry->iova, ett); > - te = address_space_ldq(&address_space_memory, to + tx * sizeof(uint64_t), > - MEMTXATTRS_UNSPECIFIED, NULL); > + te = address_space_ldq_be(&address_space_memory, to + tx * sizeof(uint64_t), > + MEMTXATTRS_UNSPECIFIED, NULL); > > if (!te) { > err = ERR_EVENT_INVALTE; > diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c > index 4a3ffb84f8f..9dd838c61e4 100644 > --- a/hw/s390x/virtio-ccw.c > +++ b/hw/s390x/virtio-ccw.c > @@ -889,26 +889,26 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector) > } > } else { > assert(vector < NR_CLASSIC_INDICATOR_BITS); > - indicators = address_space_ldq(&address_space_memory, > - dev->indicators->addr, > - MEMTXATTRS_UNSPECIFIED, > - NULL); > + indicators = address_space_ldq_be(&address_space_memory, > + dev->indicators->addr, > + MEMTXATTRS_UNSPECIFIED, > + NULL); > indicators |= 1ULL << vector; > - address_space_stq(&address_space_memory, dev->indicators->addr, > - indicators, MEMTXATTRS_UNSPECIFIED, NULL); > + address_space_stq_be(&address_space_memory, dev->indicators->addr, > + indicators, MEMTXATTRS_UNSPECIFIED, NULL); > css_conditional_io_interrupt(sch); > } > } else { > if (!dev->indicators2) { > return; > } > - indicators = address_space_ldq(&address_space_memory, > - dev->indicators2->addr, > - MEMTXATTRS_UNSPECIFIED, > - NULL); > + indicators = address_space_ldq_be(&address_space_memory, > + dev->indicators2->addr, > + MEMTXATTRS_UNSPECIFIED, > + NULL); > indicators |= 1ULL; > - address_space_stq(&address_space_memory, dev->indicators2->addr, > - indicators, MEMTXATTRS_UNSPECIFIED, NULL); > + address_space_stq_be(&address_space_memory, dev->indicators2->addr, > + indicators, MEMTXATTRS_UNSPECIFIED, NULL); > css_conditional_io_interrupt(sch); > } > } > -- > 2.52.0 > ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 2/8] target/s390x: Use explicit big-endian LD/ST API 2025-12-24 16:20 [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Philippe Mathieu-Daudé 2025-12-24 16:20 ` [PATCH 1/8] hw/s390x: " Philippe Mathieu-Daudé @ 2025-12-24 16:20 ` Philippe Mathieu-Daudé 2025-12-29 11:03 ` Manos Pitsidianakis 2025-12-24 16:20 ` [PATCH 3/8] target/s390x: Replace gdb_get_regl() -> gdb_get_reg64() Philippe Mathieu-Daudé ` (7 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Philippe Mathieu-Daudé @ 2025-12-24 16:20 UTC (permalink / raw) To: qemu-devel Cc: qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin, Philippe Mathieu-Daudé The S390x architecture uses big endianness. Directly use the big-endian LD/ST API. Mechanical change running: $ for a in uw w l q; do \ sed -i -e "s/ld${a}_p(/ld${a}_be_p(/" \ $(git grep -wlE '(ld|st)u?[wlq]_p' target/s390x/); done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/s390x/cpu-system.c | 2 +- target/s390x/kvm/kvm.c | 8 ++++---- target/s390x/mmu_helper.c | 3 ++- target/s390x/tcg/excp_helper.c | 16 ++++++++-------- target/s390x/tcg/mem_helper.c | 5 +++-- 5 files changed, 18 insertions(+), 16 deletions(-) diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index f3a9ffb2a27..b0c59b5676e 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -63,7 +63,7 @@ static void s390_cpu_load_normal(CPUState *s) uint64_t spsw; if (!s390_is_pv()) { - spsw = ldq_phys(s->as, 0); + spsw = ldq_be_phys(s->as, 0); cpu->env.psw.mask = spsw & PSW_MASK_SHORT_CTRL; /* * Invert short psw indication, so SIE will report a specification diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 916dac1f14e..89911f356e4 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -1667,10 +1667,10 @@ static int handle_oper_loop(S390CPU *cpu, struct kvm_run *run) CPUState *cs = CPU(cpu); PSW oldpsw, newpsw; - newpsw.mask = ldq_phys(cs->as, cpu->env.psa + - offsetof(LowCore, program_new_psw)); - newpsw.addr = ldq_phys(cs->as, cpu->env.psa + - offsetof(LowCore, program_new_psw) + 8); + newpsw.mask = ldq_be_phys(cs->as, cpu->env.psa + + offsetof(LowCore, program_new_psw)); + newpsw.addr = ldq_be_phys(cs->as, cpu->env.psa + + offsetof(LowCore, program_new_psw) + 8); oldpsw.mask = run->psw_mask; oldpsw.addr = run->psw_addr; /* diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 3b1e75f7833..8c87b30a8e3 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -44,7 +44,8 @@ static void trigger_access_exception(CPUS390XState *env, uint32_t type, } else { CPUState *cs = env_cpu(env); if (type != PGM_ADDRESSING) { - stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec); + stq_be_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), + tec); } trigger_pgm_exception(env, type); } diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index c6641280bc6..868efca3221 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -55,8 +55,8 @@ G_NORETURN void tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc, g_assert(dxc <= 0xff); #if !defined(CONFIG_USER_ONLY) /* Store the DXC into the lowcore */ - stl_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, data_exc_code), dxc); + stl_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, data_exc_code), dxc); #endif /* Store the DXC into the FPC if AFP is enabled */ @@ -72,8 +72,8 @@ G_NORETURN void tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc, g_assert(vxc <= 0xff); #if !defined(CONFIG_USER_ONLY) /* Always store the VXC into the lowcore, without AFP it is undefined */ - stl_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, data_exc_code), vxc); + stl_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, data_exc_code), vxc); #endif /* Always store the VXC into the FPC, without AFP it is undefined */ @@ -651,10 +651,10 @@ void monitor_event(CPUS390XState *env, uint8_t monitor_class, uintptr_t ra) { /* Store the Monitor Code and the Monitor Class Number into the lowcore */ - stq_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, monitor_code), monitor_code); - stw_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, mon_class_num), monitor_class); + stq_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, monitor_code), monitor_code); + stw_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, mon_class_num), monitor_class); tcg_s390_program_interrupt(env, PGM_MONITOR, ra); } diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 24675fc818d..0c7e099df21 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -958,8 +958,9 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, uint32_t r1, uint32_t r2) inject_exc: #if !defined(CONFIG_USER_ONLY) if (exc != PGM_ADDRESSING) { - stq_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, trans_exc_code), - env->tlb_fill_tec); + stq_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, trans_exc_code), + env->tlb_fill_tec); } if (exc == PGM_PAGE_TRANS) { stb_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, op_access_id), -- 2.52.0 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 2/8] target/s390x: Use explicit big-endian LD/ST API 2025-12-24 16:20 ` [PATCH 2/8] target/s390x: " Philippe Mathieu-Daudé @ 2025-12-29 11:03 ` Manos Pitsidianakis 0 siblings, 0 replies; 23+ messages in thread From: Manos Pitsidianakis @ 2025-12-29 11:03 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On Wed, Dec 24, 2025 at 6:20 PM Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > The S390x architecture uses big endianness. Directly use > the big-endian LD/ST API. > > Mechanical change running: > > $ for a in uw w l q; do \ > sed -i -e "s/ld${a}_p(/ld${a}_be_p(/" \ > $(git grep -wlE '(ld|st)u?[wlq]_p' target/s390x/); > done > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> > target/s390x/cpu-system.c | 2 +- > target/s390x/kvm/kvm.c | 8 ++++---- > target/s390x/mmu_helper.c | 3 ++- > target/s390x/tcg/excp_helper.c | 16 ++++++++-------- > target/s390x/tcg/mem_helper.c | 5 +++-- > 5 files changed, 18 insertions(+), 16 deletions(-) > > diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c > index f3a9ffb2a27..b0c59b5676e 100644 > --- a/target/s390x/cpu-system.c > +++ b/target/s390x/cpu-system.c > @@ -63,7 +63,7 @@ static void s390_cpu_load_normal(CPUState *s) > uint64_t spsw; > > if (!s390_is_pv()) { > - spsw = ldq_phys(s->as, 0); > + spsw = ldq_be_phys(s->as, 0); > cpu->env.psw.mask = spsw & PSW_MASK_SHORT_CTRL; > /* > * Invert short psw indication, so SIE will report a specification > diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c > index 916dac1f14e..89911f356e4 100644 > --- a/target/s390x/kvm/kvm.c > +++ b/target/s390x/kvm/kvm.c > @@ -1667,10 +1667,10 @@ static int handle_oper_loop(S390CPU *cpu, struct kvm_run *run) > CPUState *cs = CPU(cpu); > PSW oldpsw, newpsw; > > - newpsw.mask = ldq_phys(cs->as, cpu->env.psa + > - offsetof(LowCore, program_new_psw)); > - newpsw.addr = ldq_phys(cs->as, cpu->env.psa + > - offsetof(LowCore, program_new_psw) + 8); > + newpsw.mask = ldq_be_phys(cs->as, cpu->env.psa + > + offsetof(LowCore, program_new_psw)); > + newpsw.addr = ldq_be_phys(cs->as, cpu->env.psa + > + offsetof(LowCore, program_new_psw) + 8); > oldpsw.mask = run->psw_mask; > oldpsw.addr = run->psw_addr; > /* > diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c > index 3b1e75f7833..8c87b30a8e3 100644 > --- a/target/s390x/mmu_helper.c > +++ b/target/s390x/mmu_helper.c > @@ -44,7 +44,8 @@ static void trigger_access_exception(CPUS390XState *env, uint32_t type, > } else { > CPUState *cs = env_cpu(env); > if (type != PGM_ADDRESSING) { > - stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec); > + stq_be_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), > + tec); > } > trigger_pgm_exception(env, type); > } > diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c > index c6641280bc6..868efca3221 100644 > --- a/target/s390x/tcg/excp_helper.c > +++ b/target/s390x/tcg/excp_helper.c > @@ -55,8 +55,8 @@ G_NORETURN void tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc, > g_assert(dxc <= 0xff); > #if !defined(CONFIG_USER_ONLY) > /* Store the DXC into the lowcore */ > - stl_phys(env_cpu(env)->as, > - env->psa + offsetof(LowCore, data_exc_code), dxc); > + stl_be_phys(env_cpu(env)->as, > + env->psa + offsetof(LowCore, data_exc_code), dxc); > #endif > > /* Store the DXC into the FPC if AFP is enabled */ > @@ -72,8 +72,8 @@ G_NORETURN void tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc, > g_assert(vxc <= 0xff); > #if !defined(CONFIG_USER_ONLY) > /* Always store the VXC into the lowcore, without AFP it is undefined */ > - stl_phys(env_cpu(env)->as, > - env->psa + offsetof(LowCore, data_exc_code), vxc); > + stl_be_phys(env_cpu(env)->as, > + env->psa + offsetof(LowCore, data_exc_code), vxc); > #endif > > /* Always store the VXC into the FPC, without AFP it is undefined */ > @@ -651,10 +651,10 @@ void monitor_event(CPUS390XState *env, > uint8_t monitor_class, uintptr_t ra) > { > /* Store the Monitor Code and the Monitor Class Number into the lowcore */ > - stq_phys(env_cpu(env)->as, > - env->psa + offsetof(LowCore, monitor_code), monitor_code); > - stw_phys(env_cpu(env)->as, > - env->psa + offsetof(LowCore, mon_class_num), monitor_class); > + stq_be_phys(env_cpu(env)->as, > + env->psa + offsetof(LowCore, monitor_code), monitor_code); > + stw_be_phys(env_cpu(env)->as, > + env->psa + offsetof(LowCore, mon_class_num), monitor_class); > > tcg_s390_program_interrupt(env, PGM_MONITOR, ra); > } > diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c > index 24675fc818d..0c7e099df21 100644 > --- a/target/s390x/tcg/mem_helper.c > +++ b/target/s390x/tcg/mem_helper.c > @@ -958,8 +958,9 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, uint32_t r1, uint32_t r2) > inject_exc: > #if !defined(CONFIG_USER_ONLY) > if (exc != PGM_ADDRESSING) { > - stq_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, trans_exc_code), > - env->tlb_fill_tec); > + stq_be_phys(env_cpu(env)->as, > + env->psa + offsetof(LowCore, trans_exc_code), > + env->tlb_fill_tec); > } > if (exc == PGM_PAGE_TRANS) { > stb_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, op_access_id), > -- > 2.52.0 > ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 3/8] target/s390x: Replace gdb_get_regl() -> gdb_get_reg64() 2025-12-24 16:20 [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Philippe Mathieu-Daudé 2025-12-24 16:20 ` [PATCH 1/8] hw/s390x: " Philippe Mathieu-Daudé 2025-12-24 16:20 ` [PATCH 2/8] target/s390x: " Philippe Mathieu-Daudé @ 2025-12-24 16:20 ` Philippe Mathieu-Daudé 2025-12-29 11:03 ` Manos Pitsidianakis 2025-12-24 16:20 ` [PATCH 4/8] target/s390x: Replace MO_TE -> MO_BE Philippe Mathieu-Daudé ` (6 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Philippe Mathieu-Daudé @ 2025-12-24 16:20 UTC (permalink / raw) To: qemu-devel Cc: qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin, Philippe Mathieu-Daudé We only build s390x targets as 64-bit: $ git grep BIT configs/targets/s390x-* configs/targets/s390x-linux-user.mak:6:TARGET_LONG_BITS=64 configs/targets/s390x-softmmu.mak:5:TARGET_LONG_BITS=64 Therefore gdb_get_regl() expands to gdb_get_reg64(). Use the latter which is more explicit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/s390x/gdbstub.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 6bca376f2b6..d1f02ea5ce4 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -34,11 +34,11 @@ int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) switch (n) { case S390_PSWM_REGNUM: - return gdb_get_regl(mem_buf, s390_cpu_get_psw_mask(env)); + return gdb_get_reg64(mem_buf, s390_cpu_get_psw_mask(env)); case S390_PSWA_REGNUM: - return gdb_get_regl(mem_buf, env->psw.addr); + return gdb_get_reg64(mem_buf, env->psw.addr); case S390_R0_REGNUM ... S390_R15_REGNUM: - return gdb_get_regl(mem_buf, env->regs[n - S390_R0_REGNUM]); + return gdb_get_reg64(mem_buf, env->regs[n - S390_R0_REGNUM]); } return 0; } @@ -190,7 +190,7 @@ static int cpu_read_c_reg(CPUState *cs, GByteArray *buf, int n) switch (n) { case S390_C0_REGNUM ... S390_C15_REGNUM: - return gdb_get_regl(buf, env->cregs[n]); + return gdb_get_reg64(buf, env->cregs[n]); default: return 0; } @@ -227,13 +227,13 @@ static int cpu_read_virt_reg(CPUState *cs, GByteArray *mem_buf, int n) switch (n) { case S390_VIRT_CKC_REGNUM: - return gdb_get_regl(mem_buf, env->ckc); + return gdb_get_reg64(mem_buf, env->ckc); case S390_VIRT_CPUTM_REGNUM: - return gdb_get_regl(mem_buf, env->cputm); + return gdb_get_reg64(mem_buf, env->cputm); case S390_VIRT_BEA_REGNUM: - return gdb_get_regl(mem_buf, env->gbea); + return gdb_get_reg64(mem_buf, env->gbea); case S390_VIRT_PREFIX_REGNUM: - return gdb_get_regl(mem_buf, env->psa); + return gdb_get_reg64(mem_buf, env->psa); default: return 0; } @@ -279,13 +279,13 @@ static int cpu_read_virt_kvm_reg(CPUState *cs, GByteArray *mem_buf, int n) switch (n) { case S390_VIRT_KVM_PP_REGNUM: - return gdb_get_regl(mem_buf, env->pp); + return gdb_get_reg64(mem_buf, env->pp); case S390_VIRT_KVM_PFT_REGNUM: - return gdb_get_regl(mem_buf, env->pfault_token); + return gdb_get_reg64(mem_buf, env->pfault_token); case S390_VIRT_KVM_PFS_REGNUM: - return gdb_get_regl(mem_buf, env->pfault_select); + return gdb_get_reg64(mem_buf, env->pfault_select); case S390_VIRT_KVM_PFC_REGNUM: - return gdb_get_regl(mem_buf, env->pfault_compare); + return gdb_get_reg64(mem_buf, env->pfault_compare); default: return 0; } @@ -330,7 +330,7 @@ static int cpu_read_gs_reg(CPUState *cs, GByteArray *buf, int n) S390CPU *cpu = S390_CPU(cs); CPUS390XState *env = &cpu->env; - return gdb_get_regl(buf, env->gscb[n]); + return gdb_get_reg64(buf, env->gscb[n]); } static int cpu_write_gs_reg(CPUState *cs, uint8_t *mem_buf, int n) -- 2.52.0 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 3/8] target/s390x: Replace gdb_get_regl() -> gdb_get_reg64() 2025-12-24 16:20 ` [PATCH 3/8] target/s390x: Replace gdb_get_regl() -> gdb_get_reg64() Philippe Mathieu-Daudé @ 2025-12-29 11:03 ` Manos Pitsidianakis 0 siblings, 0 replies; 23+ messages in thread From: Manos Pitsidianakis @ 2025-12-29 11:03 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On Wed, Dec 24, 2025 at 6:21 PM Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > We only build s390x targets as 64-bit: > > $ git grep BIT configs/targets/s390x-* > configs/targets/s390x-linux-user.mak:6:TARGET_LONG_BITS=64 > configs/targets/s390x-softmmu.mak:5:TARGET_LONG_BITS=64 > > Therefore gdb_get_regl() expands to gdb_get_reg64(). Use > the latter which is more explicit. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> > target/s390x/gdbstub.c | 26 +++++++++++++------------- > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c > index 6bca376f2b6..d1f02ea5ce4 100644 > --- a/target/s390x/gdbstub.c > +++ b/target/s390x/gdbstub.c > @@ -34,11 +34,11 @@ int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) > > switch (n) { > case S390_PSWM_REGNUM: > - return gdb_get_regl(mem_buf, s390_cpu_get_psw_mask(env)); > + return gdb_get_reg64(mem_buf, s390_cpu_get_psw_mask(env)); > case S390_PSWA_REGNUM: > - return gdb_get_regl(mem_buf, env->psw.addr); > + return gdb_get_reg64(mem_buf, env->psw.addr); > case S390_R0_REGNUM ... S390_R15_REGNUM: > - return gdb_get_regl(mem_buf, env->regs[n - S390_R0_REGNUM]); > + return gdb_get_reg64(mem_buf, env->regs[n - S390_R0_REGNUM]); > } > return 0; > } > @@ -190,7 +190,7 @@ static int cpu_read_c_reg(CPUState *cs, GByteArray *buf, int n) > > switch (n) { > case S390_C0_REGNUM ... S390_C15_REGNUM: > - return gdb_get_regl(buf, env->cregs[n]); > + return gdb_get_reg64(buf, env->cregs[n]); > default: > return 0; > } > @@ -227,13 +227,13 @@ static int cpu_read_virt_reg(CPUState *cs, GByteArray *mem_buf, int n) > > switch (n) { > case S390_VIRT_CKC_REGNUM: > - return gdb_get_regl(mem_buf, env->ckc); > + return gdb_get_reg64(mem_buf, env->ckc); > case S390_VIRT_CPUTM_REGNUM: > - return gdb_get_regl(mem_buf, env->cputm); > + return gdb_get_reg64(mem_buf, env->cputm); > case S390_VIRT_BEA_REGNUM: > - return gdb_get_regl(mem_buf, env->gbea); > + return gdb_get_reg64(mem_buf, env->gbea); > case S390_VIRT_PREFIX_REGNUM: > - return gdb_get_regl(mem_buf, env->psa); > + return gdb_get_reg64(mem_buf, env->psa); > default: > return 0; > } > @@ -279,13 +279,13 @@ static int cpu_read_virt_kvm_reg(CPUState *cs, GByteArray *mem_buf, int n) > > switch (n) { > case S390_VIRT_KVM_PP_REGNUM: > - return gdb_get_regl(mem_buf, env->pp); > + return gdb_get_reg64(mem_buf, env->pp); > case S390_VIRT_KVM_PFT_REGNUM: > - return gdb_get_regl(mem_buf, env->pfault_token); > + return gdb_get_reg64(mem_buf, env->pfault_token); > case S390_VIRT_KVM_PFS_REGNUM: > - return gdb_get_regl(mem_buf, env->pfault_select); > + return gdb_get_reg64(mem_buf, env->pfault_select); > case S390_VIRT_KVM_PFC_REGNUM: > - return gdb_get_regl(mem_buf, env->pfault_compare); > + return gdb_get_reg64(mem_buf, env->pfault_compare); > default: > return 0; > } > @@ -330,7 +330,7 @@ static int cpu_read_gs_reg(CPUState *cs, GByteArray *buf, int n) > S390CPU *cpu = S390_CPU(cs); > CPUS390XState *env = &cpu->env; > > - return gdb_get_regl(buf, env->gscb[n]); > + return gdb_get_reg64(buf, env->gscb[n]); > } > > static int cpu_write_gs_reg(CPUState *cs, uint8_t *mem_buf, int n) > -- > 2.52.0 > ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 4/8] target/s390x: Replace MO_TE -> MO_BE 2025-12-24 16:20 [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Philippe Mathieu-Daudé ` (2 preceding siblings ...) 2025-12-24 16:20 ` [PATCH 3/8] target/s390x: Replace gdb_get_regl() -> gdb_get_reg64() Philippe Mathieu-Daudé @ 2025-12-24 16:20 ` Philippe Mathieu-Daudé 2025-12-29 11:04 ` Manos Pitsidianakis 2025-12-24 16:20 ` [PATCH 5/8] target/s390x: Inline cpu_ld{uw, l}_code() calls in EX opcode helper Philippe Mathieu-Daudé ` (5 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Philippe Mathieu-Daudé @ 2025-12-24 16:20 UTC (permalink / raw) To: qemu-devel Cc: qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin, Philippe Mathieu-Daudé We only build the S390x target using big endianness order, therefore the MO_TE definitions expand to the big endian one. Use the latter which is more explicit. Mechanical change running: $ sed -i -e s/MO_TE/MO_BE/ \ $(git grep -wl MO_TE target/s390x/) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/s390x/tcg/insn-data.h.inc | 54 +++++------ target/s390x/tcg/mem_helper.c | 8 +- target/s390x/tcg/translate.c | 138 ++++++++++++++-------------- target/s390x/tcg/translate_vx.c.inc | 38 ++++---- 4 files changed, 119 insertions(+), 119 deletions(-) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc index ec730ee0919..baaafe922e9 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -42,10 +42,10 @@ C(0xb9d8, AHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, add, adds32) /* ADD IMMEDIATE */ C(0xc209, AFI, RIL_a, EI, r1, i2, new, r1_32, add, adds32) - D(0xeb6a, ASI, SIY, GIE, la1, i2, new, 0, asi, adds32, MO_TESL) + D(0xeb6a, ASI, SIY, GIE, la1, i2, new, 0, asi, adds32, MO_BESL) C(0xecd8, AHIK, RIE_d, DO, r3, i2, new, r1_32, add, adds32) C(0xc208, AGFI, RIL_a, EI, r1, i2, r1, 0, add, adds64) - D(0xeb7a, AGSI, SIY, GIE, la1, i2, new, 0, asi, adds64, MO_TEUQ) + D(0xeb7a, AGSI, SIY, GIE, la1, i2, new, 0, asi, adds64, MO_BEUQ) C(0xecd9, AGHIK, RIE_d, DO, r3, i2, r1, 0, add, adds64) /* ADD IMMEDIATE HIGH */ C(0xcc08, AIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, adds32) @@ -74,9 +74,9 @@ C(0xc20b, ALFI, RIL_a, EI, r1_32u, i2_32u, new, r1_32, add, addu32) C(0xc20a, ALGFI, RIL_a, EI, r1, i2_32u, r1, 0, addu64, addu64) /* ADD LOGICAL WITH SIGNED IMMEDIATE */ - D(0xeb6e, ALSI, SIY, GIE, la1, i2_32u, new, 0, asi, addu32, MO_TEUL) + D(0xeb6e, ALSI, SIY, GIE, la1, i2_32u, new, 0, asi, addu32, MO_BEUL) C(0xecda, ALHSIK, RIE_d, DO, r3_32u, i2_32u, new, r1_32, add, addu32) - D(0xeb7e, ALGSI, SIY, GIE, la1, i2, new, 0, asiu64, addu64, MO_TEUQ) + D(0xeb7e, ALGSI, SIY, GIE, la1, i2, new, 0, asiu64, addu64, MO_BEUQ) C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, addu64, addu64) /* ADD LOGICAL WITH SIGNED IMMEDIATE HIGH */ C(0xcc0a, ALSIH, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, addu32) @@ -270,12 +270,12 @@ D(0xec7d, CLGIJ, RIE_c, GIE, r1_o, i2_8u, 0, 0, cj, 0, 1) /* COMPARE AND SWAP */ - D(0xba00, CS, RS_a, Z, r3_32u, r1_32u, new, r1_32, cs, 0, MO_TEUL) - D(0xeb14, CSY, RSY_a, LD, r3_32u, r1_32u, new, r1_32, cs, 0, MO_TEUL) - D(0xeb30, CSG, RSY_a, Z, r3_o, r1_o, new, r1, cs, 0, MO_TEUQ) + D(0xba00, CS, RS_a, Z, r3_32u, r1_32u, new, r1_32, cs, 0, MO_BEUL) + D(0xeb14, CSY, RSY_a, LD, r3_32u, r1_32u, new, r1_32, cs, 0, MO_BEUL) + D(0xeb30, CSG, RSY_a, Z, r3_o, r1_o, new, r1, cs, 0, MO_BEUQ) /* COMPARE DOUBLE AND SWAP */ - D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ) - D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ) + D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_BEUQ) + D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_BEUQ) C(0xeb3e, CDSG, RSY_a, Z, la2, r3_D64, 0, r1_D64, cdsg, 0) /* COMPARE AND SWAP AND STORE */ C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0) @@ -443,20 +443,20 @@ /* LOAD ADDRESS RELATIVE LONG */ C(0xc000, LARL, RIL_b, Z, 0, ri2, 0, r1, mov2, 0) /* LOAD AND ADD */ - D(0xebf8, LAA, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, laa, adds32, MO_TESL) - D(0xebe8, LAAG, RSY_a, ILA, r3, a2, new, in2_r1, laa, adds64, MO_TEUQ) + D(0xebf8, LAA, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, laa, adds32, MO_BESL) + D(0xebe8, LAAG, RSY_a, ILA, r3, a2, new, in2_r1, laa, adds64, MO_BEUQ) /* LOAD AND ADD LOGICAL */ - D(0xebfa, LAAL, RSY_a, ILA, r3_32u, a2, new, in2_r1_32, laa, addu32, MO_TEUL) - D(0xebea, LAALG, RSY_a, ILA, r3, a2, new, in2_r1, laa_addu64, addu64, MO_TEUQ) + D(0xebfa, LAAL, RSY_a, ILA, r3_32u, a2, new, in2_r1_32, laa, addu32, MO_BEUL) + D(0xebea, LAALG, RSY_a, ILA, r3, a2, new, in2_r1, laa_addu64, addu64, MO_BEUQ) /* LOAD AND AND */ - D(0xebf4, LAN, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lan, nz32, MO_TESL) - D(0xebe4, LANG, RSY_a, ILA, r3, a2, new, in2_r1, lan, nz64, MO_TEUQ) + D(0xebf4, LAN, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lan, nz32, MO_BESL) + D(0xebe4, LANG, RSY_a, ILA, r3, a2, new, in2_r1, lan, nz64, MO_BEUQ) /* LOAD AND EXCLUSIVE OR */ - D(0xebf7, LAX, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lax, nz32, MO_TESL) - D(0xebe7, LAXG, RSY_a, ILA, r3, a2, new, in2_r1, lax, nz64, MO_TEUQ) + D(0xebf7, LAX, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lax, nz32, MO_BESL) + D(0xebe7, LAXG, RSY_a, ILA, r3, a2, new, in2_r1, lax, nz64, MO_BEUQ) /* LOAD AND OR */ - D(0xebf6, LAO, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lao, nz32, MO_TESL) - D(0xebe6, LAOG, RSY_a, ILA, r3, a2, new, in2_r1, lao, nz64, MO_TEUQ) + D(0xebf6, LAO, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lao, nz32, MO_BESL) + D(0xebe6, LAOG, RSY_a, ILA, r3, a2, new, in2_r1, lao, nz64, MO_BEUQ) /* LOAD AND TEST */ C(0x1200, LTR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, s32) C(0xb902, LTGR, RRE, Z, 0, r2_o, 0, r1, mov2, s64) @@ -572,8 +572,8 @@ C(0xb9e0, LOCFHR, RRF_c, LOC2, r1_sr32, r2_sr32, new, r1_32h, loc, 0) C(0xebe0, LOCFH, RSY_b, LOC2, r1_sr32, m2_32u, new, r1_32h, loc, 0) /* LOAD PAIR DISJOINT */ - D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL) - D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEUQ) + D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_BEUL) + D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_BEUQ) /* LOAD PAIR FROM QUADWORD */ C(0xe38f, LPQ, RXY_a, Z, 0, a2, 0, r1_D64, lpq, 0) /* LOAD POSITIVE */ @@ -1333,8 +1333,8 @@ #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ - E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, IF_PRIV) - E(0xb98a, CSPG, RRE, DAT_ENH, r1_o, ra2, r1_P, 0, csp, 0, MO_TEUQ, IF_PRIV) + E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_BEUL, IF_PRIV) + E(0xb98a, CSPG, RRE, DAT_ENH, r1_o, ra2, r1_P, 0, csp, 0, MO_BEUQ, IF_PRIV) /* DIAGNOSE (KVM hypercall) */ F(0x8300, DIAG, RSI, Z, 0, 0, 0, 0, diag, 0, IF_PRIV | IF_IO) /* INSERT STORAGE KEY EXTENDED */ @@ -1357,8 +1357,8 @@ F(0xe313, LRAY, RXY_a, LD, 0, a2, r1, 0, lra, 0, IF_PRIV) F(0xe303, LRAG, RXY_a, Z, 0, a2, r1, 0, lra, 0, IF_PRIV) /* LOAD USING REAL ADDRESS */ - E(0xb24b, LURA, RRE, Z, 0, ra2, new, r1_32, lura, 0, MO_TEUL, IF_PRIV) - E(0xb905, LURAG, RRE, Z, 0, ra2, r1, 0, lura, 0, MO_TEUQ, IF_PRIV) + E(0xb24b, LURA, RRE, Z, 0, ra2, new, r1_32, lura, 0, MO_BEUL, IF_PRIV) + E(0xb905, LURAG, RRE, Z, 0, ra2, r1, 0, lura, 0, MO_BEUQ, IF_PRIV) /* MOVE TO PRIMARY */ C(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0) /* MOVE TO SECONDARY */ @@ -1411,8 +1411,8 @@ /* STORE THEN OR SYSTEM MASK */ F(0xad00, STOSM, SI, Z, la1, 0, 0, 0, stnosm, 0, IF_PRIV) /* STORE USING REAL ADDRESS */ - E(0xb246, STURA, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_TEUL, IF_PRIV) - E(0xb925, STURG, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_TEUQ, IF_PRIV) + E(0xb246, STURA, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_BEUL, IF_PRIV) + E(0xb925, STURG, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_BEUQ, IF_PRIV) /* TEST BLOCK */ F(0xb22c, TB, RRE, Z, 0, r2_o, 0, 0, testblock, 0, IF_PRIV) /* TEST PROTECTION */ diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 0c7e099df21..507eb7feac7 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1776,10 +1776,10 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { uint32_t mem_idx = s390x_env_mmu_index(env, false); - MemOpIdx oi16 = make_memop_idx(MO_TE | MO_128, mem_idx); - MemOpIdx oi8 = make_memop_idx(MO_TE | MO_64, mem_idx); - MemOpIdx oi4 = make_memop_idx(MO_TE | MO_32, mem_idx); - MemOpIdx oi2 = make_memop_idx(MO_TE | MO_16, mem_idx); + MemOpIdx oi16 = make_memop_idx(MO_BE | MO_128, mem_idx); + MemOpIdx oi8 = make_memop_idx(MO_BE | MO_64, mem_idx); + MemOpIdx oi4 = make_memop_idx(MO_BE | MO_32, mem_idx); + MemOpIdx oi2 = make_memop_idx(MO_BE | MO_16, mem_idx); MemOpIdx oi1 = make_memop_idx(MO_8, mem_idx); uintptr_t ra = GETPC(); uint32_t fc = extract32(env->regs[0], 0, 8); diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 4d2b8c5e2be..db2276f1cfc 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1914,7 +1914,7 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o) case 2: case 4: case 8: - mop = ctz32(l + 1) | MO_TE; + mop = ctz32(l + 1) | MO_BE; /* Do not update cc_src yet: loading cc_dst may cause an exception. */ src = tcg_temp_new_i64(); tcg_gen_qemu_ld_tl(src, o->addr1, get_mem_index(s), mop); @@ -2124,7 +2124,7 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps *o) static DisasJumpType op_cvb(DisasContext *s, DisasOps *o) { TCGv_i64 t = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_BEUQ); gen_helper_cvb(tcg_env, tcg_constant_i32(get_field(s, r1)), t); return DISAS_NEXT; } @@ -2132,7 +2132,7 @@ static DisasJumpType op_cvb(DisasContext *s, DisasOps *o) static DisasJumpType op_cvbg(DisasContext *s, DisasOps *o) { TCGv_i128 t = tcg_temp_new_i128(); - tcg_gen_qemu_ld_i128(t, o->addr1, get_mem_index(s), MO_TE | MO_128); + tcg_gen_qemu_ld_i128(t, o->addr1, get_mem_index(s), MO_BE | MO_128); gen_helper_cvbg(o->out, tcg_env, t); return DISAS_NEXT; } @@ -2143,7 +2143,7 @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps *o) TCGv_i32 t2 = tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, o->in1); gen_helper_cvd(t1, t2); - tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_BEUQ); return DISAS_NEXT; } @@ -2151,7 +2151,7 @@ static DisasJumpType op_cvdg(DisasContext *s, DisasOps *o) { TCGv_i128 t = tcg_temp_new_i128(); gen_helper_cvdg(t, o->in1); - tcg_gen_qemu_st_i128(t, o->in2, get_mem_index(s), MO_TE | MO_128); + tcg_gen_qemu_st_i128(t, o->in2, get_mem_index(s), MO_BE | MO_128); return DISAS_NEXT; } @@ -2413,7 +2413,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o) switch (m3) { case 0xf: /* Effectively a 32-bit load. */ - tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUL); len = 32; goto one_insert; @@ -2421,7 +2421,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o) case 0x6: case 0x3: /* Effectively a 16-bit load. */ - tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUW); len = 16; goto one_insert; @@ -2735,34 +2735,34 @@ static DisasJumpType op_ld8u(DisasContext *s, DisasOps *o) static DisasJumpType op_ld16s(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TESW); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BESW); return DISAS_NEXT; } static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUW); return DISAS_NEXT; } static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o) { tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), - MO_TESL | s->insn->data); + MO_BESL | s->insn->data); return DISAS_NEXT; } static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o) { tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), - MO_TEUL | s->insn->data); + MO_BEUL | s->insn->data); return DISAS_NEXT; } static DisasJumpType op_ld64(DisasContext *s, DisasOps *o) { tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), - MO_TEUQ | s->insn->data); + MO_BEUQ | s->insn->data); return DISAS_NEXT; } @@ -2780,7 +2780,7 @@ static DisasJumpType op_lat(DisasContext *s, DisasOps *o) static DisasJumpType op_lgat(DisasContext *s, DisasOps *o) { TCGLabel *lab = gen_new_label(); - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUQ); /* The value is stored even in case of trap. */ tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab); gen_trap(s); @@ -2803,7 +2803,7 @@ static DisasJumpType op_llgfat(DisasContext *s, DisasOps *o) { TCGLabel *lab = gen_new_label(); - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUL); /* The value is stored even in case of trap. */ tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab); gen_trap(s); @@ -2901,7 +2901,7 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o) */ mask = tcg_temp_new_i64(); addr = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(mask, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN_8); + tcg_gen_qemu_ld_i64(mask, o->in2, get_mem_index(s), MO_BEUQ | MO_ALIGN_8); tcg_gen_andi_i64(addr, mask, PSW_MASK_SHORT_ADDR); tcg_gen_andi_i64(mask, mask, PSW_MASK_SHORT_CTRL); tcg_gen_xori_i64(mask, mask, PSW_MASK_SHORTPSW); @@ -2918,9 +2918,9 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o) t1 = tcg_temp_new_i64(); t2 = tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), - MO_TEUQ | MO_ALIGN_8); + MO_BEUQ | MO_ALIGN_8); tcg_gen_addi_i64(o->in2, o->in2, 8); - tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_BEUQ); gen_helper_load_psw(tcg_env, t1, t2); return DISAS_NORETURN; } @@ -2944,7 +2944,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o) /* Only one register to read. */ t1 = tcg_temp_new_i64(); if (unlikely(r1 == r3)) { - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); store_reg32_i64(r1, t1); return DISAS_NEXT; } @@ -2952,9 +2952,9 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o) /* First load the values of the first and last registers to trigger possible page faults. */ t2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15)); - tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_BEUL); store_reg32_i64(r1, t1); store_reg32_i64(r3, t2); @@ -2969,7 +2969,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o) while (r1 != r3) { r1 = (r1 + 1) & 15; tcg_gen_add_i64(o->in2, o->in2, t2); - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); store_reg32_i64(r1, t1); } return DISAS_NEXT; @@ -2984,7 +2984,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o) /* Only one register to read. */ t1 = tcg_temp_new_i64(); if (unlikely(r1 == r3)) { - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); store_reg32h_i64(r1, t1); return DISAS_NEXT; } @@ -2992,9 +2992,9 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o) /* First load the values of the first and last registers to trigger possible page faults. */ t2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15)); - tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_BEUL); store_reg32h_i64(r1, t1); store_reg32h_i64(r3, t2); @@ -3009,7 +3009,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o) while (r1 != r3) { r1 = (r1 + 1) & 15; tcg_gen_add_i64(o->in2, o->in2, t2); - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); store_reg32h_i64(r1, t1); } return DISAS_NEXT; @@ -3023,7 +3023,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o) /* Only one register to read. */ if (unlikely(r1 == r3)) { - tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_BEUQ); return DISAS_NEXT; } @@ -3031,9 +3031,9 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o) possible page faults. */ t1 = tcg_temp_new_i64(); t2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUQ); tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15)); - tcg_gen_qemu_ld_i64(regs[r3], t2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(regs[r3], t2, get_mem_index(s), MO_BEUQ); tcg_gen_mov_i64(regs[r1], t1); /* Only two registers to read. */ @@ -3047,7 +3047,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o) while (r1 != r3) { r1 = (r1 + 1) & 15; tcg_gen_add_i64(o->in2, o->in2, t1); - tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_BEUQ); } return DISAS_NEXT; } @@ -3080,7 +3080,7 @@ static DisasJumpType op_lpq(DisasContext *s, DisasOps *o) { o->out_128 = tcg_temp_new_i128(); tcg_gen_qemu_ld_i128(o->out_128, o->in2, get_mem_index(s), - MO_TE | MO_128 | MO_ALIGN); + MO_BE | MO_128 | MO_ALIGN); return DISAS_NEXT; } @@ -3896,15 +3896,15 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps *o) a = get_address(s, 0, get_field(s, b2), get_field(s, d2)); switch (s->insn->data) { case 1: /* STOCG */ - tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEUQ); break; case 0: /* STOC */ - tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEUL); break; case 2: /* STOCFH */ h = tcg_temp_new_i64(); tcg_gen_shri_i64(h, regs[r1], 32); - tcg_gen_qemu_st_i64(h, a, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(h, a, get_mem_index(s), MO_BEUL); break; default: g_assert_not_reached(); @@ -4023,7 +4023,7 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOps *o) gen_addi_and_wrap_i64(s, o->addr1, regs[r3], 0); /* load the third operand into r3 before modifying anything */ - tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_BEUQ); /* subtract CPU timer from first operand and store in GR0 */ gen_helper_stpt(tmp, tcg_env); @@ -4101,9 +4101,9 @@ static DisasJumpType op_stcke(DisasContext *s, DisasOps *o) tcg_gen_shri_i64(c1, c1, 8); tcg_gen_ori_i64(c2, c2, 0x10000); tcg_gen_or_i64(c2, c2, todpr); - tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_BEUQ); tcg_gen_addi_i64(o->in2, o->in2, 8); - tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_BEUQ); /* ??? We don't implement clock states. */ gen_op_movi_cc(s, 0); return DISAS_NEXT; @@ -4361,21 +4361,21 @@ static DisasJumpType op_st8(DisasContext *s, DisasOps *o) static DisasJumpType op_st16(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_BEUW); return DISAS_NEXT; } static DisasJumpType op_st32(DisasContext *s, DisasOps *o) { tcg_gen_qemu_st_tl(o->in1, o->in2, get_mem_index(s), - MO_TEUL | s->insn->data); + MO_BEUL | s->insn->data); return DISAS_NEXT; } static DisasJumpType op_st64(DisasContext *s, DisasOps *o) { tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), - MO_TEUQ | s->insn->data); + MO_BEUQ | s->insn->data); return DISAS_NEXT; } @@ -4399,7 +4399,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o) case 0xf: /* Effectively a 32-bit store. */ tcg_gen_shri_i64(tmp, o->in1, pos); - tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUL); break; case 0xc: @@ -4407,7 +4407,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o) case 0x3: /* Effectively a 16-bit store. */ tcg_gen_shri_i64(tmp, o->in1, pos); - tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUW); break; case 0x8: @@ -4445,7 +4445,7 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o) while (1) { tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), - size == 8 ? MO_TEUQ : MO_TEUL); + size == 8 ? MO_BEUQ : MO_BEUL); if (r1 == r3) { break; } @@ -4466,7 +4466,7 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o) while (1) { tcg_gen_shl_i64(t, regs[r1], t32); - tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_BEUL); if (r1 == r3) { break; } @@ -4482,7 +4482,7 @@ static DisasJumpType op_stpq(DisasContext *s, DisasOps *o) tcg_gen_concat_i64_i128(t16, o->out2, o->out); tcg_gen_qemu_st_i128(t16, o->in2, get_mem_index(s), - MO_TE | MO_128 | MO_ALIGN); + MO_BE | MO_128 | MO_ALIGN); return DISAS_NEXT; } @@ -5284,49 +5284,49 @@ static void wout_m1_8(DisasContext *s, DisasOps *o) static void wout_m1_16(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUW); } #define SPEC_wout_m1_16 0 #ifndef CONFIG_USER_ONLY static void wout_m1_16a(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUW | MO_ALIGN); + tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUW | MO_ALIGN); } #define SPEC_wout_m1_16a 0 #endif static void wout_m1_32(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUL); } #define SPEC_wout_m1_32 0 #ifndef CONFIG_USER_ONLY static void wout_m1_32a(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUL | MO_ALIGN); + tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUL | MO_ALIGN); } #define SPEC_wout_m1_32a 0 #endif static void wout_m1_64(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUQ); } #define SPEC_wout_m1_64 0 #ifndef CONFIG_USER_ONLY static void wout_m1_64a(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ | MO_ALIGN); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUQ | MO_ALIGN); } #define SPEC_wout_m1_64a 0 #endif static void wout_m2_32(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_BEUL); } #define SPEC_wout_m2_32 0 @@ -5529,7 +5529,7 @@ static void in1_m1_16s(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESW); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BESW); } #define SPEC_in1_m1_16s 0 @@ -5537,7 +5537,7 @@ static void in1_m1_16u(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUW); } #define SPEC_in1_m1_16u 0 @@ -5545,7 +5545,7 @@ static void in1_m1_32s(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESL); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BESL); } #define SPEC_in1_m1_32s 0 @@ -5553,7 +5553,7 @@ static void in1_m1_32u(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUL); } #define SPEC_in1_m1_32u 0 @@ -5561,7 +5561,7 @@ static void in1_m1_64(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUQ); } #define SPEC_in1_m1_64 0 @@ -5787,28 +5787,28 @@ static void in2_m2_8u(DisasContext *s, DisasOps *o) static void in2_m2_16s(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESW); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESW); } #define SPEC_in2_m2_16s 0 static void in2_m2_16u(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUW); } #define SPEC_in2_m2_16u 0 static void in2_m2_32s(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESL); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESL); } #define SPEC_in2_m2_32s 0 static void in2_m2_32u(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUL); } #define SPEC_in2_m2_32u 0 @@ -5816,7 +5816,7 @@ static void in2_m2_32u(DisasContext *s, DisasOps *o) static void in2_m2_32ua(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_TEUL | MO_ALIGN); + tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_BEUL | MO_ALIGN); } #define SPEC_in2_m2_32ua 0 #endif @@ -5824,14 +5824,14 @@ static void in2_m2_32ua(DisasContext *s, DisasOps *o) static void in2_m2_64(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUQ); } #define SPEC_in2_m2_64 0 static void in2_m2_64w(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->in2, o->in2, 0); } #define SPEC_in2_m2_64w 0 @@ -5840,7 +5840,7 @@ static void in2_m2_64w(DisasContext *s, DisasOps *o) static void in2_m2_64a(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUQ | MO_ALIGN); } #define SPEC_in2_m2_64a 0 #endif @@ -5848,14 +5848,14 @@ static void in2_m2_64a(DisasContext *s, DisasOps *o) static void in2_mri2_16s(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TESW); + tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_BESW); } #define SPEC_in2_mri2_16s 0 static void in2_mri2_16u(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TEUW); + tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_BEUW); } #define SPEC_in2_mri2_16u 0 @@ -5863,7 +5863,7 @@ static void in2_mri2_32s(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), - MO_TESL | MO_ALIGN); + MO_BESL | MO_ALIGN); } #define SPEC_in2_mri2_32s 0 @@ -5871,7 +5871,7 @@ static void in2_mri2_32u(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), - MO_TEUL | MO_ALIGN); + MO_BEUL | MO_ALIGN); } #define SPEC_in2_mri2_32u 0 @@ -5879,7 +5879,7 @@ static void in2_mri2_64(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), - MO_TEUQ | MO_ALIGN); + MO_BEUQ | MO_ALIGN); } #define SPEC_in2_mri2_64 0 diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/translate_vx.c.inc index f3b4b48ab7b..b53e9e52639 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -331,7 +331,7 @@ static DisasJumpType op_vge(DisasContext *s, DisasOps *o) tcg_gen_add_i64(o->addr1, o->addr1, tmp); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0); - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); return DISAS_NEXT; } @@ -402,9 +402,9 @@ static DisasJumpType op_vl(DisasContext *s, DisasOps *o) TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); return DISAS_NEXT; @@ -427,7 +427,7 @@ static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o) } tmp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); gen_gvec_dup_i64(es, get_field(s, v1), tmp); return DISAS_NEXT; } @@ -561,7 +561,7 @@ static DisasJumpType op_vle(DisasContext *s, DisasOps *o) } tmp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); return DISAS_NEXT; } @@ -595,9 +595,9 @@ static DisasJumpType op_vler(DisasContext *s, DisasOps *o) TCGv_i64 t1 = tcg_temp_new_i64(); /* Begin with the two doublewords swapped... */ - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_BEUQ); /* ... then swap smaller elements within the doublewords as required. */ switch (es) { @@ -693,7 +693,7 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o) } t = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_BE | es); gen_gvec_dup_imm(es, get_field(s, v1), 0); write_vec_element_i64(t, get_field(s, v1), enr, es); return DISAS_NEXT; @@ -717,16 +717,16 @@ static DisasJumpType op_vlm(DisasContext *s, DisasOps *o) t0 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64(); gen_addi_and_wrap_i64(s, t0, o->addr1, (v3 - v1) * 16 + 8); - tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_BEUQ); for (;; v1++) { - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); write_vec_element_i64(t1, v1, 0, ES_64); if (v1 == v3) { break; } gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); write_vec_element_i64(t1, v1, 1, ES_64); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); } @@ -1009,7 +1009,7 @@ static DisasJumpType op_vsce(DisasContext *s, DisasOps *o) gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0); read_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); return DISAS_NEXT; } @@ -1063,10 +1063,10 @@ static DisasJumpType op_vst(DisasContext *s, DisasOps *o) tmp = tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); return DISAS_NEXT; } @@ -1154,7 +1154,7 @@ static DisasJumpType op_vste(DisasContext *s, DisasOps *o) tmp = tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); return DISAS_NEXT; } @@ -1193,9 +1193,9 @@ static DisasJumpType op_vster(DisasContext *s, DisasOps *o) g_assert_not_reached(); } - tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); return DISAS_NEXT; } @@ -1217,10 +1217,10 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOps *o) tmp = tcg_temp_new_i64(); for (;; v1++) { read_vec_element_i64(tmp, v1, 0, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); read_vec_element_i64(tmp, v1, 1, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); if (v1 == v3) { break; } -- 2.52.0 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 4/8] target/s390x: Replace MO_TE -> MO_BE 2025-12-24 16:20 ` [PATCH 4/8] target/s390x: Replace MO_TE -> MO_BE Philippe Mathieu-Daudé @ 2025-12-29 11:04 ` Manos Pitsidianakis 0 siblings, 0 replies; 23+ messages in thread From: Manos Pitsidianakis @ 2025-12-29 11:04 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On Wed, Dec 24, 2025 at 6:21 PM Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > We only build the S390x target using big endianness order, > therefore the MO_TE definitions expand to the big endian > one. Use the latter which is more explicit. > > Mechanical change running: > > $ sed -i -e s/MO_TE/MO_BE/ \ > $(git grep -wl MO_TE target/s390x/) > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> > target/s390x/tcg/insn-data.h.inc | 54 +++++------ > target/s390x/tcg/mem_helper.c | 8 +- > target/s390x/tcg/translate.c | 138 ++++++++++++++-------------- > target/s390x/tcg/translate_vx.c.inc | 38 ++++---- > 4 files changed, 119 insertions(+), 119 deletions(-) > > diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc > index ec730ee0919..baaafe922e9 100644 > --- a/target/s390x/tcg/insn-data.h.inc > +++ b/target/s390x/tcg/insn-data.h.inc > @@ -42,10 +42,10 @@ > C(0xb9d8, AHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, add, adds32) > /* ADD IMMEDIATE */ > C(0xc209, AFI, RIL_a, EI, r1, i2, new, r1_32, add, adds32) > - D(0xeb6a, ASI, SIY, GIE, la1, i2, new, 0, asi, adds32, MO_TESL) > + D(0xeb6a, ASI, SIY, GIE, la1, i2, new, 0, asi, adds32, MO_BESL) > C(0xecd8, AHIK, RIE_d, DO, r3, i2, new, r1_32, add, adds32) > C(0xc208, AGFI, RIL_a, EI, r1, i2, r1, 0, add, adds64) > - D(0xeb7a, AGSI, SIY, GIE, la1, i2, new, 0, asi, adds64, MO_TEUQ) > + D(0xeb7a, AGSI, SIY, GIE, la1, i2, new, 0, asi, adds64, MO_BEUQ) > C(0xecd9, AGHIK, RIE_d, DO, r3, i2, r1, 0, add, adds64) > /* ADD IMMEDIATE HIGH */ > C(0xcc08, AIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, adds32) > @@ -74,9 +74,9 @@ > C(0xc20b, ALFI, RIL_a, EI, r1_32u, i2_32u, new, r1_32, add, addu32) > C(0xc20a, ALGFI, RIL_a, EI, r1, i2_32u, r1, 0, addu64, addu64) > /* ADD LOGICAL WITH SIGNED IMMEDIATE */ > - D(0xeb6e, ALSI, SIY, GIE, la1, i2_32u, new, 0, asi, addu32, MO_TEUL) > + D(0xeb6e, ALSI, SIY, GIE, la1, i2_32u, new, 0, asi, addu32, MO_BEUL) > C(0xecda, ALHSIK, RIE_d, DO, r3_32u, i2_32u, new, r1_32, add, addu32) > - D(0xeb7e, ALGSI, SIY, GIE, la1, i2, new, 0, asiu64, addu64, MO_TEUQ) > + D(0xeb7e, ALGSI, SIY, GIE, la1, i2, new, 0, asiu64, addu64, MO_BEUQ) > C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, addu64, addu64) > /* ADD LOGICAL WITH SIGNED IMMEDIATE HIGH */ > C(0xcc0a, ALSIH, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, addu32) > @@ -270,12 +270,12 @@ > D(0xec7d, CLGIJ, RIE_c, GIE, r1_o, i2_8u, 0, 0, cj, 0, 1) > > /* COMPARE AND SWAP */ > - D(0xba00, CS, RS_a, Z, r3_32u, r1_32u, new, r1_32, cs, 0, MO_TEUL) > - D(0xeb14, CSY, RSY_a, LD, r3_32u, r1_32u, new, r1_32, cs, 0, MO_TEUL) > - D(0xeb30, CSG, RSY_a, Z, r3_o, r1_o, new, r1, cs, 0, MO_TEUQ) > + D(0xba00, CS, RS_a, Z, r3_32u, r1_32u, new, r1_32, cs, 0, MO_BEUL) > + D(0xeb14, CSY, RSY_a, LD, r3_32u, r1_32u, new, r1_32, cs, 0, MO_BEUL) > + D(0xeb30, CSG, RSY_a, Z, r3_o, r1_o, new, r1, cs, 0, MO_BEUQ) > /* COMPARE DOUBLE AND SWAP */ > - D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ) > - D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ) > + D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_BEUQ) > + D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_BEUQ) > C(0xeb3e, CDSG, RSY_a, Z, la2, r3_D64, 0, r1_D64, cdsg, 0) > /* COMPARE AND SWAP AND STORE */ > C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0) > @@ -443,20 +443,20 @@ > /* LOAD ADDRESS RELATIVE LONG */ > C(0xc000, LARL, RIL_b, Z, 0, ri2, 0, r1, mov2, 0) > /* LOAD AND ADD */ > - D(0xebf8, LAA, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, laa, adds32, MO_TESL) > - D(0xebe8, LAAG, RSY_a, ILA, r3, a2, new, in2_r1, laa, adds64, MO_TEUQ) > + D(0xebf8, LAA, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, laa, adds32, MO_BESL) > + D(0xebe8, LAAG, RSY_a, ILA, r3, a2, new, in2_r1, laa, adds64, MO_BEUQ) > /* LOAD AND ADD LOGICAL */ > - D(0xebfa, LAAL, RSY_a, ILA, r3_32u, a2, new, in2_r1_32, laa, addu32, MO_TEUL) > - D(0xebea, LAALG, RSY_a, ILA, r3, a2, new, in2_r1, laa_addu64, addu64, MO_TEUQ) > + D(0xebfa, LAAL, RSY_a, ILA, r3_32u, a2, new, in2_r1_32, laa, addu32, MO_BEUL) > + D(0xebea, LAALG, RSY_a, ILA, r3, a2, new, in2_r1, laa_addu64, addu64, MO_BEUQ) > /* LOAD AND AND */ > - D(0xebf4, LAN, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lan, nz32, MO_TESL) > - D(0xebe4, LANG, RSY_a, ILA, r3, a2, new, in2_r1, lan, nz64, MO_TEUQ) > + D(0xebf4, LAN, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lan, nz32, MO_BESL) > + D(0xebe4, LANG, RSY_a, ILA, r3, a2, new, in2_r1, lan, nz64, MO_BEUQ) > /* LOAD AND EXCLUSIVE OR */ > - D(0xebf7, LAX, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lax, nz32, MO_TESL) > - D(0xebe7, LAXG, RSY_a, ILA, r3, a2, new, in2_r1, lax, nz64, MO_TEUQ) > + D(0xebf7, LAX, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lax, nz32, MO_BESL) > + D(0xebe7, LAXG, RSY_a, ILA, r3, a2, new, in2_r1, lax, nz64, MO_BEUQ) > /* LOAD AND OR */ > - D(0xebf6, LAO, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lao, nz32, MO_TESL) > - D(0xebe6, LAOG, RSY_a, ILA, r3, a2, new, in2_r1, lao, nz64, MO_TEUQ) > + D(0xebf6, LAO, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lao, nz32, MO_BESL) > + D(0xebe6, LAOG, RSY_a, ILA, r3, a2, new, in2_r1, lao, nz64, MO_BEUQ) > /* LOAD AND TEST */ > C(0x1200, LTR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, s32) > C(0xb902, LTGR, RRE, Z, 0, r2_o, 0, r1, mov2, s64) > @@ -572,8 +572,8 @@ > C(0xb9e0, LOCFHR, RRF_c, LOC2, r1_sr32, r2_sr32, new, r1_32h, loc, 0) > C(0xebe0, LOCFH, RSY_b, LOC2, r1_sr32, m2_32u, new, r1_32h, loc, 0) > /* LOAD PAIR DISJOINT */ > - D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL) > - D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEUQ) > + D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_BEUL) > + D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_BEUQ) > /* LOAD PAIR FROM QUADWORD */ > C(0xe38f, LPQ, RXY_a, Z, 0, a2, 0, r1_D64, lpq, 0) > /* LOAD POSITIVE */ > @@ -1333,8 +1333,8 @@ > > #ifndef CONFIG_USER_ONLY > /* COMPARE AND SWAP AND PURGE */ > - E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, IF_PRIV) > - E(0xb98a, CSPG, RRE, DAT_ENH, r1_o, ra2, r1_P, 0, csp, 0, MO_TEUQ, IF_PRIV) > + E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_BEUL, IF_PRIV) > + E(0xb98a, CSPG, RRE, DAT_ENH, r1_o, ra2, r1_P, 0, csp, 0, MO_BEUQ, IF_PRIV) > /* DIAGNOSE (KVM hypercall) */ > F(0x8300, DIAG, RSI, Z, 0, 0, 0, 0, diag, 0, IF_PRIV | IF_IO) > /* INSERT STORAGE KEY EXTENDED */ > @@ -1357,8 +1357,8 @@ > F(0xe313, LRAY, RXY_a, LD, 0, a2, r1, 0, lra, 0, IF_PRIV) > F(0xe303, LRAG, RXY_a, Z, 0, a2, r1, 0, lra, 0, IF_PRIV) > /* LOAD USING REAL ADDRESS */ > - E(0xb24b, LURA, RRE, Z, 0, ra2, new, r1_32, lura, 0, MO_TEUL, IF_PRIV) > - E(0xb905, LURAG, RRE, Z, 0, ra2, r1, 0, lura, 0, MO_TEUQ, IF_PRIV) > + E(0xb24b, LURA, RRE, Z, 0, ra2, new, r1_32, lura, 0, MO_BEUL, IF_PRIV) > + E(0xb905, LURAG, RRE, Z, 0, ra2, r1, 0, lura, 0, MO_BEUQ, IF_PRIV) > /* MOVE TO PRIMARY */ > C(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0) > /* MOVE TO SECONDARY */ > @@ -1411,8 +1411,8 @@ > /* STORE THEN OR SYSTEM MASK */ > F(0xad00, STOSM, SI, Z, la1, 0, 0, 0, stnosm, 0, IF_PRIV) > /* STORE USING REAL ADDRESS */ > - E(0xb246, STURA, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_TEUL, IF_PRIV) > - E(0xb925, STURG, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_TEUQ, IF_PRIV) > + E(0xb246, STURA, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_BEUL, IF_PRIV) > + E(0xb925, STURG, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_BEUQ, IF_PRIV) > /* TEST BLOCK */ > F(0xb22c, TB, RRE, Z, 0, r2_o, 0, 0, testblock, 0, IF_PRIV) > /* TEST PROTECTION */ > diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c > index 0c7e099df21..507eb7feac7 100644 > --- a/target/s390x/tcg/mem_helper.c > +++ b/target/s390x/tcg/mem_helper.c > @@ -1776,10 +1776,10 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, > uint64_t a2, bool parallel) > { > uint32_t mem_idx = s390x_env_mmu_index(env, false); > - MemOpIdx oi16 = make_memop_idx(MO_TE | MO_128, mem_idx); > - MemOpIdx oi8 = make_memop_idx(MO_TE | MO_64, mem_idx); > - MemOpIdx oi4 = make_memop_idx(MO_TE | MO_32, mem_idx); > - MemOpIdx oi2 = make_memop_idx(MO_TE | MO_16, mem_idx); > + MemOpIdx oi16 = make_memop_idx(MO_BE | MO_128, mem_idx); > + MemOpIdx oi8 = make_memop_idx(MO_BE | MO_64, mem_idx); > + MemOpIdx oi4 = make_memop_idx(MO_BE | MO_32, mem_idx); > + MemOpIdx oi2 = make_memop_idx(MO_BE | MO_16, mem_idx); > MemOpIdx oi1 = make_memop_idx(MO_8, mem_idx); > uintptr_t ra = GETPC(); > uint32_t fc = extract32(env->regs[0], 0, 8); > diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c > index 4d2b8c5e2be..db2276f1cfc 100644 > --- a/target/s390x/tcg/translate.c > +++ b/target/s390x/tcg/translate.c > @@ -1914,7 +1914,7 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o) > case 2: > case 4: > case 8: > - mop = ctz32(l + 1) | MO_TE; > + mop = ctz32(l + 1) | MO_BE; > /* Do not update cc_src yet: loading cc_dst may cause an exception. */ > src = tcg_temp_new_i64(); > tcg_gen_qemu_ld_tl(src, o->addr1, get_mem_index(s), mop); > @@ -2124,7 +2124,7 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps *o) > static DisasJumpType op_cvb(DisasContext *s, DisasOps *o) > { > TCGv_i64 t = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_BEUQ); > gen_helper_cvb(tcg_env, tcg_constant_i32(get_field(s, r1)), t); > return DISAS_NEXT; > } > @@ -2132,7 +2132,7 @@ static DisasJumpType op_cvb(DisasContext *s, DisasOps *o) > static DisasJumpType op_cvbg(DisasContext *s, DisasOps *o) > { > TCGv_i128 t = tcg_temp_new_i128(); > - tcg_gen_qemu_ld_i128(t, o->addr1, get_mem_index(s), MO_TE | MO_128); > + tcg_gen_qemu_ld_i128(t, o->addr1, get_mem_index(s), MO_BE | MO_128); > gen_helper_cvbg(o->out, tcg_env, t); > return DISAS_NEXT; > } > @@ -2143,7 +2143,7 @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps *o) > TCGv_i32 t2 = tcg_temp_new_i32(); > tcg_gen_extrl_i64_i32(t2, o->in1); > gen_helper_cvd(t1, t2); > - tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_BEUQ); > return DISAS_NEXT; > } > > @@ -2151,7 +2151,7 @@ static DisasJumpType op_cvdg(DisasContext *s, DisasOps *o) > { > TCGv_i128 t = tcg_temp_new_i128(); > gen_helper_cvdg(t, o->in1); > - tcg_gen_qemu_st_i128(t, o->in2, get_mem_index(s), MO_TE | MO_128); > + tcg_gen_qemu_st_i128(t, o->in2, get_mem_index(s), MO_BE | MO_128); > return DISAS_NEXT; > } > > @@ -2413,7 +2413,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o) > switch (m3) { > case 0xf: > /* Effectively a 32-bit load. */ > - tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUL); > len = 32; > goto one_insert; > > @@ -2421,7 +2421,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o) > case 0x6: > case 0x3: > /* Effectively a 16-bit load. */ > - tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUW); > + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUW); > len = 16; > goto one_insert; > > @@ -2735,34 +2735,34 @@ static DisasJumpType op_ld8u(DisasContext *s, DisasOps *o) > > static DisasJumpType op_ld16s(DisasContext *s, DisasOps *o) > { > - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TESW); > + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BESW); > return DISAS_NEXT; > } > > static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o) > { > - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUW); > + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUW); > return DISAS_NEXT; > } > > static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o) > { > tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), > - MO_TESL | s->insn->data); > + MO_BESL | s->insn->data); > return DISAS_NEXT; > } > > static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o) > { > tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), > - MO_TEUL | s->insn->data); > + MO_BEUL | s->insn->data); > return DISAS_NEXT; > } > > static DisasJumpType op_ld64(DisasContext *s, DisasOps *o) > { > tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), > - MO_TEUQ | s->insn->data); > + MO_BEUQ | s->insn->data); > return DISAS_NEXT; > } > > @@ -2780,7 +2780,7 @@ static DisasJumpType op_lat(DisasContext *s, DisasOps *o) > static DisasJumpType op_lgat(DisasContext *s, DisasOps *o) > { > TCGLabel *lab = gen_new_label(); > - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUQ); > /* The value is stored even in case of trap. */ > tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab); > gen_trap(s); > @@ -2803,7 +2803,7 @@ static DisasJumpType op_llgfat(DisasContext *s, DisasOps *o) > { > TCGLabel *lab = gen_new_label(); > > - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUL); > /* The value is stored even in case of trap. */ > tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab); > gen_trap(s); > @@ -2901,7 +2901,7 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o) > */ > mask = tcg_temp_new_i64(); > addr = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(mask, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN_8); > + tcg_gen_qemu_ld_i64(mask, o->in2, get_mem_index(s), MO_BEUQ | MO_ALIGN_8); > tcg_gen_andi_i64(addr, mask, PSW_MASK_SHORT_ADDR); > tcg_gen_andi_i64(mask, mask, PSW_MASK_SHORT_CTRL); > tcg_gen_xori_i64(mask, mask, PSW_MASK_SHORTPSW); > @@ -2918,9 +2918,9 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o) > t1 = tcg_temp_new_i64(); > t2 = tcg_temp_new_i64(); > tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), > - MO_TEUQ | MO_ALIGN_8); > + MO_BEUQ | MO_ALIGN_8); > tcg_gen_addi_i64(o->in2, o->in2, 8); > - tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_BEUQ); > gen_helper_load_psw(tcg_env, t1, t2); > return DISAS_NORETURN; > } > @@ -2944,7 +2944,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o) > /* Only one register to read. */ > t1 = tcg_temp_new_i64(); > if (unlikely(r1 == r3)) { > - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); > store_reg32_i64(r1, t1); > return DISAS_NEXT; > } > @@ -2952,9 +2952,9 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o) > /* First load the values of the first and last registers to trigger > possible page faults. */ > t2 = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); > tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15)); > - tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_BEUL); > store_reg32_i64(r1, t1); > store_reg32_i64(r3, t2); > > @@ -2969,7 +2969,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o) > while (r1 != r3) { > r1 = (r1 + 1) & 15; > tcg_gen_add_i64(o->in2, o->in2, t2); > - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); > store_reg32_i64(r1, t1); > } > return DISAS_NEXT; > @@ -2984,7 +2984,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o) > /* Only one register to read. */ > t1 = tcg_temp_new_i64(); > if (unlikely(r1 == r3)) { > - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); > store_reg32h_i64(r1, t1); > return DISAS_NEXT; > } > @@ -2992,9 +2992,9 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o) > /* First load the values of the first and last registers to trigger > possible page faults. */ > t2 = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); > tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15)); > - tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_BEUL); > store_reg32h_i64(r1, t1); > store_reg32h_i64(r3, t2); > > @@ -3009,7 +3009,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o) > while (r1 != r3) { > r1 = (r1 + 1) & 15; > tcg_gen_add_i64(o->in2, o->in2, t2); > - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); > store_reg32h_i64(r1, t1); > } > return DISAS_NEXT; > @@ -3023,7 +3023,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o) > > /* Only one register to read. */ > if (unlikely(r1 == r3)) { > - tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_BEUQ); > return DISAS_NEXT; > } > > @@ -3031,9 +3031,9 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o) > possible page faults. */ > t1 = tcg_temp_new_i64(); > t2 = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUQ); > tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15)); > - tcg_gen_qemu_ld_i64(regs[r3], t2, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(regs[r3], t2, get_mem_index(s), MO_BEUQ); > tcg_gen_mov_i64(regs[r1], t1); > > /* Only two registers to read. */ > @@ -3047,7 +3047,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o) > while (r1 != r3) { > r1 = (r1 + 1) & 15; > tcg_gen_add_i64(o->in2, o->in2, t1); > - tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_BEUQ); > } > return DISAS_NEXT; > } > @@ -3080,7 +3080,7 @@ static DisasJumpType op_lpq(DisasContext *s, DisasOps *o) > { > o->out_128 = tcg_temp_new_i128(); > tcg_gen_qemu_ld_i128(o->out_128, o->in2, get_mem_index(s), > - MO_TE | MO_128 | MO_ALIGN); > + MO_BE | MO_128 | MO_ALIGN); > return DISAS_NEXT; > } > > @@ -3896,15 +3896,15 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps *o) > a = get_address(s, 0, get_field(s, b2), get_field(s, d2)); > switch (s->insn->data) { > case 1: /* STOCG */ > - tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEUQ); > break; > case 0: /* STOC */ > - tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEUL); > break; > case 2: /* STOCFH */ > h = tcg_temp_new_i64(); > tcg_gen_shri_i64(h, regs[r1], 32); > - tcg_gen_qemu_st_i64(h, a, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_st_i64(h, a, get_mem_index(s), MO_BEUL); > break; > default: > g_assert_not_reached(); > @@ -4023,7 +4023,7 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOps *o) > gen_addi_and_wrap_i64(s, o->addr1, regs[r3], 0); > > /* load the third operand into r3 before modifying anything */ > - tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_BEUQ); > > /* subtract CPU timer from first operand and store in GR0 */ > gen_helper_stpt(tmp, tcg_env); > @@ -4101,9 +4101,9 @@ static DisasJumpType op_stcke(DisasContext *s, DisasOps *o) > tcg_gen_shri_i64(c1, c1, 8); > tcg_gen_ori_i64(c2, c2, 0x10000); > tcg_gen_or_i64(c2, c2, todpr); > - tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_BEUQ); > tcg_gen_addi_i64(o->in2, o->in2, 8); > - tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_BEUQ); > /* ??? We don't implement clock states. */ > gen_op_movi_cc(s, 0); > return DISAS_NEXT; > @@ -4361,21 +4361,21 @@ static DisasJumpType op_st8(DisasContext *s, DisasOps *o) > > static DisasJumpType op_st16(DisasContext *s, DisasOps *o) > { > - tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_TEUW); > + tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_BEUW); > return DISAS_NEXT; > } > > static DisasJumpType op_st32(DisasContext *s, DisasOps *o) > { > tcg_gen_qemu_st_tl(o->in1, o->in2, get_mem_index(s), > - MO_TEUL | s->insn->data); > + MO_BEUL | s->insn->data); > return DISAS_NEXT; > } > > static DisasJumpType op_st64(DisasContext *s, DisasOps *o) > { > tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), > - MO_TEUQ | s->insn->data); > + MO_BEUQ | s->insn->data); > return DISAS_NEXT; > } > > @@ -4399,7 +4399,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o) > case 0xf: > /* Effectively a 32-bit store. */ > tcg_gen_shri_i64(tmp, o->in1, pos); > - tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUL); > break; > > case 0xc: > @@ -4407,7 +4407,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o) > case 0x3: > /* Effectively a 16-bit store. */ > tcg_gen_shri_i64(tmp, o->in1, pos); > - tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUW); > + tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUW); > break; > > case 0x8: > @@ -4445,7 +4445,7 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o) > > while (1) { > tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), > - size == 8 ? MO_TEUQ : MO_TEUL); > + size == 8 ? MO_BEUQ : MO_BEUL); > if (r1 == r3) { > break; > } > @@ -4466,7 +4466,7 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o) > > while (1) { > tcg_gen_shl_i64(t, regs[r1], t32); > - tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_BEUL); > if (r1 == r3) { > break; > } > @@ -4482,7 +4482,7 @@ static DisasJumpType op_stpq(DisasContext *s, DisasOps *o) > > tcg_gen_concat_i64_i128(t16, o->out2, o->out); > tcg_gen_qemu_st_i128(t16, o->in2, get_mem_index(s), > - MO_TE | MO_128 | MO_ALIGN); > + MO_BE | MO_128 | MO_ALIGN); > return DISAS_NEXT; > } > > @@ -5284,49 +5284,49 @@ static void wout_m1_8(DisasContext *s, DisasOps *o) > > static void wout_m1_16(DisasContext *s, DisasOps *o) > { > - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUW); > + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUW); > } > #define SPEC_wout_m1_16 0 > > #ifndef CONFIG_USER_ONLY > static void wout_m1_16a(DisasContext *s, DisasOps *o) > { > - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUW | MO_ALIGN); > + tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUW | MO_ALIGN); > } > #define SPEC_wout_m1_16a 0 > #endif > > static void wout_m1_32(DisasContext *s, DisasOps *o) > { > - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUL); > } > #define SPEC_wout_m1_32 0 > > #ifndef CONFIG_USER_ONLY > static void wout_m1_32a(DisasContext *s, DisasOps *o) > { > - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUL | MO_ALIGN); > + tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUL | MO_ALIGN); > } > #define SPEC_wout_m1_32a 0 > #endif > > static void wout_m1_64(DisasContext *s, DisasOps *o) > { > - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUQ); > } > #define SPEC_wout_m1_64 0 > > #ifndef CONFIG_USER_ONLY > static void wout_m1_64a(DisasContext *s, DisasOps *o) > { > - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ | MO_ALIGN); > + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUQ | MO_ALIGN); > } > #define SPEC_wout_m1_64a 0 > #endif > > static void wout_m2_32(DisasContext *s, DisasOps *o) > { > - tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_BEUL); > } > #define SPEC_wout_m2_32 0 > > @@ -5529,7 +5529,7 @@ static void in1_m1_16s(DisasContext *s, DisasOps *o) > { > in1_la1(s, o); > o->in1 = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESW); > + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BESW); > } > #define SPEC_in1_m1_16s 0 > > @@ -5537,7 +5537,7 @@ static void in1_m1_16u(DisasContext *s, DisasOps *o) > { > in1_la1(s, o); > o->in1 = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUW); > + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUW); > } > #define SPEC_in1_m1_16u 0 > > @@ -5545,7 +5545,7 @@ static void in1_m1_32s(DisasContext *s, DisasOps *o) > { > in1_la1(s, o); > o->in1 = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESL); > + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BESL); > } > #define SPEC_in1_m1_32s 0 > > @@ -5553,7 +5553,7 @@ static void in1_m1_32u(DisasContext *s, DisasOps *o) > { > in1_la1(s, o); > o->in1 = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUL); > } > #define SPEC_in1_m1_32u 0 > > @@ -5561,7 +5561,7 @@ static void in1_m1_64(DisasContext *s, DisasOps *o) > { > in1_la1(s, o); > o->in1 = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUQ); > } > #define SPEC_in1_m1_64 0 > > @@ -5787,28 +5787,28 @@ static void in2_m2_8u(DisasContext *s, DisasOps *o) > static void in2_m2_16s(DisasContext *s, DisasOps *o) > { > in2_a2(s, o); > - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESW); > + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESW); > } > #define SPEC_in2_m2_16s 0 > > static void in2_m2_16u(DisasContext *s, DisasOps *o) > { > in2_a2(s, o); > - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUW); > + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUW); > } > #define SPEC_in2_m2_16u 0 > > static void in2_m2_32s(DisasContext *s, DisasOps *o) > { > in2_a2(s, o); > - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESL); > + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESL); > } > #define SPEC_in2_m2_32s 0 > > static void in2_m2_32u(DisasContext *s, DisasOps *o) > { > in2_a2(s, o); > - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUL); > + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUL); > } > #define SPEC_in2_m2_32u 0 > > @@ -5816,7 +5816,7 @@ static void in2_m2_32u(DisasContext *s, DisasOps *o) > static void in2_m2_32ua(DisasContext *s, DisasOps *o) > { > in2_a2(s, o); > - tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_TEUL | MO_ALIGN); > + tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_BEUL | MO_ALIGN); > } > #define SPEC_in2_m2_32ua 0 > #endif > @@ -5824,14 +5824,14 @@ static void in2_m2_32ua(DisasContext *s, DisasOps *o) > static void in2_m2_64(DisasContext *s, DisasOps *o) > { > in2_a2(s, o); > - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUQ); > } > #define SPEC_in2_m2_64 0 > > static void in2_m2_64w(DisasContext *s, DisasOps *o) > { > in2_a2(s, o); > - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUQ); > gen_addi_and_wrap_i64(s, o->in2, o->in2, 0); > } > #define SPEC_in2_m2_64w 0 > @@ -5840,7 +5840,7 @@ static void in2_m2_64w(DisasContext *s, DisasOps *o) > static void in2_m2_64a(DisasContext *s, DisasOps *o) > { > in2_a2(s, o); > - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN); > + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUQ | MO_ALIGN); > } > #define SPEC_in2_m2_64a 0 > #endif > @@ -5848,14 +5848,14 @@ static void in2_m2_64a(DisasContext *s, DisasOps *o) > static void in2_mri2_16s(DisasContext *s, DisasOps *o) > { > o->in2 = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TESW); > + tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_BESW); > } > #define SPEC_in2_mri2_16s 0 > > static void in2_mri2_16u(DisasContext *s, DisasOps *o) > { > o->in2 = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TEUW); > + tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_BEUW); > } > #define SPEC_in2_mri2_16u 0 > > @@ -5863,7 +5863,7 @@ static void in2_mri2_32s(DisasContext *s, DisasOps *o) > { > o->in2 = tcg_temp_new_i64(); > tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), > - MO_TESL | MO_ALIGN); > + MO_BESL | MO_ALIGN); > } > #define SPEC_in2_mri2_32s 0 > > @@ -5871,7 +5871,7 @@ static void in2_mri2_32u(DisasContext *s, DisasOps *o) > { > o->in2 = tcg_temp_new_i64(); > tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), > - MO_TEUL | MO_ALIGN); > + MO_BEUL | MO_ALIGN); > } > #define SPEC_in2_mri2_32u 0 > > @@ -5879,7 +5879,7 @@ static void in2_mri2_64(DisasContext *s, DisasOps *o) > { > o->in2 = tcg_temp_new_i64(); > tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), > - MO_TEUQ | MO_ALIGN); > + MO_BEUQ | MO_ALIGN); > } > #define SPEC_in2_mri2_64 0 > > diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/translate_vx.c.inc > index f3b4b48ab7b..b53e9e52639 100644 > --- a/target/s390x/tcg/translate_vx.c.inc > +++ b/target/s390x/tcg/translate_vx.c.inc > @@ -331,7 +331,7 @@ static DisasJumpType op_vge(DisasContext *s, DisasOps *o) > tcg_gen_add_i64(o->addr1, o->addr1, tmp); > gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0); > > - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); > + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); > write_vec_element_i64(tmp, get_field(s, v1), enr, es); > return DISAS_NEXT; > } > @@ -402,9 +402,9 @@ static DisasJumpType op_vl(DisasContext *s, DisasOps *o) > TCGv_i64 t0 = tcg_temp_new_i64(); > TCGv_i64 t1 = tcg_temp_new_i64(); > > - tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_BEUQ); > gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); > - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); > write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); > write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); > return DISAS_NEXT; > @@ -427,7 +427,7 @@ static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o) > } > > tmp = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); > + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); > gen_gvec_dup_i64(es, get_field(s, v1), tmp); > return DISAS_NEXT; > } > @@ -561,7 +561,7 @@ static DisasJumpType op_vle(DisasContext *s, DisasOps *o) > } > > tmp = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); > + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); > write_vec_element_i64(tmp, get_field(s, v1), enr, es); > return DISAS_NEXT; > } > @@ -595,9 +595,9 @@ static DisasJumpType op_vler(DisasContext *s, DisasOps *o) > TCGv_i64 t1 = tcg_temp_new_i64(); > > /* Begin with the two doublewords swapped... */ > - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); > gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); > - tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_BEUQ); > > /* ... then swap smaller elements within the doublewords as required. */ > switch (es) { > @@ -693,7 +693,7 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o) > } > > t = tcg_temp_new_i64(); > - tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es); > + tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_BE | es); > gen_gvec_dup_imm(es, get_field(s, v1), 0); > write_vec_element_i64(t, get_field(s, v1), enr, es); > return DISAS_NEXT; > @@ -717,16 +717,16 @@ static DisasJumpType op_vlm(DisasContext *s, DisasOps *o) > t0 = tcg_temp_new_i64(); > t1 = tcg_temp_new_i64(); > gen_addi_and_wrap_i64(s, t0, o->addr1, (v3 - v1) * 16 + 8); > - tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_BEUQ); > > for (;; v1++) { > - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); > write_vec_element_i64(t1, v1, 0, ES_64); > if (v1 == v3) { > break; > } > gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); > - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); > write_vec_element_i64(t1, v1, 1, ES_64); > gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); > } > @@ -1009,7 +1009,7 @@ static DisasJumpType op_vsce(DisasContext *s, DisasOps *o) > gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0); > > read_vec_element_i64(tmp, get_field(s, v1), enr, es); > - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); > + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); > return DISAS_NEXT; > } > > @@ -1063,10 +1063,10 @@ static DisasJumpType op_vst(DisasContext *s, DisasOps *o) > > tmp = tcg_temp_new_i64(); > read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); > - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); > gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); > read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); > - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); > return DISAS_NEXT; > } > > @@ -1154,7 +1154,7 @@ static DisasJumpType op_vste(DisasContext *s, DisasOps *o) > > tmp = tcg_temp_new_i64(); > read_vec_element_i64(tmp, get_field(s, v1), enr, es); > - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); > + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); > return DISAS_NEXT; > } > > @@ -1193,9 +1193,9 @@ static DisasJumpType op_vster(DisasContext *s, DisasOps *o) > g_assert_not_reached(); > } > > - tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_BEUQ); > gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); > - tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); > return DISAS_NEXT; > } > > @@ -1217,10 +1217,10 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOps *o) > tmp = tcg_temp_new_i64(); > for (;; v1++) { > read_vec_element_i64(tmp, v1, 0, ES_64); > - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); > gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); > read_vec_element_i64(tmp, v1, 1, ES_64); > - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); > + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); > if (v1 == v3) { > break; > } > -- > 2.52.0 > ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 5/8] target/s390x: Inline cpu_ld{uw, l}_code() calls in EX opcode helper 2025-12-24 16:20 [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Philippe Mathieu-Daudé ` (3 preceding siblings ...) 2025-12-24 16:20 ` [PATCH 4/8] target/s390x: Replace MO_TE -> MO_BE Philippe Mathieu-Daudé @ 2025-12-24 16:20 ` Philippe Mathieu-Daudé 2025-12-29 11:08 ` Manos Pitsidianakis 2025-12-24 16:20 ` [PATCH 6/8] target/s390x: Use big-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé ` (4 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Philippe Mathieu-Daudé @ 2025-12-24 16:20 UTC (permalink / raw) To: qemu-devel Cc: qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin, Philippe Mathieu-Daudé In preparation of removing the cpu_lduw_code() and cpu_ldl_code() wrappers, inline them. Since S390x instructions are always stored in big-endian order, replace MO_TE -> MO_BE. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/s390x/tcg/mem_helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 507eb7feac7..ce9ced8275f 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -2430,15 +2430,18 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t r1, uint64_t addr) */ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr) { + CPUState *cs = env_cpu(env); uint64_t insn; uint8_t opc; + MemOpIdx oi; /* EXECUTE targets must be at even addresses. */ if (addr & 1) { tcg_s390_program_interrupt(env, PGM_SPECIFICATION, GETPC()); } - insn = cpu_lduw_code(env, addr); + oi = make_memop_idx(MO_BEUW, cpu_mmu_index(cs, true)); + insn = cpu_ldw_code_mmu(env, addr, oi, 0); opc = insn >> 8; /* Or in the contents of R1[56:63]. */ @@ -2450,10 +2453,11 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr) case 2: break; case 4: - insn |= (uint64_t)cpu_lduw_code(env, addr + 2) << 32; + insn |= (uint64_t)cpu_ldw_code_mmu(env, addr + 2, oi, 0) << 32; break; case 6: - insn |= (uint64_t)(uint32_t)cpu_ldl_code(env, addr + 2) << 16; + oi = make_memop_idx(MO_BEUL, cpu_mmu_index(cs, true)); + insn |= (uint64_t)(uint32_t)cpu_ldl_code_mmu(env, addr + 2, oi, 0) << 16; break; default: g_assert_not_reached(); -- 2.52.0 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 5/8] target/s390x: Inline cpu_ld{uw, l}_code() calls in EX opcode helper 2025-12-24 16:20 ` [PATCH 5/8] target/s390x: Inline cpu_ld{uw, l}_code() calls in EX opcode helper Philippe Mathieu-Daudé @ 2025-12-29 11:08 ` Manos Pitsidianakis 0 siblings, 0 replies; 23+ messages in thread From: Manos Pitsidianakis @ 2025-12-29 11:08 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On Wed, Dec 24, 2025 at 6:21 PM Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > In preparation of removing the cpu_lduw_code() and cpu_ldl_code() > wrappers, inline them. > > Since S390x instructions are always stored in big-endian order, > replace MO_TE -> MO_BE. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> > target/s390x/tcg/mem_helper.c | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c > index 507eb7feac7..ce9ced8275f 100644 > --- a/target/s390x/tcg/mem_helper.c > +++ b/target/s390x/tcg/mem_helper.c > @@ -2430,15 +2430,18 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t r1, uint64_t addr) > */ > void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr) > { > + CPUState *cs = env_cpu(env); > uint64_t insn; > uint8_t opc; > + MemOpIdx oi; > > /* EXECUTE targets must be at even addresses. */ > if (addr & 1) { > tcg_s390_program_interrupt(env, PGM_SPECIFICATION, GETPC()); > } > > - insn = cpu_lduw_code(env, addr); > + oi = make_memop_idx(MO_BEUW, cpu_mmu_index(cs, true)); > + insn = cpu_ldw_code_mmu(env, addr, oi, 0); > opc = insn >> 8; > > /* Or in the contents of R1[56:63]. */ > @@ -2450,10 +2453,11 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr) > case 2: > break; > case 4: > - insn |= (uint64_t)cpu_lduw_code(env, addr + 2) << 32; > + insn |= (uint64_t)cpu_ldw_code_mmu(env, addr + 2, oi, 0) << 32; > break; > case 6: > - insn |= (uint64_t)(uint32_t)cpu_ldl_code(env, addr + 2) << 16; > + oi = make_memop_idx(MO_BEUL, cpu_mmu_index(cs, true)); > + insn |= (uint64_t)(uint32_t)cpu_ldl_code_mmu(env, addr + 2, oi, 0) << 16; > break; > default: > g_assert_not_reached(); > -- > 2.52.0 > ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 6/8] target/s390x: Use big-endian variant of cpu_ld/st_data*() 2025-12-24 16:20 [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Philippe Mathieu-Daudé ` (4 preceding siblings ...) 2025-12-24 16:20 ` [PATCH 5/8] target/s390x: Inline cpu_ld{uw, l}_code() calls in EX opcode helper Philippe Mathieu-Daudé @ 2025-12-24 16:20 ` Philippe Mathieu-Daudé 2025-12-29 11:09 ` Manos Pitsidianakis 2025-12-24 16:20 ` [PATCH 7/8] target/s390x: Inline translator_lduw() and translator_ldl() Philippe Mathieu-Daudé ` (3 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Philippe Mathieu-Daudé @ 2025-12-24 16:20 UTC (permalink / raw) To: qemu-devel Cc: qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin, Philippe Mathieu-Daudé We only build the S390x target using big endianness order, therefore the cpu_ld/st_data*() definitions expand to the big endian declarations. Use the explicit big-endian variants. Mechanical change running: $ tgt=s390x; \ end=be; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> --- target/s390x/tcg/mem_helper.c | 48 +++++++++++++++++------------------ target/s390x/tcg/vec_helper.c | 8 +++--- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index ce9ced8275f..8a7d78f9108 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -101,7 +101,7 @@ static inline uint64_t cpu_ldusize_data_ra(CPUS390XState *env, uint64_t addr, case 1: return cpu_ldub_data_ra(env, addr, ra); case 2: - return cpu_lduw_data_ra(env, addr, ra); + return cpu_lduw_be_data_ra(env, addr, ra); default: abort(); } @@ -117,7 +117,7 @@ static inline void cpu_stsize_data_ra(CPUS390XState *env, uint64_t addr, cpu_stb_data_ra(env, addr, value, ra); break; case 2: - cpu_stw_data_ra(env, addr, value, ra); + cpu_stw_be_data_ra(env, addr, value, ra); break; default: abort(); @@ -865,7 +865,7 @@ void HELPER(srstu)(CPUS390XState *env, uint32_t r1, uint32_t r2) env->cc_op = 2; return; } - v = cpu_lduw_data_ra(env, str + len, ra); + v = cpu_lduw_be_data_ra(env, str + len, ra); if (v == c) { /* Character found. Set R1 to the location; R2 is unmodified. */ env->cc_op = 1; @@ -1023,7 +1023,7 @@ void HELPER(lam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } for (i = r1;; i = (i + 1) % 16) { - env->aregs[i] = cpu_ldl_data_ra(env, a2, ra); + env->aregs[i] = cpu_ldl_be_data_ra(env, a2, ra); a2 += 4; if (i == r3) { @@ -1043,7 +1043,7 @@ void HELPER(stam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } for (i = r1;; i = (i + 1) % 16) { - cpu_stl_data_ra(env, a2, env->aregs[i], ra); + cpu_stl_be_data_ra(env, a2, env->aregs[i], ra); a2 += 4; if (i == r3) { @@ -1364,7 +1364,7 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, /* Process full words as available. */ for (len = 0; len + 4 <= max_len; len += 4, src += 4) { - cksm += (uint32_t)cpu_ldl_data_ra(env, src, ra); + cksm += (uint32_t)cpu_ldl_be_data_ra(env, src, ra); } switch (max_len - len) { @@ -1373,11 +1373,11 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, len += 1; break; case 2: - cksm += cpu_lduw_data_ra(env, src, ra) << 16; + cksm += cpu_lduw_be_data_ra(env, src, ra) << 16; len += 2; break; case 3: - cksm += cpu_lduw_data_ra(env, src, ra) << 16; + cksm += cpu_lduw_be_data_ra(env, src, ra) << 16; cksm += cpu_ldub_data_ra(env, src + 2, ra) << 8; len += 3; break; @@ -1956,7 +1956,7 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } for (i = r1;; i = (i + 1) % 16) { - uint64_t val = cpu_ldq_data_ra(env, src, ra); + uint64_t val = cpu_ldq_be_data_ra(env, src, ra); if (env->cregs[i] != val && i >= 9 && i <= 11) { PERchanged = true; } @@ -1993,7 +1993,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } for (i = r1;; i = (i + 1) % 16) { - uint32_t val = cpu_ldl_data_ra(env, src, ra); + uint32_t val = cpu_ldl_be_data_ra(env, src, ra); uint64_t val64 = deposit64(env->cregs[i], 0, 32, val); if ((uint32_t)env->cregs[i] != val && i >= 9 && i <= 11) { PERchanged = true; @@ -2029,7 +2029,7 @@ void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } for (i = r1;; i = (i + 1) % 16) { - cpu_stq_data_ra(env, dest, env->cregs[i], ra); + cpu_stq_be_data_ra(env, dest, env->cregs[i], ra); dest += sizeof(uint64_t); if (i == r3) { @@ -2049,7 +2049,7 @@ void HELPER(stctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } for (i = r1;; i = (i + 1) % 16) { - cpu_stl_data_ra(env, dest, env->cregs[i], ra); + cpu_stl_be_data_ra(env, dest, env->cregs[i], ra); dest += sizeof(uint32_t); if (i == r3) { @@ -2066,7 +2066,7 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64_t real_addr) real_addr = wrap_address(env, real_addr) & TARGET_PAGE_MASK; for (i = 0; i < TARGET_PAGE_SIZE; i += 8) { - cpu_stq_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra); } return 0; @@ -2325,11 +2325,11 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4) for (i = 0; i < entries; i++) { /* addresses are not wrapped in 24/31bit mode but table index is */ raddr = table + ((index + i) & 0x7ff) * sizeof(entry); - entry = cpu_ldq_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra); + entry = cpu_ldq_be_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra); if (!(entry & REGION_ENTRY_I)) { /* we are allowed to not store if already invalid */ entry |= REGION_ENTRY_I; - cpu_stq_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra); } } } @@ -2356,9 +2356,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr, pte_addr += VADDR_PAGE_TX(vaddr) * 8; /* Mark the page table entry as invalid */ - pte = cpu_ldq_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra); + pte = cpu_ldq_be_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra); pte |= PAGE_ENTRY_I; - cpu_stq_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra); /* XXX we exploit the fact that Linux passes the exact virtual address here - it's not obliged to! */ @@ -2700,7 +2700,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen, if (ilen < 2) { return 0; } - s0 = cpu_lduw_data_ra(env, addr, ra); + s0 = cpu_lduw_be_data_ra(env, addr, ra); if ((s0 & 0xfc00) != 0xd800) { /* one word character */ l = 2; @@ -2711,7 +2711,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen, if (ilen < 4) { return 0; } - s1 = cpu_lduw_data_ra(env, addr + 2, ra); + s1 = cpu_lduw_be_data_ra(env, addr + 2, ra); c = extract32(s0, 6, 4) + 1; c = (c << 6) | (s0 & 0x3f); c = (c << 10) | (s1 & 0x3ff); @@ -2735,7 +2735,7 @@ static int decode_utf32(CPUS390XState *env, uint64_t addr, uint64_t ilen, if (ilen < 4) { return 0; } - c = cpu_ldl_data_ra(env, addr, ra); + c = cpu_ldl_be_data_ra(env, addr, ra); if ((c >= 0xd800 && c <= 0xdbff) || c > 0x10ffff) { /* invalid unicode character */ return 2; @@ -2797,7 +2797,7 @@ static int encode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen, if (ilen < 2) { return 1; } - cpu_stw_data_ra(env, addr, c, ra); + cpu_stw_be_data_ra(env, addr, c, ra); *olen = 2; } else { /* two word character */ @@ -2807,8 +2807,8 @@ static int encode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen, d1 = 0xdc00 | extract32(c, 0, 10); d0 = 0xd800 | extract32(c, 10, 6); d0 = deposit32(d0, 6, 4, extract32(c, 16, 5) - 1); - cpu_stw_data_ra(env, addr + 0, d0, ra); - cpu_stw_data_ra(env, addr + 2, d1, ra); + cpu_stw_be_data_ra(env, addr + 0, d0, ra); + cpu_stw_be_data_ra(env, addr + 2, d1, ra); *olen = 4; } @@ -2821,7 +2821,7 @@ static int encode_utf32(CPUS390XState *env, uint64_t addr, uint64_t ilen, if (ilen < 4) { return 1; } - cpu_stl_data_ra(env, addr, c, ra); + cpu_stl_be_data_ra(env, addr, c, ra); *olen = 4; return -1; } diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c index 46ec4a947dd..304745c971b 100644 --- a/target/s390x/tcg/vec_helper.c +++ b/target/s390x/tcg/vec_helper.c @@ -45,9 +45,9 @@ void HELPER(vll)(CPUS390XState *env, void *v1, uint64_t addr, uint64_t bytes) if (likely(bytes >= 16)) { uint64_t t0, t1; - t0 = cpu_ldq_data_ra(env, addr, GETPC()); + t0 = cpu_ldq_be_data_ra(env, addr, GETPC()); addr = wrap_address(env, addr + 8); - t1 = cpu_ldq_data_ra(env, addr, GETPC()); + t1 = cpu_ldq_be_data_ra(env, addr, GETPC()); s390_vec_write_element64(v1, 0, t0); s390_vec_write_element64(v1, 1, t1); } else { @@ -195,9 +195,9 @@ void HELPER(vstl)(CPUS390XState *env, const void *v1, uint64_t addr, probe_write_access(env, addr, MIN(bytes, 16), GETPC()); if (likely(bytes >= 16)) { - cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETPC()); + cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETPC()); addr = wrap_address(env, addr + 8); - cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETPC()); + cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETPC()); } else { int i; -- 2.52.0 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 6/8] target/s390x: Use big-endian variant of cpu_ld/st_data*() 2025-12-24 16:20 ` [PATCH 6/8] target/s390x: Use big-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé @ 2025-12-29 11:09 ` Manos Pitsidianakis 0 siblings, 0 replies; 23+ messages in thread From: Manos Pitsidianakis @ 2025-12-29 11:09 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On Wed, Dec 24, 2025 at 6:21 PM Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > We only build the S390x target using big endianness order, > therefore the cpu_ld/st_data*() definitions expand to the > big endian declarations. Use the explicit big-endian variants. > > Mechanical change running: > > $ tgt=s390x; \ > end=be; \ > for op in data mmuidx_ra; do \ > for ac in uw sw l q; do \ > sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ > $(git grep -l cpu_ target/${tgt}/); \ > done; > for ac in w l q; do \ > sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ > $(git grep -l cpu_ target/${tgt}/); \ > done; > done > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Reviewed-by: Thomas Huth <thuth@redhat.com> > --- Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> > target/s390x/tcg/mem_helper.c | 48 +++++++++++++++++------------------ > target/s390x/tcg/vec_helper.c | 8 +++--- > 2 files changed, 28 insertions(+), 28 deletions(-) > > diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c > index ce9ced8275f..8a7d78f9108 100644 > --- a/target/s390x/tcg/mem_helper.c > +++ b/target/s390x/tcg/mem_helper.c > @@ -101,7 +101,7 @@ static inline uint64_t cpu_ldusize_data_ra(CPUS390XState *env, uint64_t addr, > case 1: > return cpu_ldub_data_ra(env, addr, ra); > case 2: > - return cpu_lduw_data_ra(env, addr, ra); > + return cpu_lduw_be_data_ra(env, addr, ra); > default: > abort(); > } > @@ -117,7 +117,7 @@ static inline void cpu_stsize_data_ra(CPUS390XState *env, uint64_t addr, > cpu_stb_data_ra(env, addr, value, ra); > break; > case 2: > - cpu_stw_data_ra(env, addr, value, ra); > + cpu_stw_be_data_ra(env, addr, value, ra); > break; > default: > abort(); > @@ -865,7 +865,7 @@ void HELPER(srstu)(CPUS390XState *env, uint32_t r1, uint32_t r2) > env->cc_op = 2; > return; > } > - v = cpu_lduw_data_ra(env, str + len, ra); > + v = cpu_lduw_be_data_ra(env, str + len, ra); > if (v == c) { > /* Character found. Set R1 to the location; R2 is unmodified. */ > env->cc_op = 1; > @@ -1023,7 +1023,7 @@ void HELPER(lam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) > } > > for (i = r1;; i = (i + 1) % 16) { > - env->aregs[i] = cpu_ldl_data_ra(env, a2, ra); > + env->aregs[i] = cpu_ldl_be_data_ra(env, a2, ra); > a2 += 4; > > if (i == r3) { > @@ -1043,7 +1043,7 @@ void HELPER(stam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) > } > > for (i = r1;; i = (i + 1) % 16) { > - cpu_stl_data_ra(env, a2, env->aregs[i], ra); > + cpu_stl_be_data_ra(env, a2, env->aregs[i], ra); > a2 += 4; > > if (i == r3) { > @@ -1364,7 +1364,7 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, > > /* Process full words as available. */ > for (len = 0; len + 4 <= max_len; len += 4, src += 4) { > - cksm += (uint32_t)cpu_ldl_data_ra(env, src, ra); > + cksm += (uint32_t)cpu_ldl_be_data_ra(env, src, ra); > } > > switch (max_len - len) { > @@ -1373,11 +1373,11 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, > len += 1; > break; > case 2: > - cksm += cpu_lduw_data_ra(env, src, ra) << 16; > + cksm += cpu_lduw_be_data_ra(env, src, ra) << 16; > len += 2; > break; > case 3: > - cksm += cpu_lduw_data_ra(env, src, ra) << 16; > + cksm += cpu_lduw_be_data_ra(env, src, ra) << 16; > cksm += cpu_ldub_data_ra(env, src + 2, ra) << 8; > len += 3; > break; > @@ -1956,7 +1956,7 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) > } > > for (i = r1;; i = (i + 1) % 16) { > - uint64_t val = cpu_ldq_data_ra(env, src, ra); > + uint64_t val = cpu_ldq_be_data_ra(env, src, ra); > if (env->cregs[i] != val && i >= 9 && i <= 11) { > PERchanged = true; > } > @@ -1993,7 +1993,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) > } > > for (i = r1;; i = (i + 1) % 16) { > - uint32_t val = cpu_ldl_data_ra(env, src, ra); > + uint32_t val = cpu_ldl_be_data_ra(env, src, ra); > uint64_t val64 = deposit64(env->cregs[i], 0, 32, val); > if ((uint32_t)env->cregs[i] != val && i >= 9 && i <= 11) { > PERchanged = true; > @@ -2029,7 +2029,7 @@ void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) > } > > for (i = r1;; i = (i + 1) % 16) { > - cpu_stq_data_ra(env, dest, env->cregs[i], ra); > + cpu_stq_be_data_ra(env, dest, env->cregs[i], ra); > dest += sizeof(uint64_t); > > if (i == r3) { > @@ -2049,7 +2049,7 @@ void HELPER(stctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) > } > > for (i = r1;; i = (i + 1) % 16) { > - cpu_stl_data_ra(env, dest, env->cregs[i], ra); > + cpu_stl_be_data_ra(env, dest, env->cregs[i], ra); > dest += sizeof(uint32_t); > > if (i == r3) { > @@ -2066,7 +2066,7 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64_t real_addr) > real_addr = wrap_address(env, real_addr) & TARGET_PAGE_MASK; > > for (i = 0; i < TARGET_PAGE_SIZE; i += 8) { > - cpu_stq_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra); > + cpu_stq_be_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra); > } > > return 0; > @@ -2325,11 +2325,11 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4) > for (i = 0; i < entries; i++) { > /* addresses are not wrapped in 24/31bit mode but table index is */ > raddr = table + ((index + i) & 0x7ff) * sizeof(entry); > - entry = cpu_ldq_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra); > + entry = cpu_ldq_be_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra); > if (!(entry & REGION_ENTRY_I)) { > /* we are allowed to not store if already invalid */ > entry |= REGION_ENTRY_I; > - cpu_stq_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra); > + cpu_stq_be_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra); > } > } > } > @@ -2356,9 +2356,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr, > pte_addr += VADDR_PAGE_TX(vaddr) * 8; > > /* Mark the page table entry as invalid */ > - pte = cpu_ldq_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra); > + pte = cpu_ldq_be_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra); > pte |= PAGE_ENTRY_I; > - cpu_stq_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra); > + cpu_stq_be_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra); > > /* XXX we exploit the fact that Linux passes the exact virtual > address here - it's not obliged to! */ > @@ -2700,7 +2700,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen, > if (ilen < 2) { > return 0; > } > - s0 = cpu_lduw_data_ra(env, addr, ra); > + s0 = cpu_lduw_be_data_ra(env, addr, ra); > if ((s0 & 0xfc00) != 0xd800) { > /* one word character */ > l = 2; > @@ -2711,7 +2711,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen, > if (ilen < 4) { > return 0; > } > - s1 = cpu_lduw_data_ra(env, addr + 2, ra); > + s1 = cpu_lduw_be_data_ra(env, addr + 2, ra); > c = extract32(s0, 6, 4) + 1; > c = (c << 6) | (s0 & 0x3f); > c = (c << 10) | (s1 & 0x3ff); > @@ -2735,7 +2735,7 @@ static int decode_utf32(CPUS390XState *env, uint64_t addr, uint64_t ilen, > if (ilen < 4) { > return 0; > } > - c = cpu_ldl_data_ra(env, addr, ra); > + c = cpu_ldl_be_data_ra(env, addr, ra); > if ((c >= 0xd800 && c <= 0xdbff) || c > 0x10ffff) { > /* invalid unicode character */ > return 2; > @@ -2797,7 +2797,7 @@ static int encode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen, > if (ilen < 2) { > return 1; > } > - cpu_stw_data_ra(env, addr, c, ra); > + cpu_stw_be_data_ra(env, addr, c, ra); > *olen = 2; > } else { > /* two word character */ > @@ -2807,8 +2807,8 @@ static int encode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen, > d1 = 0xdc00 | extract32(c, 0, 10); > d0 = 0xd800 | extract32(c, 10, 6); > d0 = deposit32(d0, 6, 4, extract32(c, 16, 5) - 1); > - cpu_stw_data_ra(env, addr + 0, d0, ra); > - cpu_stw_data_ra(env, addr + 2, d1, ra); > + cpu_stw_be_data_ra(env, addr + 0, d0, ra); > + cpu_stw_be_data_ra(env, addr + 2, d1, ra); > *olen = 4; > } > > @@ -2821,7 +2821,7 @@ static int encode_utf32(CPUS390XState *env, uint64_t addr, uint64_t ilen, > if (ilen < 4) { > return 1; > } > - cpu_stl_data_ra(env, addr, c, ra); > + cpu_stl_be_data_ra(env, addr, c, ra); > *olen = 4; > return -1; > } > diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c > index 46ec4a947dd..304745c971b 100644 > --- a/target/s390x/tcg/vec_helper.c > +++ b/target/s390x/tcg/vec_helper.c > @@ -45,9 +45,9 @@ void HELPER(vll)(CPUS390XState *env, void *v1, uint64_t addr, uint64_t bytes) > if (likely(bytes >= 16)) { > uint64_t t0, t1; > > - t0 = cpu_ldq_data_ra(env, addr, GETPC()); > + t0 = cpu_ldq_be_data_ra(env, addr, GETPC()); > addr = wrap_address(env, addr + 8); > - t1 = cpu_ldq_data_ra(env, addr, GETPC()); > + t1 = cpu_ldq_be_data_ra(env, addr, GETPC()); > s390_vec_write_element64(v1, 0, t0); > s390_vec_write_element64(v1, 1, t1); > } else { > @@ -195,9 +195,9 @@ void HELPER(vstl)(CPUS390XState *env, const void *v1, uint64_t addr, > probe_write_access(env, addr, MIN(bytes, 16), GETPC()); > > if (likely(bytes >= 16)) { > - cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETPC()); > + cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETPC()); > addr = wrap_address(env, addr + 8); > - cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETPC()); > + cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETPC()); > } else { > int i; > > -- > 2.52.0 > ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 7/8] target/s390x: Inline translator_lduw() and translator_ldl() 2025-12-24 16:20 [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Philippe Mathieu-Daudé ` (5 preceding siblings ...) 2025-12-24 16:20 ` [PATCH 6/8] target/s390x: Use big-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé @ 2025-12-24 16:20 ` Philippe Mathieu-Daudé 2025-12-29 11:11 ` Manos Pitsidianakis 2025-12-24 16:20 ` [PATCH 8/8] configs/targets: Forbid S390x to use legacy native endianness APIs Philippe Mathieu-Daudé ` (2 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Philippe Mathieu-Daudé @ 2025-12-24 16:20 UTC (permalink / raw) To: qemu-devel Cc: qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin, Philippe Mathieu-Daudé translator_lduw() and translator_ldl() are defined in "exec/translator.h" as: 192 static inline uint16_t 193 translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc) 194 { 195 return translator_lduw_end(env, db, pc, MO_TE); 196 } 198 static inline uint32_t 199 translator_ldl(CPUArchState *env, DisasContextBase *db, vaddr pc) 200 { 201 return translator_ldl_end(env, db, pc, MO_TE); 202 } Directly use the inlined form, expanding MO_TE -> MO_BE since we only build the S390x target as big-endian. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/s390x/tcg/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index db2276f1cfc..e38607ee18c 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -365,13 +365,13 @@ static void update_cc_op(DisasContext *s) static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s, uint64_t pc) { - return (uint64_t)translator_lduw(env, &s->base, pc); + return (uint64_t) translator_lduw_end(env, &s->base, pc, MO_BE); } static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s, uint64_t pc) { - return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc); + return (uint64_t)(uint32_t) translator_ldl_end(env, &s->base, pc, MO_BE); } static int get_mem_index(DisasContext *s) @@ -6408,7 +6408,7 @@ static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) static target_ulong get_next_pc(CPUS390XState *env, DisasContext *s, uint64_t pc) { - uint64_t insn = translator_lduw(env, &s->base, pc); + uint64_t insn = translator_lduw_end(env, &s->base, pc, MO_BE); return pc + get_ilen((insn >> 8) & 0xff); } -- 2.52.0 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 7/8] target/s390x: Inline translator_lduw() and translator_ldl() 2025-12-24 16:20 ` [PATCH 7/8] target/s390x: Inline translator_lduw() and translator_ldl() Philippe Mathieu-Daudé @ 2025-12-29 11:11 ` Manos Pitsidianakis 0 siblings, 0 replies; 23+ messages in thread From: Manos Pitsidianakis @ 2025-12-29 11:11 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On Wed, Dec 24, 2025 at 6:21 PM Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > translator_lduw() and translator_ldl() are defined in > "exec/translator.h" as: > > 192 static inline uint16_t > 193 translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc) > 194 { > 195 return translator_lduw_end(env, db, pc, MO_TE); > 196 } > > 198 static inline uint32_t > 199 translator_ldl(CPUArchState *env, DisasContextBase *db, vaddr pc) > 200 { > 201 return translator_ldl_end(env, db, pc, MO_TE); > 202 } > > Directly use the inlined form, expanding MO_TE -> MO_BE > since we only build the S390x target as big-endian. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> > target/s390x/tcg/translate.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c > index db2276f1cfc..e38607ee18c 100644 > --- a/target/s390x/tcg/translate.c > +++ b/target/s390x/tcg/translate.c > @@ -365,13 +365,13 @@ static void update_cc_op(DisasContext *s) > static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s, > uint64_t pc) > { > - return (uint64_t)translator_lduw(env, &s->base, pc); > + return (uint64_t) translator_lduw_end(env, &s->base, pc, MO_BE); > } > > static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s, > uint64_t pc) > { > - return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc); > + return (uint64_t)(uint32_t) translator_ldl_end(env, &s->base, pc, MO_BE); > } > > static int get_mem_index(DisasContext *s) > @@ -6408,7 +6408,7 @@ static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) > static target_ulong get_next_pc(CPUS390XState *env, DisasContext *s, > uint64_t pc) > { > - uint64_t insn = translator_lduw(env, &s->base, pc); > + uint64_t insn = translator_lduw_end(env, &s->base, pc, MO_BE); > > return pc + get_ilen((insn >> 8) & 0xff); > } > -- > 2.52.0 > ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 8/8] configs/targets: Forbid S390x to use legacy native endianness APIs 2025-12-24 16:20 [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Philippe Mathieu-Daudé ` (6 preceding siblings ...) 2025-12-24 16:20 ` [PATCH 7/8] target/s390x: Inline translator_lduw() and translator_ldl() Philippe Mathieu-Daudé @ 2025-12-24 16:20 ` Philippe Mathieu-Daudé 2025-12-29 11:12 ` Manos Pitsidianakis 2026-01-06 20:29 ` Eric Farman 2026-01-05 1:06 ` [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Richard Henderson 2026-01-06 20:26 ` Eric Farman 9 siblings, 2 replies; 23+ messages in thread From: Philippe Mathieu-Daudé @ 2025-12-24 16:20 UTC (permalink / raw) To: qemu-devel Cc: qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin, Philippe Mathieu-Daudé All S390x-related binaries are buildable without a single use of the legacy "native endian" API. Unset the transitional TARGET_USE_LEGACY_NATIVE_ENDIAN_API definition to forbid further uses of the legacy API. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- configs/targets/s390x-linux-user.mak | 1 + configs/targets/s390x-softmmu.mak | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/targets/s390x-linux-user.mak b/configs/targets/s390x-linux-user.mak index 68c2f288724..e3723f5dc54 100644 --- a/configs/targets/s390x-linux-user.mak +++ b/configs/targets/s390x-linux-user.mak @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml TARGET_LONG_BITS=64 +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-softmmu.mak index 76dd5de6584..544657cfe2d 100644 --- a/configs/targets/s390x-softmmu.mak +++ b/configs/targets/s390x-softmmu.mak @@ -3,3 +3,4 @@ TARGET_BIG_ENDIAN=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml TARGET_LONG_BITS=64 +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y -- 2.52.0 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 8/8] configs/targets: Forbid S390x to use legacy native endianness APIs 2025-12-24 16:20 ` [PATCH 8/8] configs/targets: Forbid S390x to use legacy native endianness APIs Philippe Mathieu-Daudé @ 2025-12-29 11:12 ` Manos Pitsidianakis 2026-01-06 20:29 ` Eric Farman 1 sibling, 0 replies; 23+ messages in thread From: Manos Pitsidianakis @ 2025-12-29 11:12 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On Wed, Dec 24, 2025 at 6:21 PM Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > All S390x-related binaries are buildable without a single use > of the legacy "native endian" API. Unset the transitional > TARGET_USE_LEGACY_NATIVE_ENDIAN_API definition to forbid > further uses of the legacy API. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> > configs/targets/s390x-linux-user.mak | 1 + > configs/targets/s390x-softmmu.mak | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/configs/targets/s390x-linux-user.mak b/configs/targets/s390x-linux-user.mak > index 68c2f288724..e3723f5dc54 100644 > --- a/configs/targets/s390x-linux-user.mak > +++ b/configs/targets/s390x-linux-user.mak > @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl > TARGET_BIG_ENDIAN=y > TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml > TARGET_LONG_BITS=64 > +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y > diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-softmmu.mak > index 76dd5de6584..544657cfe2d 100644 > --- a/configs/targets/s390x-softmmu.mak > +++ b/configs/targets/s390x-softmmu.mak > @@ -3,3 +3,4 @@ TARGET_BIG_ENDIAN=y > TARGET_KVM_HAVE_GUEST_DEBUG=y > TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml > TARGET_LONG_BITS=64 > +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y > -- > 2.52.0 > ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 8/8] configs/targets: Forbid S390x to use legacy native endianness APIs 2025-12-24 16:20 ` [PATCH 8/8] configs/targets: Forbid S390x to use legacy native endianness APIs Philippe Mathieu-Daudé 2025-12-29 11:12 ` Manos Pitsidianakis @ 2026-01-06 20:29 ` Eric Farman 2026-01-07 5:11 ` Thomas Huth 1 sibling, 1 reply; 23+ messages in thread From: Eric Farman @ 2026-01-06 20:29 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: qemu-s390x, Christian Borntraeger, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On Wed, 2025-12-24 at 17:20 +0100, Philippe Mathieu-Daudé wrote: > All S390x-related binaries are buildable without a single use > of the legacy "native endian" API. Unset the transitional > TARGET_USE_LEGACY_NATIVE_ENDIAN_API definition to forbid > further uses of the legacy API. One nit is that this text confuses me, because the code below sets TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API rather than unsetting TARGET_USE_LEGACY_NATIVE_ENDIAN_API. End goal seems the same though. Thanks, Eric > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > configs/targets/s390x-linux-user.mak | 1 + > configs/targets/s390x-softmmu.mak | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/configs/targets/s390x-linux-user.mak b/configs/targets/s390x-linux-user.mak > index 68c2f288724..e3723f5dc54 100644 > --- a/configs/targets/s390x-linux-user.mak > +++ b/configs/targets/s390x-linux-user.mak > @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl > TARGET_BIG_ENDIAN=y > TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml > TARGET_LONG_BITS=64 > +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y > diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-softmmu.mak > index 76dd5de6584..544657cfe2d 100644 > --- a/configs/targets/s390x-softmmu.mak > +++ b/configs/targets/s390x-softmmu.mak > @@ -3,3 +3,4 @@ TARGET_BIG_ENDIAN=y > TARGET_KVM_HAVE_GUEST_DEBUG=y > TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml > TARGET_LONG_BITS=64 > +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 8/8] configs/targets: Forbid S390x to use legacy native endianness APIs 2026-01-06 20:29 ` Eric Farman @ 2026-01-07 5:11 ` Thomas Huth 2026-01-07 8:11 ` Philippe Mathieu-Daudé 0 siblings, 1 reply; 23+ messages in thread From: Thomas Huth @ 2026-01-07 5:11 UTC (permalink / raw) To: Eric Farman, Philippe Mathieu-Daudé, qemu-devel Cc: qemu-s390x, Christian Borntraeger, Pierrick Bouvier, David Hildenbrand, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On 06/01/2026 21.29, Eric Farman wrote: > On Wed, 2025-12-24 at 17:20 +0100, Philippe Mathieu-Daudé wrote: >> All S390x-related binaries are buildable without a single use >> of the legacy "native endian" API. Unset the transitional >> TARGET_USE_LEGACY_NATIVE_ENDIAN_API definition to forbid >> further uses of the legacy API. > > One nit is that this text confuses me, because the code below sets > TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API rather than unsetting TARGET_USE_LEGACY_NATIVE_ENDIAN_API. > > End goal seems the same though. By the way, both definitions seem to be completely unused in QEMU currently, so this patch is currently for no real use yet? Unless some more infrastructure gets merged that consumes this setting, I think we should rather not merge this patch yet. I'll queue patches 1-7 for my next pull request. Thomas ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 8/8] configs/targets: Forbid S390x to use legacy native endianness APIs 2026-01-07 5:11 ` Thomas Huth @ 2026-01-07 8:11 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 23+ messages in thread From: Philippe Mathieu-Daudé @ 2026-01-07 8:11 UTC (permalink / raw) To: Thomas Huth, Eric Farman, qemu-devel Cc: qemu-s390x, Christian Borntraeger, Pierrick Bouvier, David Hildenbrand, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On 7/1/26 06:11, Thomas Huth wrote: > On 06/01/2026 21.29, Eric Farman wrote: >> On Wed, 2025-12-24 at 17:20 +0100, Philippe Mathieu-Daudé wrote: >>> All S390x-related binaries are buildable without a single use >>> of the legacy "native endian" API. Unset the transitional >>> TARGET_USE_LEGACY_NATIVE_ENDIAN_API definition to forbid >>> further uses of the legacy API. >> >> One nit is that this text confuses me, because the code below sets >> TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API rather than unsetting >> TARGET_USE_LEGACY_NATIVE_ENDIAN_API. Oops, I'll reword. >> End goal seems the same though. > By the way, both definitions seem to be completely unused in QEMU > currently, so this patch is currently for no real use yet? Unless some > more infrastructure gets merged that consumes this setting, I think we > should rather not merge this patch yet. Oh. I usually add 'Based-on' in my cover letters when there are dependencies between series. I did that in the previous version (which was not covering s390x) but Pierrick told me this was not practical to apply and test, and suggested to share a branch/tag with all series; which is what I did (sharing a tag, https://gitlab.com/philmd/qemu/-/tags/endian_s390x-v1), however I failed to precise the other series. In particular, this is based on: https://lore.kernel.org/qemu-devel/20251224152210.87880-1-philmd@linaro.org/ See these patches: system: Allow restricting the legacy ld/st_phys() 'native-endian' API system: Allow restricting the legacy ld/st_he() 'native-endian' API system: Allow restricting legacy address_space_ldst() native-endian API system: Allow restricting the legacy cpu_ld/st() 'native-endian' API system: Allow restricting the legacy translator_ld() 'native-endian' API system: Allow restricting the legacy tswap() 'native-endian' API system: Allow restricting the legacy MO_TE* 'native-endian' definitions system: Allow restricting the legacy DEVICE_NATIVE_ENDIAN definition > I'll queue patches 1-7 for my > next pull request. Thanks! ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API 2025-12-24 16:20 [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Philippe Mathieu-Daudé ` (7 preceding siblings ...) 2025-12-24 16:20 ` [PATCH 8/8] configs/targets: Forbid S390x to use legacy native endianness APIs Philippe Mathieu-Daudé @ 2026-01-05 1:06 ` Richard Henderson 2026-01-06 20:26 ` Eric Farman 9 siblings, 0 replies; 23+ messages in thread From: Richard Henderson @ 2026-01-05 1:06 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: qemu-s390x, Christian Borntraeger, Eric Farman, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On 12/25/25 03:20, Philippe Mathieu-Daudé wrote: > S390x is big-endian. Use the explicit 'big' > endianness instead of the 'native' one. > Forbid further uses of legacy APIs. > > tag:https://gitlab.com/philmd/qemu/-/tags/endian_s390x-v1 > CI:https://gitlab.com/philmd/qemu/-/pipelines/2231223066 > > Philippe Mathieu-Daudé (8): > hw/s390x: Use explicit big-endian LD/ST API > target/s390x: Use explicit big-endian LD/ST API > target/s390x: Replace gdb_get_regl() -> gdb_get_reg64() > target/s390x: Replace MO_TE -> MO_BE > target/s390x: Inline cpu_ld{uw,l}_code() calls in EX opcode helper > target/s390x: Use big-endian variant of cpu_ld/st_data*() > target/s390x: Inline translator_lduw() and translator_ldl() > configs/targets: Forbid S390x to use legacy native endianness APIs Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API 2025-12-24 16:20 [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Philippe Mathieu-Daudé ` (8 preceding siblings ...) 2026-01-05 1:06 ` [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Richard Henderson @ 2026-01-06 20:26 ` Eric Farman 9 siblings, 0 replies; 23+ messages in thread From: Eric Farman @ 2026-01-06 20:26 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: qemu-s390x, Christian Borntraeger, Pierrick Bouvier, David Hildenbrand, Thomas Huth, Ilya Leoshkevich, Manos Pitsidianakis, Halil Pasic, Richard Henderson, Laurent Vivier, Matthew Rosato, Farhan Ali, Cornelia Huck, Anton Johansson, Michael S. Tsirkin On Wed, 2025-12-24 at 17:20 +0100, Philippe Mathieu-Daudé wrote: > S390x is big-endian. Use the explicit 'big' > endianness instead of the 'native' one. > Forbid further uses of legacy APIs. > > tag: https://gitlab.com/philmd/qemu/-/tags/endian_s390x-v1 > CI: https://gitlab.com/philmd/qemu/-/pipelines/2231223066 > > Philippe Mathieu-Daudé (8): > hw/s390x: Use explicit big-endian LD/ST API > target/s390x: Use explicit big-endian LD/ST API > target/s390x: Replace gdb_get_regl() -> gdb_get_reg64() > target/s390x: Replace MO_TE -> MO_BE > target/s390x: Inline cpu_ld{uw,l}_code() calls in EX opcode helper > target/s390x: Use big-endian variant of cpu_ld/st_data*() > target/s390x: Inline translator_lduw() and translator_ldl() > configs/targets: Forbid S390x to use legacy native endianness APIs For the series: Reviewed-by: Eric Farman <farman@linux.ibm.com> > > configs/targets/s390x-linux-user.mak | 1 + > configs/targets/s390x-softmmu.mak | 1 + > target/s390x/tcg/insn-data.h.inc | 54 +++++----- > hw/s390x/css.c | 24 ++--- > hw/s390x/s390-pci-bus.c | 4 +- > hw/s390x/virtio-ccw.c | 24 ++--- > target/s390x/cpu-system.c | 2 +- > target/s390x/gdbstub.c | 26 ++--- > target/s390x/kvm/kvm.c | 8 +- > target/s390x/mmu_helper.c | 3 +- > target/s390x/tcg/excp_helper.c | 16 +-- > target/s390x/tcg/mem_helper.c | 71 +++++++------ > target/s390x/tcg/translate.c | 144 +++++++++++++-------------- > target/s390x/tcg/vec_helper.c | 8 +- > target/s390x/tcg/translate_vx.c.inc | 38 +++---- > 15 files changed, 215 insertions(+), 209 deletions(-) ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2026-01-07 8:12 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-24 16:20 [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Philippe Mathieu-Daudé
2025-12-24 16:20 ` [PATCH 1/8] hw/s390x: " Philippe Mathieu-Daudé
2025-12-24 19:55 ` Halil Pasic
2025-12-29 11:27 ` Manos Pitsidianakis
2025-12-24 16:20 ` [PATCH 2/8] target/s390x: " Philippe Mathieu-Daudé
2025-12-29 11:03 ` Manos Pitsidianakis
2025-12-24 16:20 ` [PATCH 3/8] target/s390x: Replace gdb_get_regl() -> gdb_get_reg64() Philippe Mathieu-Daudé
2025-12-29 11:03 ` Manos Pitsidianakis
2025-12-24 16:20 ` [PATCH 4/8] target/s390x: Replace MO_TE -> MO_BE Philippe Mathieu-Daudé
2025-12-29 11:04 ` Manos Pitsidianakis
2025-12-24 16:20 ` [PATCH 5/8] target/s390x: Inline cpu_ld{uw, l}_code() calls in EX opcode helper Philippe Mathieu-Daudé
2025-12-29 11:08 ` Manos Pitsidianakis
2025-12-24 16:20 ` [PATCH 6/8] target/s390x: Use big-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé
2025-12-29 11:09 ` Manos Pitsidianakis
2025-12-24 16:20 ` [PATCH 7/8] target/s390x: Inline translator_lduw() and translator_ldl() Philippe Mathieu-Daudé
2025-12-29 11:11 ` Manos Pitsidianakis
2025-12-24 16:20 ` [PATCH 8/8] configs/targets: Forbid S390x to use legacy native endianness APIs Philippe Mathieu-Daudé
2025-12-29 11:12 ` Manos Pitsidianakis
2026-01-06 20:29 ` Eric Farman
2026-01-07 5:11 ` Thomas Huth
2026-01-07 8:11 ` Philippe Mathieu-Daudé
2026-01-05 1:06 ` [PATCH 0/8] target/s390x: Use explicit big-endian LD/ST API Richard Henderson
2026-01-06 20:26 ` Eric Farman
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.