From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Sascha Bischoff <Sascha.Bischoff@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>, nd <nd@arm.com>,
"maz@kernel.org" <maz@kernel.org>,
"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
Joey Gouly <Joey.Gouly@arm.com>,
Suzuki Poulose <Suzuki.Poulose@arm.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
Timothy Hayes <Timothy.Hayes@arm.com>
Subject: Re: [PATCH v2 36/36] KVM: arm64: gic-v5: Communicate userspace-drivable PPIs via a UAPI
Date: Wed, 7 Jan 2026 16:51:10 +0000 [thread overview]
Message-ID: <20260107165110.0000638d@huawei.com> (raw)
In-Reply-To: <20251219155222.1383109-37-sascha.bischoff@arm.com>
On Fri, 19 Dec 2025 15:52:48 +0000
Sascha Bischoff <Sascha.Bischoff@arm.com> wrote:
> GICv5 systems will likely not support the full set of PPIs. The
> presence of any virtual PPI is tied to the presence of the physical
> PPI. Therefore, the available PPIs will be limited by the physical
> host. Userspace cannot drive any PPIs that are not implemented.
>
> Moreover, it is not desirable to expose all PPIs to the guest in the
> first place, even if they are supported in hardware. Some devices,
> such as the arch timer, are implemented in KVM, and hence those PPIs
> shouldn't be driven by userspace, either.
>
> Provided a new UAPI:
> KVM_DEV_ARM_VGIC_GRP_CTRL => KVM_DEV_ARM_VGIC_USERPSPACE_PPIs
>
> This allows userspace to query which PPIs it is able to drive via
> KVM_IRQ_LINE.
>
> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
A couple of trivial comments on this patch.
Overall, to me as a definite non expert in kvm GIC emulation this
series looks to be in a pretty good state.
Thanks,
Jonathan
> ---
> .../virt/kvm/devices/arm-vgic-v5.rst | 13 ++++++++++
> arch/arm64/include/uapi/asm/kvm.h | 1 +
> arch/arm64/kvm/vgic/vgic-kvm-device.c | 25 +++++++++++++++++++
> arch/arm64/kvm/vgic/vgic-v5.c | 8 ++++++
> include/kvm/arm_vgic.h | 5 ++++
> include/linux/irqchip/arm-gic-v5.h | 4 +++
> tools/arch/arm64/include/uapi/asm/kvm.h | 1 +
> 7 files changed, 57 insertions(+)
>
> diff --git a/Documentation/virt/kvm/devices/arm-vgic-v5.rst b/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> index 9904cb888277d..d9f2917b609c5 100644
> --- a/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> +++ b/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> @@ -25,6 +25,19 @@ Groups:
> request the initialization of the VGIC, no additional parameter in
> kvm_device_attr.addr. Must be called after all VCPUs have been created.
>
> + KVM_DEV_ARM_VGIC_USERPSPACE_PPIs
> + request the mask of userspace-drivable PPIs. Only a subset of the PPIs can
> + be directly driven from userspace with GICv5, and the returned mask
> + informs userspace of which it is allowed to drive via KVM_IRQ_LINE.
> +
> + Userspace must allocate and point to __u64[2] with of data in
with of?
> + kvm_device_attr.addr. When this call returns, the provided memory will be
> + populated with the userspace PPI mask. The lower __u64 contains the mask
> + for the lower 64 PPIS, with the remaining 64 being in the second __u64.
> +
> + This is a read-only attribute, and cannot be set. Attempts to set it are
> + rejected.
> +
> Errors:
>
> ======= ========================================================
> diff --git a/arch/arm64/kvm/vgic/vgic-kvm-device.c b/arch/arm64/kvm/vgic/vgic-kvm-device.c
> index 78903182bba08..360c78ed4f104 100644
> --- a/arch/arm64/kvm/vgic/vgic-kvm-device.c
> +++ b/arch/arm64/kvm/vgic/vgic-kvm-device.c
> @@ -719,6 +719,25 @@ struct kvm_device_ops kvm_arm_vgic_v3_ops = {
> .has_attr = vgic_v3_has_attr,
> };
>
> +static int vgic_v5_get_userspace_ppis(struct kvm_device *dev,
> + struct kvm_device_attr *attr)
> +{
> + u64 __user *uaddr = (u64 __user *)(long)attr->addr;
> + struct gicv5_vm *gicv5_vm = &dev->kvm->arch.vgic.gicv5_vm;
> + int i, ret;
> +
> + guard(mutex)(&dev->kvm->arch.config_lock);
> +
> + for (i = 0; i < 2; ++i) {
Can drag declaration of i into loop init.
Also I just noticed the series is rather random wrt to pre or post increment
in cases where it doesn't matter. I'd go with post increment for for loops.
I took a quick look at a random file in this directory and that's what is used there.
> + ret = put_user(gicv5_vm->userspace_ppis[i], uaddr);
> + if (ret)
> + return ret;
> + uaddr++;
> + }
> +
> + return 0;
> +}
> diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
> index bf72982d6a2e8..04300926683b6 100644
> --- a/arch/arm64/kvm/vgic/vgic-v5.c
> +++ b/arch/arm64/kvm/vgic/vgic-v5.c
> @@ -122,6 +122,14 @@ int vgic_v5_init(struct kvm *kvm)
> }
> }
>
> + /*
> + * We only allow userspace to drive the SW_PPI, if it is
> + * implemented.
> + */
/* We only allow userspace to drive the SW_PPI, if it is implemented. */
Is under 80 chars (just) so go with that.
> + kvm->arch.vgic.gicv5_vm.userspace_ppis[0] = GICV5_SW_PPI & GICV5_HWIRQ_ID;
> + kvm->arch.vgic.gicv5_vm.userspace_ppis[0] &= ppi_caps->impl_ppi_mask[0];
> + kvm->arch.vgic.gicv5_vm.userspace_ppis[1] = 0;
> +
> return 0;
> }
next prev parent reply other threads:[~2026-01-07 16:51 UTC|newest]
Thread overview: 101+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-19 15:52 [PATCH v2 00/36] KVM: arm64: Introduce vGIC-v5 with PPI support Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 01/36] KVM: arm64: Account for RES1 bits in DECLARE_FEAT_MAP() and co Sascha Bischoff
2026-01-06 17:23 ` Jonathan Cameron
2026-01-08 16:52 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 03/36] arm64/sysreg: Drop ICH_HFGRTR_EL2.ICC_HAPR_EL1 and make RES1 Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 02/36] KVM: arm64: gic-v3: Switch vGIC-v3 to use generated ICH_VMCR_EL2 Sascha Bischoff
2026-01-06 18:00 ` Jonathan Cameron
2026-01-07 10:55 ` Sascha Bischoff
2026-01-09 16:57 ` Sascha Bischoff
2026-01-12 12:41 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 04/36] arm64/sysreg: Add remaining GICv5 ICC_ & ICH_ sysregs for KVM support Sascha Bischoff
2026-01-06 18:28 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 06/36] KVM: arm64: gic-v5: Add ARM_VGIC_V5 device to KVM headers Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 05/36] arm64/sysreg: Add GICR CDNMIA encoding Sascha Bischoff
2026-01-06 18:08 ` Jonathan Cameron
2026-01-07 8:39 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 08/36] KVM: arm64: Introduce kvm_call_hyp_nvhe_res() Sascha Bischoff
2026-01-07 10:30 ` Jonathan Cameron
2026-01-08 9:48 ` Sascha Bischoff
2026-01-08 10:26 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 09/36] KVM: arm64: gic-v5: Detect implemented PPIs on boot Sascha Bischoff
2026-01-06 18:34 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 07/36] KVM: arm64: gic: Introduce interrupt type helpers Sascha Bischoff
2026-01-06 14:51 ` Joey Gouly
2026-01-06 18:43 ` Jonathan Cameron
2026-01-08 9:33 ` Sascha Bischoff
2026-01-08 10:25 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 12/36] KVM: arm64: gic-v5: Add emulation for ICC_IAFFIDR_EL1 accesses Sascha Bischoff
2026-01-07 11:10 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 10/36] KVM: arm64: gic-v5: Sanitize ID_AA64PFR2_EL1.GCIE Sascha Bischoff
2026-01-07 10:58 ` Jonathan Cameron
2026-01-08 9:54 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 11/36] KVM: arm64: gic-v5: Support GICv5 FGTs & FGUs Sascha Bischoff
2026-01-07 11:19 ` Jonathan Cameron
2026-01-08 10:36 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 13/36] KVM: arm64: gic: Set vgic_model before initing private IRQs Sascha Bischoff
2026-01-07 11:24 ` Jonathan Cameron
2026-01-08 13:39 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 14/36] KVM: arm64: gic-v5: Add vgic-v5 save/restore hyp interface Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 17/36] KVM: arm64: gic: Introduce irq_queue and set_pending_state to irq_ops Sascha Bischoff
2026-01-07 12:22 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 16/36] KVM: arm64: gic-v5: Implement direct injection of PPIs Sascha Bischoff
2026-01-07 12:16 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 15/36] KVM: arm64: gic-v5: Implement GICv5 load/put and save/restore Sascha Bischoff
2026-01-07 12:28 ` Jonathan Cameron
2026-01-08 13:40 ` Sascha Bischoff
2026-01-08 16:52 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 20/36] KVM: arm64: gic-v5: Init Private IRQs (PPIs) for GICv5 Sascha Bischoff
2026-01-07 15:04 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 19/36] KVM: arm64: gic-v5: Check for pending PPIs Sascha Bischoff
2026-01-07 15:00 ` Jonathan Cameron
2026-01-08 16:23 ` Sascha Bischoff
2026-01-08 16:57 ` Jonathan Cameron
2026-01-08 16:10 ` Joey Gouly
2026-01-08 16:21 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 18/36] KVM: arm64: gic-v5: Implement PPI interrupt injection Sascha Bischoff
2026-01-06 16:06 ` Joey Gouly
2026-01-06 18:04 ` Sascha Bischoff
2026-01-07 12:50 ` Jonathan Cameron
2026-01-08 14:43 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 21/36] KVM: arm64: gic-v5: Finalize GICv5 PPIs and generate mask Sascha Bischoff
2026-01-07 15:08 ` Jonathan Cameron
2026-01-08 16:51 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 22/36] KVM: arm64: gic-v5: Trap and mask guest PPI register accesses Sascha Bischoff
2026-01-07 15:17 ` Jonathan Cameron
2026-01-09 16:59 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 23/36] KVM: arm64: gic-v5: Support GICv5 interrupts with KVM_IRQ_LINE Sascha Bischoff
2026-01-07 15:29 ` Jonathan Cameron
2026-01-08 16:53 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 25/36] KVM: arm64: gic-v5: Reset vcpu state Sascha Bischoff
2026-01-07 15:51 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 24/36] KVM: arm64: gic-v5: Create, init vgic_v5 Sascha Bischoff
2026-01-07 15:49 ` Jonathan Cameron
2026-01-08 16:55 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 26/36] KVM: arm64: gic-v5: Bump arch timer for GICv5 Sascha Bischoff
2026-01-07 16:08 ` Jonathan Cameron
2026-01-09 16:56 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 28/36] KVM: arm64: gic: Hide GICv5 for protected guests Sascha Bischoff
2026-01-07 16:12 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 27/36] KVM: arm64: gic-v5: Mandate architected PPI for PMU emulation on GICv5 Sascha Bischoff
2026-01-06 15:06 ` Joey Gouly
2026-01-07 9:48 ` Sascha Bischoff
2026-01-07 16:11 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 30/36] KVM: arm64: gic-v5: Introduce kvm_arm_vgic_v5_ops and register them Sascha Bischoff
2026-01-07 16:19 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 31/36] KVM: arm64: gic-v5: Set ICH_VCTLR_EL2.En on boot Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 29/36] KVM: arm64: gic-v5: Hide FEAT_GCIE from NV GICv5 guests Sascha Bischoff
2026-01-07 16:13 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 32/36] irqchip/gic-v5: Check if impl is virt capable Sascha Bischoff
2026-01-07 16:21 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 33/36] KVM: arm64: gic-v5: Probe for GICv5 device Sascha Bischoff
2026-01-07 16:25 ` Jonathan Cameron
2026-01-09 15:00 ` Joey Gouly
2025-12-19 15:52 ` [PATCH v2 34/36] Documentation: KVM: Introduce documentation for VGICv5 Sascha Bischoff
2026-01-07 16:27 ` Jonathan Cameron
2025-12-19 15:52 ` [PATCH v2 36/36] KVM: arm64: gic-v5: Communicate userspace-drivable PPIs via a UAPI Sascha Bischoff
2026-01-07 16:51 ` Jonathan Cameron [this message]
2026-01-09 17:00 ` Sascha Bischoff
2025-12-19 15:52 ` [PATCH v2 35/36] KVM: arm64: selftests: Introduce a minimal GICv5 PPI selftest Sascha Bischoff
2026-01-07 16:38 ` Jonathan Cameron
2025-12-19 16:17 ` [PATCH v2 00/36] KVM: arm64: Introduce vGIC-v5 with PPI support Sascha Bischoff
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