* [PATCH 0/2] cnxk: Add HALO support for CN20K mempool @ 2025-12-04 6:51 Nawal Kishor 2025-12-04 6:51 ` [PATCH 1/2] common/cnxk: add support for halos Nawal Kishor 2025-12-04 6:51 ` [PATCH 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor 0 siblings, 2 replies; 18+ messages in thread From: Nawal Kishor @ 2025-12-04 6:51 UTC (permalink / raw) To: dev; +Cc: jerinj, asekhar, Nawal Kishor This patch series introduces HALO support for the CN20K platform. On earlier platforms (CN9K/CN10K), the NPA mempool required separate aura and pool contexts even for a 1:1 aura-to-pool mapping. This led to unnecessary context usage for the most common use case. With CN20K, HALOs allow replacing this 1:1 aura/pool model with a single combined context, reducing context consumption and simplifying mempool management. Patch 1 adds HALO creation support in the ROC common layer. Patch 2 integrates HALO usage into the CN20K mempool driver and adds a new "halo_ena" devarg to enable or disable this feature. Nawal Kishor (2): common/cnxk: add support for halos mempool/cnxk: add halo support in mempool drivers/common/cnxk/hw/npa.h | 81 ++++++ drivers/common/cnxk/roc_idev.c | 25 ++ drivers/common/cnxk/roc_idev.h | 3 + drivers/common/cnxk/roc_idev_priv.h | 1 + drivers/common/cnxk/roc_mbox.h | 6 + drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 46 ++- drivers/common/cnxk/roc_npa.c | 268 ++++++++++++++++-- drivers/common/cnxk/roc_npa.h | 20 +- drivers/common/cnxk/roc_npa_debug.c | 201 ++++++++++++- drivers/common/cnxk/roc_npa_priv.h | 3 + .../common/cnxk/roc_platform_base_symbols.c | 2 + drivers/common/cnxk/roc_sso.c | 35 ++- drivers/common/cnxk/roc_sso.h | 1 + drivers/mempool/cnxk/cn10k_mempool_ops.c | 19 +- drivers/mempool/cnxk/cn20k_mempool_ops.c | 60 ++++ drivers/mempool/cnxk/cn9k_mempool_ops.c | 2 +- drivers/mempool/cnxk/cnxk_mempool.c | 40 ++- drivers/mempool/cnxk/cnxk_mempool.h | 16 +- drivers/mempool/cnxk/cnxk_mempool_ops.c | 11 +- drivers/mempool/cnxk/meson.build | 1 + 21 files changed, 750 insertions(+), 92 deletions(-) create mode 100644 drivers/mempool/cnxk/cn20k_mempool_ops.c -- 2.48.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/2] common/cnxk: add support for halos 2025-12-04 6:51 [PATCH 0/2] cnxk: Add HALO support for CN20K mempool Nawal Kishor @ 2025-12-04 6:51 ` Nawal Kishor 2025-12-05 5:51 ` [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool Nawal Kishor 2025-12-04 6:51 ` [PATCH 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor 1 sibling, 1 reply; 18+ messages in thread From: Nawal Kishor @ 2025-12-04 6:51 UTC (permalink / raw) To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao, Harman Kalra Cc: jerinj, asekhar, Nawal Kishor In cn9k/cn10k NPA mempool creation required the creation of atleast one aura and pool context. Even, if the mapping between aura and pool was 1:1 (i.e, one aura mapped to one pool), separate contexts were required for aura and pool. This wasted the context space and most of common use case for NPA mempool is 1:1 mapping between aura and pool. In cn20k, 1:1 aura pool mapping can now be replaced by using halos. Halos allow the creation of only one context which contains the information required for both aura and pool. This patch adds the support for creation of Halos in ROC. Signed-off-by: Nawal Kishor <nkishor@marvell.com> --- drivers/common/cnxk/hw/npa.h | 81 ++++++ drivers/common/cnxk/roc_idev.c | 25 ++ drivers/common/cnxk/roc_idev.h | 3 + drivers/common/cnxk/roc_idev_priv.h | 1 + drivers/common/cnxk/roc_mbox.h | 6 + drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 46 ++- drivers/common/cnxk/roc_npa.c | 268 ++++++++++++++++-- drivers/common/cnxk/roc_npa.h | 20 +- drivers/common/cnxk/roc_npa_debug.c | 201 ++++++++++++- drivers/common/cnxk/roc_npa_priv.h | 3 + .../common/cnxk/roc_platform_base_symbols.c | 2 + drivers/common/cnxk/roc_sso.c | 35 ++- drivers/common/cnxk/roc_sso.h | 1 + 14 files changed, 630 insertions(+), 63 deletions(-) diff --git a/drivers/common/cnxk/hw/npa.h b/drivers/common/cnxk/hw/npa.h index 4fd1f9a64b..e421c70e01 100644 --- a/drivers/common/cnxk/hw/npa.h +++ b/drivers/common/cnxk/hw/npa.h @@ -118,6 +118,7 @@ #define NPA_AQ_CTYPE_AURA (0x0ull) #define NPA_AQ_CTYPE_POOL (0x1ull) +#define NPA_AQ_CTYPE_HALO (0x2ull) #define NPA_BPINTF_NIX0_RX (0x0ull) #define NPA_BPINTF_NIX1_RX (0x1ull) @@ -456,6 +457,86 @@ struct npa_cn20k_pool_s { uint64_t rsvd_1023_960 : 64; /* W15 */ }; +/* NPA halo context structure [CN20K] */ +struct npa_cn20k_halo_s { + uint64_t stack_base : 64; /* W0 */ + uint64_t ena : 1; /* W1 */ + uint64_t nat_align : 1; + uint64_t reserved_67_66 : 2; + uint64_t stack_caching : 1; + uint64_t reserved_71_69 : 3; + uint64_t aura_drop_ena : 1; + uint64_t reserved_79_73 : 7; + uint64_t aura_drop : 8; + uint64_t buf_offset : 12; + uint64_t reserved_103_100 : 4; + uint64_t buf_size : 12; + uint64_t reserved_119_116 : 4; + uint64_t ref_cnt_prof : 3; + uint64_t reserved_127_123 : 5; + uint64_t stack_max_pages : 32; /* W2 */ + uint64_t stack_pages : 32; + uint64_t bp_0 : 7; /* W3 */ + uint64_t bp_1 : 7; + uint64_t bp_2 : 7; + uint64_t bp_3 : 7; + uint64_t bp_4 : 7; + uint64_t bp_5 : 7; + uint64_t bp_6 : 7; + uint64_t bp_7 : 7; + uint64_t bp_ena_0 : 1; + uint64_t bp_ena_1 : 1; + uint64_t bp_ena_2 : 1; + uint64_t bp_ena_3 : 1; + uint64_t bp_ena_4 : 1; + uint64_t bp_ena_5 : 1; + uint64_t bp_ena_6 : 1; + uint64_t bp_ena_7 : 1; + uint64_t stack_offset : 4; /* W4 */ + uint64_t reserved_263_260 : 4; + uint64_t shift : 6; + uint64_t reserved_271_270 : 2; + uint64_t avg_level : 8; + uint64_t avg_con : 9; + uint64_t fc_ena : 1; + uint64_t fc_stype : 2; + uint64_t fc_hyst_bits : 4; + uint64_t fc_up_crossing : 1; + uint64_t reserved_299_297 : 3; + uint64_t update_time : 16; + uint64_t reserved_319_316 : 4; + uint64_t fc_addr : 64; /* W5 */ + uint64_t ptr_start : 64; /* W6 */ + uint64_t ptr_end : 64; /* W7 */ + uint64_t bpid_0 : 12; /* W8 */ + uint64_t reserved_535_524 : 12; + uint64_t err_int : 8; + uint64_t err_int_ena : 8; + uint64_t thresh_int : 1; + uint64_t thresh_int_ena : 1; + uint64_t thresh_up : 1; + uint64_t reserved_555_555 : 1; + uint64_t thresh_qint_idx : 7; + uint64_t reserved_563_563 : 1; + uint64_t err_qint_idx : 7; + uint64_t reserved_575_571 : 5; + uint64_t thresh : 36; /* W9 */ + uint64_t reserved_615_612 : 4; + uint64_t fc_msh_dst : 11; + uint64_t reserved_630_627 : 4; + uint64_t op_dpc_ena : 1; + uint64_t op_dpc_set : 5; + uint64_t reserved_637_637 : 1; + uint64_t stream_ctx : 1; + uint64_t unified_ctx : 1; + uint64_t reserved_703_640 : 64; /* W10 */ + uint64_t reserved_767_704 : 64; /* W11 */ + uint64_t reserved_831_768 : 64; /* W12 */ + uint64_t reserved_895_832 : 64; /* W13 */ + uint64_t reserved_959_896 : 64; /* W14 */ + uint64_t reserved_1023_960 : 64; /* W15 */ +}; + /* NPA queue interrupt context hardware structure */ struct npa_qint_hw_s { uint32_t count : 22; diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c index 84812f73e0..6aa5b10ee9 100644 --- a/drivers/common/cnxk/roc_idev.c +++ b/drivers/common/cnxk/roc_idev.c @@ -33,6 +33,7 @@ idev_set_defaults(struct idev_cfg *idev) idev->npa = NULL; idev->npa_pf_func = 0; idev->max_pools = 128; + idev->halo_ena = 0; idev->lmt_pf_func = 0; idev->lmt_base_addr = 0; idev->num_lmtlines = 0; @@ -123,6 +124,30 @@ roc_idev_npa_maxpools_set(uint32_t max_pools) __atomic_store_n(&idev->max_pools, max_pools, __ATOMIC_RELEASE); } +int +roc_idev_npa_halo_ena_get(void) +{ + struct idev_cfg *idev; + int halo_ena; + + idev = idev_get_cfg(); + halo_ena = 0; + if (idev != NULL) + halo_ena = __atomic_load_n(&idev->halo_ena, __ATOMIC_ACQUIRE); + + return halo_ena; +} + +void +roc_idev_npa_halo_ena_set(int halo_ena) +{ + struct idev_cfg *idev; + + idev = idev_get_cfg(); + if (idev != NULL) + __atomic_store_n(&idev->halo_ena, halo_ena, __ATOMIC_RELEASE); +} + uint16_t idev_npa_lf_active(struct dev *dev) { diff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h index 6edb5f83b2..3803963b07 100644 --- a/drivers/common/cnxk/roc_idev.h +++ b/drivers/common/cnxk/roc_idev.h @@ -8,6 +8,9 @@ uint32_t __roc_api roc_idev_npa_maxpools_get(void); void __roc_api roc_idev_npa_maxpools_set(uint32_t max_pools); +int __roc_api roc_idev_npa_halo_ena_get(void); +void __roc_api roc_idev_npa_halo_ena_set(int halo_ena); + /* LMT */ uint64_t __roc_api roc_idev_lmt_base_addr_get(void); uint16_t __roc_api roc_idev_num_lmtlines_get(void); diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h index 98b6286bfe..dde555535b 100644 --- a/drivers/common/cnxk/roc_idev_priv.h +++ b/drivers/common/cnxk/roc_idev_priv.h @@ -30,6 +30,7 @@ struct idev_cfg { struct npa_lf *npa; uint16_t npa_refcnt; uint32_t max_pools; + int halo_ena; uint16_t lmt_pf_func; uint16_t num_lmtlines; uint64_t lmt_base_addr; diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 3e913fa13c..3176c87382 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1397,6 +1397,8 @@ struct npa_cn20k_aq_enq_req { __io struct npa_cn20k_aura_s aura; /* Valid when op == WRITE/INIT and ctype == POOL */ __io struct npa_cn20k_pool_s pool; + /* Valid when op == WRITE/INIT and ctype == HALO */ + __io struct npa_cn20k_halo_s halo; }; /* Mask data when op == WRITE (1=write, 0=don't write) */ union { @@ -1404,6 +1406,8 @@ struct npa_cn20k_aq_enq_req { __io struct npa_cn20k_aura_s aura_mask; /* Valid when op == WRITE and ctype == POOL */ __io struct npa_cn20k_pool_s pool_mask; + /* Valid when op == WRITE/INIT and ctype == HALO */ + __io struct npa_cn20k_halo_s halo_mask; }; }; @@ -1414,6 +1418,8 @@ struct npa_cn20k_aq_enq_rsp { __io struct npa_cn20k_aura_s aura; /* Valid when op == READ and ctype == POOL */ __io struct npa_cn20k_pool_s pool; + /* Valid when op == READ and ctype == HALO */ + __io struct npa_cn20k_halo_s halo; }; }; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 326decde2b..aa197eb95e 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -595,6 +595,7 @@ struct roc_nix { uintptr_t lmt_base; bool io_enabled; bool rx_ptp_ena; + bool sqb_halo_ena; uint16_t cints; uint32_t buf_sz; uint64_t meta_aura_handle; diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index c7e37abf32..a6f487fe08 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -1486,8 +1486,6 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); uint16_t sqes_per_sqb, count, nb_sqb_bufs; - struct npa_pool_s pool; - struct npa_aura_s aura; uint64_t blk_sz; uint64_t iova; int rc; @@ -1509,20 +1507,38 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) /* Explicitly set nat_align alone as by default pool is with both * nat_align and buf_offset = 1 which we don't want for SQB. */ - memset(&pool, 0, sizeof(struct npa_pool_s)); - pool.nat_align = 1; + if (roc_model_is_cn20k() && roc_nix->sqb_halo_ena) { + struct npa_cn20k_halo_s halo; + + memset(&halo, 0, sizeof(struct npa_cn20k_halo_s)); + halo.nat_align = 1; + halo.fc_ena = 1; + halo.fc_stype = 0x3; /* STSTP */ + halo.fc_addr = (uint64_t)sq->fc; + halo.fc_hyst_bits = 0; /* Store count on all updates */ + halo.unified_ctx = 1; + rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, NULL, + (struct npa_pool_s *)&halo, ROC_NPA_HALO_F); + } else { + struct npa_pool_s pool; + struct npa_aura_s aura; + + memset(&pool, 0, sizeof(struct npa_pool_s)); + pool.nat_align = 1; + + memset(&aura, 0, sizeof(aura)); + /* Disable SQ pool FC updates when SQ count updates are used */ + if (!sq->sq_cnt_ptr) + aura.fc_ena = 1; + if (roc_model_is_cn9k() || roc_errata_npa_has_no_fc_stype_ststp()) + aura.fc_stype = 0x0; /* STF */ + else + aura.fc_stype = 0x3; /* STSTP */ + aura.fc_addr = (uint64_t)sq->fc; + aura.fc_hyst_bits = sq->fc_hyst_bits & 0xF; + rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0); + } - memset(&aura, 0, sizeof(aura)); - /* Disable SQ pool FC updates when SQ count updates are used */ - if (!sq->sq_cnt_ptr) - aura.fc_ena = 1; - if (roc_model_is_cn9k() || roc_errata_npa_has_no_fc_stype_ststp()) - aura.fc_stype = 0x0; /* STF */ - else - aura.fc_stype = 0x3; /* STSTP */ - aura.fc_addr = (uint64_t)sq->fc; - aura.fc_hyst_bits = sq->fc_hyst_bits & 0xF; - rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0); if (rc) goto fail; diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index f9824f6656..954ae211f9 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -82,7 +82,6 @@ static int npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura, struct npa_pool_s *pool) { - struct npa_cn20k_aq_enq_req *aura_init_req_cn20k, *pool_init_req_cn20k; struct npa_aq_enq_req *aura_init_req, *pool_init_req; struct npa_aq_enq_rsp *aura_init_rsp, *pool_init_rsp; struct mbox_dev *mdev = &m_box->dev[0]; @@ -91,6 +90,7 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; aura_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_init_req = (struct npa_aq_enq_req *)aura_init_req_cn20k; } else { @@ -104,6 +104,7 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura mbox_memcpy(&aura_init_req->aura, aura, sizeof(*aura)); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *pool_init_req_cn20k; pool_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); pool_init_req = (struct npa_aq_enq_req *)pool_init_req_cn20k; } else { @@ -139,7 +140,6 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura static int npa_aura_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura) { - struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; struct npa_aq_enq_req *aura_init_req; struct npa_aq_enq_rsp *aura_init_rsp; struct mbox *mbox; @@ -147,6 +147,7 @@ npa_aura_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura) mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; aura_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_init_req = (struct npa_aq_enq_req *)aura_init_req_cn20k; } else { @@ -209,10 +210,92 @@ npa_pool_multi_bp_reset(struct npa_cn20k_aq_enq_req *pool_req) pool_req->pool_mask.bp_ena_7 = ~(pool_req->pool_mask.bp_ena_7); } +static int +npa_halo_init(struct mbox *m_box, uint32_t aura_id, struct npa_cn20k_halo_s *halo) +{ + struct npa_cn20k_aq_enq_req *req; + struct npa_aq_enq_rsp *rsp; + struct mbox *mbox; + int rc = -ENOSPC; + + mbox = mbox_get(m_box); + req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); + if (req == NULL) + goto exit; + req->aura_id = aura_id; + req->ctype = NPA_AQ_CTYPE_HALO; + req->op = NPA_AQ_INSTOP_INIT; + mbox_memcpy(&req->halo, halo, sizeof(*halo)); + + rc = mbox_process_msg(mbox, (void **)&rsp); + if (rc < 0) + goto exit; + + if (rsp->hdr.rc == 0) + rc = 0; + else + rc = NPA_ERR_HALO_INIT; +exit: + mbox_put(mbox); + return rc; +} + +static int +npa_halo_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) +{ + struct mbox_dev *mdev = &m_box->dev[0]; + struct npa_cn20k_aq_enq_req *req; + struct npa_aq_enq_rsp *rsp; + int rc = -ENOSPC, off; + struct mbox *mbox; + uint64_t ptr; + + /* Procedure for disabling an aura/pool */ + plt_delay_us(10); + + /* Clear all the pointers from the aura */ + do { + ptr = roc_npa_aura_op_alloc(aura_handle, 0); + } while (ptr); + + mbox = mbox_get(m_box); + req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); + if (req == NULL) + goto exit; + + /* Disable backpressure on halo on CN20K */ + if (roc_model_is_cn20k()) + npa_pool_multi_bp_reset(req); + + req->aura_id = aura_id; + req->ctype = NPA_AQ_CTYPE_HALO; + req->op = NPA_AQ_INSTOP_WRITE; + req->halo.ena = 0; + req->halo_mask.ena = ~req->halo_mask.ena; + + rc = mbox_process(mbox); + if (rc < 0) + goto exit; + + off = mbox->rx_start + + PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); + rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off); + + if (rsp->hdr.rc != 0) { + rc = NPA_ERR_HALO_FINI; + goto exit; + } + + rc = 0; +exit: + mbox_put(mbox); + return rc; +} + static int npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k, *pool_req_cn20k = NULL; + struct npa_cn20k_aq_enq_req *pool_req_cn20k; struct npa_aq_enq_req *aura_req, *pool_req; struct npa_aq_enq_rsp *aura_rsp, *pool_rsp; struct mbox_dev *mdev = &m_box->dev[0]; @@ -249,6 +332,7 @@ npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) pool_req->pool_mask.ena = ~pool_req->pool_mask.ena; if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -318,7 +402,6 @@ npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) static int npa_aura_fini(struct mbox *m_box, uint32_t aura_id) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_aq_enq_rsp *aura_rsp; struct ndc_sync_op *ndc_req; @@ -330,6 +413,7 @@ npa_aura_fini(struct mbox *m_box, uint32_t aura_id) mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -439,10 +523,10 @@ roc_npa_pool_op_pc_reset(uint64_t aura_handle) int roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_lf *lf; struct mbox *mbox; + uint64_t aura_id; int rc; lf = idev_npa_obj_get(); @@ -450,6 +534,7 @@ roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) return NPA_ERR_DEVICE_NOT_BOUNDED; mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -459,8 +544,12 @@ roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) rc = -ENOMEM; goto exit; } - aura_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle); - aura_req->ctype = NPA_AQ_CTYPE_AURA; + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + aura_req->aura_id = aura_id; + if (lf->aura_attr[aura_id].halo) + aura_req->ctype = NPA_AQ_CTYPE_HALO; + else + aura_req->ctype = NPA_AQ_CTYPE_AURA; aura_req->op = NPA_AQ_INSTOP_WRITE; aura_req->aura.aura_drop_ena = ena; @@ -575,7 +664,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, /* Block size should be cache line aligned and in range of 128B-128KB */ if (block_size % ROC_ALIGN || block_size < 128 || - block_size > ROC_NPA_MAX_BLOCK_SZ) + block_size > roc_npa_max_block_size()) return NPA_ERR_INVALID_BLOCK_SZ; /* Get aura_id from resource bitmap */ @@ -627,11 +716,21 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, /* Update pool fields */ pool->stack_base = mz->iova; pool->ena = 1; + /* In opaque mode buffer size must be 0 */ - if (!pool->nat_align) + if (!pool->nat_align) { pool->buf_size = 0; - else - pool->buf_size = block_size / ROC_ALIGN; + } else { + uint64_t buf_sz = block_size / ROC_ALIGN; + if (roc_model_is_cn20k()) { + __io struct npa_cn20k_pool_s *cn20k_pool = + (__io struct npa_cn20k_pool_s *)pool; + cn20k_pool->buf_size = buf_sz; + } else { + pool->buf_size = buf_sz; + } + } + pool->stack_max_pages = stack_size; pool->shift = plt_log2_u32(block_count); pool->shift = pool->shift < 8 ? 0 : pool->shift - 8; @@ -653,6 +752,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, lf->aura_attr[aura_id].shift = aura->shift; lf->aura_attr[aura_id].limit = aura->limit; + lf->aura_attr[aura_id].halo = 0; *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); /* Update aura count */ roc_npa_aura_op_cnt_set(*aura_handle, 0, block_count); @@ -671,6 +771,86 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, return rc; } +static int +npa_halo_alloc(struct npa_lf *lf, const uint32_t block_size, const uint32_t block_count, + struct npa_cn20k_halo_s *halo, uint64_t *aura_handle, uint32_t flags) +{ + int rc, aura_id, stack_size, alloc_size, pool_id; + char name[PLT_MEMZONE_NAMESIZE]; + const struct plt_memzone *mz; + + /* Sanity check */ + if (!lf || !halo || !aura_handle) + return NPA_ERR_PARAM; + + roc_npa_dev_lock(); + /* Get aura_id from resource bitmap */ + aura_id = find_free_aura(lf, flags); + if (aura_id < 0) { + roc_npa_dev_unlock(); + return NPA_ERR_AURA_ID_ALLOC; + } + + /* Mark aura as reserved */ + plt_bitmap_clear(lf->npa_bmp, aura_id); + + roc_npa_dev_unlock(); + rc = (aura_id < 0 || aura_id >= (int)BIT_ULL(6 + lf->aura_sz)) ? NPA_ERR_AURA_ID_ALLOC : 0; + if (rc) + goto exit; + + /* Allocate stack memory */ + stack_size = (block_count + lf->stack_pg_ptrs - 1) / lf->stack_pg_ptrs; + alloc_size = stack_size * lf->stack_pg_bytes; + + pool_id = aura_id; + mz = npa_stack_dma_alloc(lf, name, pool_id, alloc_size); + if (mz == NULL) { + rc = NPA_ERR_ALLOC; + goto aura_res_put; + } + + /* Update halo fields */ + halo->ena = 1; + halo->shift = plt_log2_u32(block_count); + halo->shift = halo->shift < 8 ? 0 : halo->shift - 8; + halo->err_int_ena = BIT(NPA_AURA_ERR_INT_AURA_ADD_OVER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS); + halo->avg_con = 0; + /* Many to one reduction */ + halo->err_qint_idx = aura_id % lf->qints; + halo->stack_base = mz->iova; + /* In opaque mode buffer size must be 0 */ + halo->buf_size = !halo->nat_align ? 0 : block_size / ROC_ALIGN; + halo->stack_max_pages = stack_size; + halo->ptr_start = 0; + halo->ptr_end = ~0; + halo->stack_caching = 1; + halo->unified_ctx = 1; + + /* Issue HALO_INIT op */ + rc = npa_halo_init(lf->mbox, aura_id, halo); + if (rc) + goto stack_mem_free; + + lf->aura_attr[aura_id].shift = halo->shift; + lf->aura_attr[aura_id].halo = 1; + *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); + + return 0; + +stack_mem_free: + plt_memzone_free(mz); +aura_res_put: + roc_npa_dev_lock(); + plt_bitmap_set(lf->npa_bmp, aura_id); + roc_npa_dev_unlock(); +exit: + return rc; +} + int roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, uint32_t block_count, struct npa_aura_s *aura, @@ -713,10 +893,21 @@ roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, if (flags & ROC_NPA_FORCE_OPAQUE_MODE_F) pool->nat_align = 0; - rc = npa_aura_pool_pair_alloc(lf, block_size, block_count, aura, pool, - aura_handle, flags); + /* The pool argument will be a pointer to a npa_cn20k_halo_s structure + * when ROC_NPA_HALO_F flag is set. Note that halo and pool contexts + * are same in size and the fields that are modified here are 1:1 + * mapped in these structures. + */ + if (roc_model_is_cn20k() && (flags & ROC_NPA_HALO_F)) { + struct npa_cn20k_halo_s *halo = (struct npa_cn20k_halo_s *)pool; + rc = npa_halo_alloc(lf, block_size, block_count, halo, aura_handle, flags); + } else { + rc = npa_aura_pool_pair_alloc(lf, block_size, block_count, aura, pool, + aura_handle, flags); + } + if (rc) { - plt_err("Failed to alloc pool or aura rc=%d", rc); + plt_err("Failed to alloc pool/aura/halo rc=%d", rc); goto error; } @@ -773,7 +964,7 @@ npa_aura_alloc(struct npa_lf *lf, const uint32_t block_count, int pool_id, /* Many to one reduction */ aura->err_qint_idx = aura_id % lf->qints; - /* Issue AURA_INIT and POOL_INIT op */ + /* Issue AURA_INIT op */ rc = npa_aura_init(lf->mbox, aura_id, aura); if (rc) return rc; @@ -836,7 +1027,6 @@ roc_npa_aura_create(uint64_t *aura_handle, uint32_t block_count, int roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_lf *lf; struct mbox *mbox; @@ -848,6 +1038,7 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -872,6 +1063,28 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) return rc; } +static int +npa_halo_free(struct npa_lf *lf, uint64_t aura_handle) +{ + char name[PLT_MEMZONE_NAMESIZE]; + int aura_id, pool_id, rc; + + if (!lf || !aura_handle) + return NPA_ERR_PARAM; + + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + pool_id = aura_id; + rc = npa_halo_fini(lf->mbox, aura_id, aura_handle); + rc |= npa_stack_dma_free(lf, name, pool_id); + memset(&lf->aura_attr[aura_id], 0, sizeof(struct npa_aura_attr)); + + roc_npa_dev_lock(); + plt_bitmap_set(lf->npa_bmp, aura_id); + roc_npa_dev_unlock(); + + return rc; +} + static int npa_aura_pool_pair_free(struct npa_lf *lf, uint64_t aura_handle) { @@ -898,12 +1111,18 @@ int roc_npa_pool_destroy(uint64_t aura_handle) { struct npa_lf *lf = idev_npa_obj_get(); - int rc = 0; + int rc = 0, aura_id; plt_npa_dbg("lf=%p aura_handle=0x%" PRIx64, lf, aura_handle); - rc = npa_aura_pool_pair_free(lf, aura_handle); + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + + if (lf->aura_attr[aura_id].halo) + rc = npa_halo_free(lf, aura_handle); + else + rc = npa_aura_pool_pair_free(lf, aura_handle); + if (rc) - plt_err("Failed to destroy pool or aura rc=%d", rc); + plt_err("Failed to destroy pool/aura/halo rc=%d", rc); /* Release the reference of npa */ rc |= npa_lf_fini(); @@ -952,14 +1171,13 @@ roc_npa_aura_destroy(uint64_t aura_handle) int roc_npa_pool_range_update_check(uint64_t aura_handle) { - uint64_t aura_id = roc_npa_aura_handle_to_aura(aura_handle); - struct npa_cn20k_aq_enq_req *req_cn20k; __io struct npa_pool_s *pool; struct npa_aq_enq_req *req; struct npa_aq_enq_rsp *rsp; struct npa_aura_lim *lim; struct mbox *mbox; struct npa_lf *lf; + uint64_t aura_id; int rc; lf = idev_npa_obj_get(); @@ -970,6 +1188,7 @@ roc_npa_pool_range_update_check(uint64_t aura_handle) mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *req_cn20k; req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); req = (struct npa_aq_enq_req *)req_cn20k; } else { @@ -980,8 +1199,12 @@ roc_npa_pool_range_update_check(uint64_t aura_handle) goto exit; } + aura_id = roc_npa_aura_handle_to_aura(aura_handle); req->aura_id = aura_id; - req->ctype = NPA_AQ_CTYPE_POOL; + if (lf->aura_attr[aura_id].halo) + req->ctype = NPA_AQ_CTYPE_HALO; + else + req->ctype = NPA_AQ_CTYPE_POOL; req->op = NPA_AQ_INSTOP_READ; rc = mbox_process_msg(mbox, (void *)&rsp); @@ -1140,7 +1363,6 @@ int roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf, uint8_t bp_thresh, bool enable) { - /* TODO: Add support for CN20K */ uint32_t aura_id = roc_npa_aura_handle_to_aura(aura_handle); struct npa_lf *lf = idev_npa_obj_get(); struct npa_aq_enq_req *req; diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 336a43f95c..18808e5873 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -21,7 +21,9 @@ #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1) -#define ROC_NPA_MAX_BLOCK_SZ (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN9K (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN10K (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN20K (256 * 1024) #define ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS 512 #define ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS 15U #define ROC_CN10K_NPA_BATCH_FREE_BURST_MAX 16U @@ -36,6 +38,17 @@ */ #define ROC_CN9K_NPA_BULK_ALLOC_MAX_PTRS 30 +static inline uint32_t +roc_npa_max_block_size(void) +{ + if (roc_model_is_cn20k()) + return ROC_NPA_MAX_BLOCK_SZ_CN20K; + else if (roc_model_is_cn10k()) + return ROC_NPA_MAX_BLOCK_SZ_CN10K; + else + return ROC_NPA_MAX_BLOCK_SZ_CN9K; +} + /* * Generate 64bit handle to have optimized alloc and free aura operation. * 0 - ROC_AURA_ID_MASK for storing the aura_id. @@ -767,8 +780,9 @@ int __roc_api roc_npa_dev_init(struct roc_npa *roc_npa); int __roc_api roc_npa_dev_fini(struct roc_npa *roc_npa); /* Flags to pool create */ -#define ROC_NPA_ZERO_AURA_F BIT(0) -#define ROC_NPA_FORCE_OPAQUE_MODE_F BIT(1) +#define ROC_NPA_ZERO_AURA_F BIT(0) +#define ROC_NPA_FORCE_OPAQUE_MODE_F BIT(1) +#define ROC_NPA_HALO_F BIT(2) /* Enumerations */ enum roc_npa_buf_type { diff --git a/drivers/common/cnxk/roc_npa_debug.c b/drivers/common/cnxk/roc_npa_debug.c index 9a16f481a8..c26ca18b86 100644 --- a/drivers/common/cnxk/roc_npa_debug.c +++ b/drivers/common/cnxk/roc_npa_debug.c @@ -86,10 +86,171 @@ npa_aura_dump(__io struct npa_aura_s *aura) npa_dump("W6: thresh\t\t%" PRIx64 "\n", (uint64_t)aura->thresh); } +static inline void +npa_cn20k_pool_dump(__io struct npa_cn20k_pool_s *pool) +{ + npa_dump("W0: Stack base\t\t0x%" PRIx64 "\n", pool->stack_base); + npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d", + pool->ena, pool->nat_align, pool->stack_caching); + npa_dump("W1: buf_offset \t\t%d", pool->buf_offset); + npa_dump("W1: buf_size \t\t%d\nW1: ref_cnt_prof \t%d", + pool->buf_size, pool->ref_cnt_prof); + + npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n", + pool->stack_max_pages, pool->stack_pages); + + npa_dump("W3: bp_0 \t\t%d\nW3: bp_1 \t\t%d\nW3: bp_2 \t\t%d", + pool->bp_0, pool->bp_1, pool->bp_2); + npa_dump("W3: bp_3 \t\t%d\nW3: bp_4 \t\t%d\nW3: bp_5 \t\t%d", + pool->bp_3, pool->bp_4, pool->bp_5); + npa_dump("W3: bp_6 \t\t%d\nW3: bp_7 \t\t%d", pool->bp_6, pool->bp_7); + npa_dump("W3: bp_ena_0 \t\t%d\nW3: bp_ena_1 \t\t%d", pool->bp_ena_0, + pool->bp_ena_1); + npa_dump("W3: bp_ena_2 \t\t%d\nW3: bp_ena_3 \t\t%d", pool->bp_ena_2, + pool->bp_ena_3); + npa_dump("W3: bp_ena_4 \t\t%d\nW3: bp_ena_5 \t\t%d", pool->bp_ena_4, + pool->bp_ena_5); + npa_dump("W3: bp_ena_6 \t\t%d\nW3: bp_ena_7 \t\t%d\n", pool->bp_6, + pool->bp_7); + + npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d", + pool->stack_offset, pool->shift, pool->avg_level); + npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d", + pool->avg_con, pool->fc_ena, pool->fc_stype); + npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d", + pool->fc_hyst_bits, pool->fc_up_crossing); + npa_dump("W4: update_time\t\t%d\n", pool->update_time); + + npa_dump("W5: fc_addr\t\t0x%" PRIx64 "\n", pool->fc_addr); + + npa_dump("W6: ptr_start\t\t0x%" PRIx64 "\n", pool->ptr_start); + + npa_dump("W7: ptr_end\t\t0x%" PRIx64 "\n", pool->ptr_end); + + npa_dump("W8: bpid_0 \t\t%d", pool->bpid_0); + npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d", pool->err_int, + pool->err_int_ena); + npa_dump("W8: thresh_int\t\t%d", pool->thresh_int); + npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d", + pool->thresh_int_ena, pool->thresh_up); + npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n", + pool->thresh_qint_idx, pool->err_qint_idx); + npa_dump("W9: thresh\t\t%" PRIx64 "", (uint64_t)pool->thresh); + npa_dump("W9: fc_msh_dst \t\t%d", pool->fc_msh_dst); + npa_dump("W9: op_dpc_ena \t\t%d\nW9: op_dpc_set \t\t%d", + pool->op_dpc_ena, pool->op_dpc_set); + npa_dump("W9: stream_ctx \t\t%d", pool->stream_ctx); +} + +static inline void +npa_halo_dump(__io struct npa_cn20k_halo_s *halo) +{ + npa_dump("W0: Stack base\t\t0x%" PRIx64 "\n", halo->stack_base); + npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d", + halo->ena, halo->nat_align, halo->stack_caching); + npa_dump("W1: buf_offset\t\t%d\nW1: buf_size\t\t%d", + halo->buf_offset, halo->buf_size); + npa_dump("W1: ref_cnt_prof \t%d\n", halo->ref_cnt_prof); + + npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n", + halo->stack_max_pages, halo->stack_pages); + + npa_dump("W3: bp_0 \t\t%d\nW3: bp_1 \t\t%d\nW3: bp_2 \t\t%d", + halo->bp_0, halo->bp_1, halo->bp_2); + npa_dump("W3: bp_3 \t\t%d\nW3: bp_4 \t\t%d\nW3: bp_5 \t\t%d", + halo->bp_3, halo->bp_4, halo->bp_5); + npa_dump("W3: bp_6 \t\t%d\nW3: bp_7 \t\t%d", halo->bp_6, halo->bp_7); + + npa_dump("W3: bp_ena_0 \t\t%d\nW3: bp_ena_1 \t\t%d", halo->bp_ena_0, + halo->bp_ena_1); + npa_dump("W3: bp_ena_2 \t\t%d\nW3: bp_ena_3 \t\t%d", halo->bp_ena_2, + halo->bp_ena_3); + npa_dump("W3: bp_ena_4 \t\t%d\nW3: bp_ena_5 \t\t%d", halo->bp_ena_4, + halo->bp_ena_5); + npa_dump("W3: bp_ena_6 \t\t%d\nW3: bp_ena_7 \t\t%d\n", halo->bp_6, + halo->bp_7); + + npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d", + halo->stack_offset, halo->shift, halo->avg_level); + npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d", + halo->avg_con, halo->fc_ena, halo->fc_stype); + npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d", + halo->fc_hyst_bits, halo->fc_up_crossing); + npa_dump("W4: update_time\t\t%d\n", halo->update_time); + + npa_dump("W5: fc_addr\t\t0x%" PRIx64 "\n", halo->fc_addr); + + npa_dump("W6: ptr_start\t\t0x%" PRIx64 "\n", halo->ptr_start); + + npa_dump("W7: ptr_end\t\t0x%" PRIx64 "\n", halo->ptr_end); + npa_dump("W8: bpid_0 \t\t%d", halo->bpid_0); + npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d", halo->err_int, + halo->err_int_ena); + npa_dump("W8: thresh_int\t\t%d", halo->thresh_int); + + npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d", + halo->thresh_int_ena, halo->thresh_up); + npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n", + halo->thresh_qint_idx, halo->err_qint_idx); + npa_dump("W9: thresh \t\t%lu\nW9: fc_msh_dst \t\t%d", + (unsigned long)halo->thresh, halo->fc_msh_dst); + npa_dump("W9: op_dpc_ena \t\t%d\nW9: op_dpc_set \t\t%d", + halo->op_dpc_ena, halo->op_dpc_set); + npa_dump("W9: stream_ctx \t\t%d\nW9: unified_ctx \t%d", + halo->stream_ctx, halo->unified_ctx); +} + +static inline void +npa_cn20k_aura_dump(__io struct npa_cn20k_aura_s *aura) +{ + npa_dump("W0: Pool addr\t\t0x%" PRIx64 "\n", aura->pool_addr); + + npa_dump("W1: ena\t\t\t%d\nW1: pool caching\t%d", aura->ena, + aura->pool_caching); + npa_dump("W1: avg con\t\t%d\nW1: pool drop ena\t%d", aura->avg_con, + aura->pool_drop_ena); + npa_dump("W1: aura drop ena\t%d", aura->aura_drop_ena); + npa_dump("W1: bp_ena\t\t%d", aura->bp_ena); + npa_dump("W1: aura drop\t\t%d\nW1: aura shift\t\t%d", aura->aura_drop, + aura->shift); + npa_dump("W1: avg_level\t\t%d\n", aura->avg_level); + + npa_dump("W2: count\t\t%" PRIx64 "", (uint64_t)aura->count); + npa_dump("W2: bpid\t\t%d\n", aura->bpid); + + npa_dump("W3: limit\t\t%" PRIx64 "", (uint64_t)aura->limit); + npa_dump("W3: bp\t\t\t%d", aura->bp); + npa_dump("W3: fc_ena\t\t%d", aura->fc_ena); + npa_dump("W3: fc_up_crossing\t%d\nW3: fc_stype\t\t%d", + aura->fc_up_crossing, aura->fc_stype); + + npa_dump("W3: fc_hyst_bits\t%d\n", aura->fc_hyst_bits); + + npa_dump("W4: fc_addr\t\t0x%" PRIx64 "\n", aura->fc_addr); + + npa_dump("W5: pool_drop\t\t%d\nW5: update_time\t\t%d", aura->pool_drop, + aura->update_time); + npa_dump("W5: err_int\t\t%d", aura->err_int); + npa_dump("W5: err_int_ena\t\t%d\nW5: thresh_int\t\t%d", + aura->err_int_ena, aura->thresh_int); + npa_dump("W5: thresh_int_ena\t%d", aura->thresh_int_ena); + + npa_dump("W5: thresh_up\t\t%d\nW5: thresh_qint_idx\t%d", + aura->thresh_up, aura->thresh_qint_idx); + npa_dump("W5: err_qint_idx\t%d\n", aura->err_qint_idx); + + npa_dump("W6: thresh\t\t%" PRIx64 "", (uint64_t)aura->thresh); + npa_dump("W6: fc_msh_dst \t\t%d", aura->fc_msh_dst); + npa_dump("W6: op_dpc_ena \t\t%d\nW6: op_dpc_set \t\t%d", + aura->op_dpc_ena, aura->op_dpc_set); + npa_dump("W6: stream_ctx \t\t%d", aura->stream_ctx); +} + int roc_npa_ctx_dump(void) { struct npa_cn20k_aq_enq_req *aq_cn20k; + struct npa_cn20k_aq_enq_rsp *rsp_cn20k; struct npa_aq_enq_rsp *rsp; struct npa_aq_enq_req *aq; struct mbox *mbox; @@ -103,7 +264,7 @@ roc_npa_ctx_dump(void) mbox = mbox_get(lf->mbox); for (q = 0; q < lf->nr_pools; q++) { - /* Skip disabled POOL */ + /* Skip disabled AURA */ if (plt_bitmap_get(lf->npa_bmp, q)) continue; @@ -118,21 +279,34 @@ roc_npa_ctx_dump(void) goto exit; } aq->aura_id = q; - aq->ctype = NPA_AQ_CTYPE_POOL; aq->op = NPA_AQ_INSTOP_READ; + if (lf->aura_attr[q].halo) { + aq->ctype = NPA_AQ_CTYPE_HALO; + rc = mbox_process_msg(mbox, (void *)&rsp_cn20k); + } else { + aq->ctype = NPA_AQ_CTYPE_AURA; + rc = mbox_process_msg(mbox, (void *)&rsp); + } - rc = mbox_process_msg(mbox, (void *)&rsp); if (rc) { - plt_err("Failed to get pool(%d) context", q); + plt_err("Failed to get aura/halo(%d) context", q); goto exit; } - npa_dump("============== pool=%d ===============\n", q); - npa_pool_dump(&rsp->pool); + if (lf->aura_attr[q].halo) { + npa_dump("============== halo=%d ===============\n", q); + npa_halo_dump(&rsp_cn20k->halo); + } else { + npa_dump("============== aura=%d ===============\n", q); + if (roc_model_is_cn20k()) + npa_cn20k_aura_dump(&rsp_cn20k->aura); + else + npa_aura_dump(&rsp->aura); + } } for (q = 0; q < lf->nr_pools; q++) { - /* Skip disabled AURA */ - if (plt_bitmap_get(lf->npa_bmp, q)) + /* Skip halo and disabled POOL */ + if (plt_bitmap_get(lf->npa_bmp, q) || lf->aura_attr[q].halo) continue; if (roc_model_is_cn20k()) { @@ -146,16 +320,19 @@ roc_npa_ctx_dump(void) goto exit; } aq->aura_id = q; - aq->ctype = NPA_AQ_CTYPE_AURA; + aq->ctype = NPA_AQ_CTYPE_POOL; aq->op = NPA_AQ_INSTOP_READ; rc = mbox_process_msg(mbox, (void *)&rsp); if (rc) { - plt_err("Failed to get aura(%d) context", q); + plt_err("Failed to get pool(%d) context", q); goto exit; } - npa_dump("============== aura=%d ===============\n", q); - npa_aura_dump(&rsp->aura); + npa_dump("============== pool=%d ===============\n", q); + if (roc_model_is_cn20k()) + npa_cn20k_pool_dump(&rsp_cn20k->pool); + else + npa_pool_dump(&rsp->pool); } exit: diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h index 0223e4a438..e437fe831a 100644 --- a/drivers/common/cnxk/roc_npa_priv.h +++ b/drivers/common/cnxk/roc_npa_priv.h @@ -14,6 +14,8 @@ enum npa_error_status { NPA_ERR_AURA_POOL_FINI = -517, NPA_ERR_BASE_INVALID = -518, NPA_ERR_DEVICE_NOT_BOUNDED = -519, + NPA_ERR_HALO_INIT = -520, + NPA_ERR_HALO_FINI = -521, }; struct npa_lf { @@ -55,6 +57,7 @@ struct npa_aura_attr { uint64_t shift; uint64_t limit; uint8_t bp_ena; + bool halo; union { uint8_t bp; /* CN9K, CN10K */ uint8_t bp_thresh[8]; /* CN20K */ diff --git a/drivers/common/cnxk/roc_platform_base_symbols.c b/drivers/common/cnxk/roc_platform_base_symbols.c index 43095741f5..79dd18fbd7 100644 --- a/drivers/common/cnxk/roc_platform_base_symbols.c +++ b/drivers/common/cnxk/roc_platform_base_symbols.c @@ -85,6 +85,8 @@ RTE_EXPORT_INTERNAL_SYMBOL(roc_hash_sha256_gen) RTE_EXPORT_INTERNAL_SYMBOL(roc_hash_sha512_gen) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_maxpools_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_maxpools_set) +RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_halo_ena_get) +RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_halo_ena_set) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_lmt_base_addr_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_num_lmtlines_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_cpt_get) diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 1d82e5b978..b07454a7f0 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -834,8 +834,6 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, uint32_t nb_xae, uint32_t xae_waes, uint32_t xaq_buf_size, uint16_t nb_hwgrp) { - struct npa_pool_s pool; - struct npa_aura_s aura; plt_iova_t iova; uint32_t i; int rc; @@ -877,15 +875,32 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, goto free_fc; } - memset(&pool, 0, sizeof(struct npa_pool_s)); - pool.nat_align = 1; + if (roc_model_is_cn20k() && xaq->halo_ena) { + struct npa_cn20k_halo_s halo; + + memset(&halo, 0, sizeof(struct npa_cn20k_halo_s)); + halo.nat_align = 1; + halo.fc_ena = 1; + halo.fc_addr = (uint64_t)xaq->fc; + halo.fc_hyst_bits = 0; /* Store count on all updates */ + halo.unified_ctx = 1; + rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, + NULL, (struct npa_pool_s *)&halo, ROC_NPA_HALO_F); + } else { + struct npa_pool_s pool; + struct npa_aura_s aura; + + memset(&pool, 0, sizeof(struct npa_pool_s)); + pool.nat_align = 1; + + memset(&aura, 0, sizeof(aura)); + aura.fc_ena = 1; + aura.fc_addr = (uint64_t)xaq->fc; + aura.fc_hyst_bits = 0; /* Store count on all updates */ + rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, + &aura, &pool, 0); + } - memset(&aura, 0, sizeof(aura)); - aura.fc_ena = 1; - aura.fc_addr = (uint64_t)xaq->fc; - aura.fc_hyst_bits = 0; /* Store count on all updates */ - rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, - &aura, &pool, 0); if (rc) { plt_err("Failed to create XAQ pool"); goto npa_fail; diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index f1ad34bcc7..9d8356abb1 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -43,6 +43,7 @@ struct roc_sso_xaq_data { uint32_t nb_xae; uint32_t xaq_lmt; uint64_t aura_handle; + int halo_ena; void *fc; void *mem; }; -- 2.48.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool 2025-12-04 6:51 ` [PATCH 1/2] common/cnxk: add support for halos Nawal Kishor @ 2025-12-05 5:51 ` Nawal Kishor 2025-12-05 5:51 ` [PATCH v2 1/2] common/cnxk: add support for halos Nawal Kishor ` (2 more replies) 0 siblings, 3 replies; 18+ messages in thread From: Nawal Kishor @ 2025-12-05 5:51 UTC (permalink / raw) To: dev; +Cc: jerinj, asekhar, Nawal Kishor This series of patches adds support for HALO in CNXK mempool driver. Changes in v2: * Fixed compilation warnings. Nawal Kishor (2): common/cnxk: add support for halos mempool/cnxk: add halo support in mempool drivers/common/cnxk/hw/npa.h | 81 ++++++ drivers/common/cnxk/roc_idev.c | 25 ++ drivers/common/cnxk/roc_idev.h | 3 + drivers/common/cnxk/roc_idev_priv.h | 1 + drivers/common/cnxk/roc_mbox.h | 6 + drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 46 ++- drivers/common/cnxk/roc_npa.c | 268 ++++++++++++++++-- drivers/common/cnxk/roc_npa.h | 20 +- drivers/common/cnxk/roc_npa_debug.c | 201 ++++++++++++- drivers/common/cnxk/roc_npa_priv.h | 3 + .../common/cnxk/roc_platform_base_symbols.c | 2 + drivers/common/cnxk/roc_sso.c | 35 ++- drivers/common/cnxk/roc_sso.h | 1 + drivers/mempool/cnxk/cn10k_mempool_ops.c | 19 +- drivers/mempool/cnxk/cn20k_mempool_ops.c | 60 ++++ drivers/mempool/cnxk/cn9k_mempool_ops.c | 2 +- drivers/mempool/cnxk/cnxk_mempool.c | 40 ++- drivers/mempool/cnxk/cnxk_mempool.h | 16 +- drivers/mempool/cnxk/cnxk_mempool_ops.c | 11 +- drivers/mempool/cnxk/meson.build | 1 + 21 files changed, 750 insertions(+), 92 deletions(-) create mode 100644 drivers/mempool/cnxk/cn20k_mempool_ops.c -- 2.48.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 1/2] common/cnxk: add support for halos 2025-12-05 5:51 ` [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool Nawal Kishor @ 2025-12-05 5:51 ` Nawal Kishor 2025-12-05 5:51 ` [PATCH v2 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor 2026-01-14 6:04 ` [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool Stephen Hemminger 2 siblings, 0 replies; 18+ messages in thread From: Nawal Kishor @ 2025-12-05 5:51 UTC (permalink / raw) To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao, Harman Kalra Cc: jerinj, asekhar, Nawal Kishor In cn9k/cn10k NPA mempool creation required the creation of at least one aura and pool context. Even, if the mapping between aura and pool was 1:1 (i.e, one aura mapped to one pool), separate contexts were required for aura and pool. This wasted the context space and most of common use case for NPA mempool is 1:1 mapping between aura and pool. In cn20k, 1:1 aura pool mapping can now be replaced by using halos. Halos allow the creation of only one context which contains the information required for both aura and pool. This patch adds the support for creation of Halos in ROC. Signed-off-by: Nawal Kishor <nkishor@marvell.com> --- v2: * Fixed compilation warnings. drivers/common/cnxk/hw/npa.h | 81 ++++++ drivers/common/cnxk/roc_idev.c | 25 ++ drivers/common/cnxk/roc_idev.h | 3 + drivers/common/cnxk/roc_idev_priv.h | 1 + drivers/common/cnxk/roc_mbox.h | 6 + drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 46 ++- drivers/common/cnxk/roc_npa.c | 268 ++++++++++++++++-- drivers/common/cnxk/roc_npa.h | 20 +- drivers/common/cnxk/roc_npa_debug.c | 201 ++++++++++++- drivers/common/cnxk/roc_npa_priv.h | 3 + .../common/cnxk/roc_platform_base_symbols.c | 2 + drivers/common/cnxk/roc_sso.c | 35 ++- drivers/common/cnxk/roc_sso.h | 1 + 14 files changed, 630 insertions(+), 63 deletions(-) diff --git a/drivers/common/cnxk/hw/npa.h b/drivers/common/cnxk/hw/npa.h index 4fd1f9a64b..e421c70e01 100644 --- a/drivers/common/cnxk/hw/npa.h +++ b/drivers/common/cnxk/hw/npa.h @@ -118,6 +118,7 @@ #define NPA_AQ_CTYPE_AURA (0x0ull) #define NPA_AQ_CTYPE_POOL (0x1ull) +#define NPA_AQ_CTYPE_HALO (0x2ull) #define NPA_BPINTF_NIX0_RX (0x0ull) #define NPA_BPINTF_NIX1_RX (0x1ull) @@ -456,6 +457,86 @@ struct npa_cn20k_pool_s { uint64_t rsvd_1023_960 : 64; /* W15 */ }; +/* NPA halo context structure [CN20K] */ +struct npa_cn20k_halo_s { + uint64_t stack_base : 64; /* W0 */ + uint64_t ena : 1; /* W1 */ + uint64_t nat_align : 1; + uint64_t reserved_67_66 : 2; + uint64_t stack_caching : 1; + uint64_t reserved_71_69 : 3; + uint64_t aura_drop_ena : 1; + uint64_t reserved_79_73 : 7; + uint64_t aura_drop : 8; + uint64_t buf_offset : 12; + uint64_t reserved_103_100 : 4; + uint64_t buf_size : 12; + uint64_t reserved_119_116 : 4; + uint64_t ref_cnt_prof : 3; + uint64_t reserved_127_123 : 5; + uint64_t stack_max_pages : 32; /* W2 */ + uint64_t stack_pages : 32; + uint64_t bp_0 : 7; /* W3 */ + uint64_t bp_1 : 7; + uint64_t bp_2 : 7; + uint64_t bp_3 : 7; + uint64_t bp_4 : 7; + uint64_t bp_5 : 7; + uint64_t bp_6 : 7; + uint64_t bp_7 : 7; + uint64_t bp_ena_0 : 1; + uint64_t bp_ena_1 : 1; + uint64_t bp_ena_2 : 1; + uint64_t bp_ena_3 : 1; + uint64_t bp_ena_4 : 1; + uint64_t bp_ena_5 : 1; + uint64_t bp_ena_6 : 1; + uint64_t bp_ena_7 : 1; + uint64_t stack_offset : 4; /* W4 */ + uint64_t reserved_263_260 : 4; + uint64_t shift : 6; + uint64_t reserved_271_270 : 2; + uint64_t avg_level : 8; + uint64_t avg_con : 9; + uint64_t fc_ena : 1; + uint64_t fc_stype : 2; + uint64_t fc_hyst_bits : 4; + uint64_t fc_up_crossing : 1; + uint64_t reserved_299_297 : 3; + uint64_t update_time : 16; + uint64_t reserved_319_316 : 4; + uint64_t fc_addr : 64; /* W5 */ + uint64_t ptr_start : 64; /* W6 */ + uint64_t ptr_end : 64; /* W7 */ + uint64_t bpid_0 : 12; /* W8 */ + uint64_t reserved_535_524 : 12; + uint64_t err_int : 8; + uint64_t err_int_ena : 8; + uint64_t thresh_int : 1; + uint64_t thresh_int_ena : 1; + uint64_t thresh_up : 1; + uint64_t reserved_555_555 : 1; + uint64_t thresh_qint_idx : 7; + uint64_t reserved_563_563 : 1; + uint64_t err_qint_idx : 7; + uint64_t reserved_575_571 : 5; + uint64_t thresh : 36; /* W9 */ + uint64_t reserved_615_612 : 4; + uint64_t fc_msh_dst : 11; + uint64_t reserved_630_627 : 4; + uint64_t op_dpc_ena : 1; + uint64_t op_dpc_set : 5; + uint64_t reserved_637_637 : 1; + uint64_t stream_ctx : 1; + uint64_t unified_ctx : 1; + uint64_t reserved_703_640 : 64; /* W10 */ + uint64_t reserved_767_704 : 64; /* W11 */ + uint64_t reserved_831_768 : 64; /* W12 */ + uint64_t reserved_895_832 : 64; /* W13 */ + uint64_t reserved_959_896 : 64; /* W14 */ + uint64_t reserved_1023_960 : 64; /* W15 */ +}; + /* NPA queue interrupt context hardware structure */ struct npa_qint_hw_s { uint32_t count : 22; diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c index 84812f73e0..6aa5b10ee9 100644 --- a/drivers/common/cnxk/roc_idev.c +++ b/drivers/common/cnxk/roc_idev.c @@ -33,6 +33,7 @@ idev_set_defaults(struct idev_cfg *idev) idev->npa = NULL; idev->npa_pf_func = 0; idev->max_pools = 128; + idev->halo_ena = 0; idev->lmt_pf_func = 0; idev->lmt_base_addr = 0; idev->num_lmtlines = 0; @@ -123,6 +124,30 @@ roc_idev_npa_maxpools_set(uint32_t max_pools) __atomic_store_n(&idev->max_pools, max_pools, __ATOMIC_RELEASE); } +int +roc_idev_npa_halo_ena_get(void) +{ + struct idev_cfg *idev; + int halo_ena; + + idev = idev_get_cfg(); + halo_ena = 0; + if (idev != NULL) + halo_ena = __atomic_load_n(&idev->halo_ena, __ATOMIC_ACQUIRE); + + return halo_ena; +} + +void +roc_idev_npa_halo_ena_set(int halo_ena) +{ + struct idev_cfg *idev; + + idev = idev_get_cfg(); + if (idev != NULL) + __atomic_store_n(&idev->halo_ena, halo_ena, __ATOMIC_RELEASE); +} + uint16_t idev_npa_lf_active(struct dev *dev) { diff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h index 6edb5f83b2..3803963b07 100644 --- a/drivers/common/cnxk/roc_idev.h +++ b/drivers/common/cnxk/roc_idev.h @@ -8,6 +8,9 @@ uint32_t __roc_api roc_idev_npa_maxpools_get(void); void __roc_api roc_idev_npa_maxpools_set(uint32_t max_pools); +int __roc_api roc_idev_npa_halo_ena_get(void); +void __roc_api roc_idev_npa_halo_ena_set(int halo_ena); + /* LMT */ uint64_t __roc_api roc_idev_lmt_base_addr_get(void); uint16_t __roc_api roc_idev_num_lmtlines_get(void); diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h index 98b6286bfe..dde555535b 100644 --- a/drivers/common/cnxk/roc_idev_priv.h +++ b/drivers/common/cnxk/roc_idev_priv.h @@ -30,6 +30,7 @@ struct idev_cfg { struct npa_lf *npa; uint16_t npa_refcnt; uint32_t max_pools; + int halo_ena; uint16_t lmt_pf_func; uint16_t num_lmtlines; uint64_t lmt_base_addr; diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 3e913fa13c..3176c87382 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1397,6 +1397,8 @@ struct npa_cn20k_aq_enq_req { __io struct npa_cn20k_aura_s aura; /* Valid when op == WRITE/INIT and ctype == POOL */ __io struct npa_cn20k_pool_s pool; + /* Valid when op == WRITE/INIT and ctype == HALO */ + __io struct npa_cn20k_halo_s halo; }; /* Mask data when op == WRITE (1=write, 0=don't write) */ union { @@ -1404,6 +1406,8 @@ struct npa_cn20k_aq_enq_req { __io struct npa_cn20k_aura_s aura_mask; /* Valid when op == WRITE and ctype == POOL */ __io struct npa_cn20k_pool_s pool_mask; + /* Valid when op == WRITE/INIT and ctype == HALO */ + __io struct npa_cn20k_halo_s halo_mask; }; }; @@ -1414,6 +1418,8 @@ struct npa_cn20k_aq_enq_rsp { __io struct npa_cn20k_aura_s aura; /* Valid when op == READ and ctype == POOL */ __io struct npa_cn20k_pool_s pool; + /* Valid when op == READ and ctype == HALO */ + __io struct npa_cn20k_halo_s halo; }; }; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 326decde2b..aa197eb95e 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -595,6 +595,7 @@ struct roc_nix { uintptr_t lmt_base; bool io_enabled; bool rx_ptp_ena; + bool sqb_halo_ena; uint16_t cints; uint32_t buf_sz; uint64_t meta_aura_handle; diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index c7e37abf32..a6f487fe08 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -1486,8 +1486,6 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); uint16_t sqes_per_sqb, count, nb_sqb_bufs; - struct npa_pool_s pool; - struct npa_aura_s aura; uint64_t blk_sz; uint64_t iova; int rc; @@ -1509,20 +1507,38 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) /* Explicitly set nat_align alone as by default pool is with both * nat_align and buf_offset = 1 which we don't want for SQB. */ - memset(&pool, 0, sizeof(struct npa_pool_s)); - pool.nat_align = 1; + if (roc_model_is_cn20k() && roc_nix->sqb_halo_ena) { + struct npa_cn20k_halo_s halo; + + memset(&halo, 0, sizeof(struct npa_cn20k_halo_s)); + halo.nat_align = 1; + halo.fc_ena = 1; + halo.fc_stype = 0x3; /* STSTP */ + halo.fc_addr = (uint64_t)sq->fc; + halo.fc_hyst_bits = 0; /* Store count on all updates */ + halo.unified_ctx = 1; + rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, NULL, + (struct npa_pool_s *)&halo, ROC_NPA_HALO_F); + } else { + struct npa_pool_s pool; + struct npa_aura_s aura; + + memset(&pool, 0, sizeof(struct npa_pool_s)); + pool.nat_align = 1; + + memset(&aura, 0, sizeof(aura)); + /* Disable SQ pool FC updates when SQ count updates are used */ + if (!sq->sq_cnt_ptr) + aura.fc_ena = 1; + if (roc_model_is_cn9k() || roc_errata_npa_has_no_fc_stype_ststp()) + aura.fc_stype = 0x0; /* STF */ + else + aura.fc_stype = 0x3; /* STSTP */ + aura.fc_addr = (uint64_t)sq->fc; + aura.fc_hyst_bits = sq->fc_hyst_bits & 0xF; + rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0); + } - memset(&aura, 0, sizeof(aura)); - /* Disable SQ pool FC updates when SQ count updates are used */ - if (!sq->sq_cnt_ptr) - aura.fc_ena = 1; - if (roc_model_is_cn9k() || roc_errata_npa_has_no_fc_stype_ststp()) - aura.fc_stype = 0x0; /* STF */ - else - aura.fc_stype = 0x3; /* STSTP */ - aura.fc_addr = (uint64_t)sq->fc; - aura.fc_hyst_bits = sq->fc_hyst_bits & 0xF; - rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0); if (rc) goto fail; diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index f9824f6656..e8df8ad077 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -82,7 +82,6 @@ static int npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura, struct npa_pool_s *pool) { - struct npa_cn20k_aq_enq_req *aura_init_req_cn20k, *pool_init_req_cn20k; struct npa_aq_enq_req *aura_init_req, *pool_init_req; struct npa_aq_enq_rsp *aura_init_rsp, *pool_init_rsp; struct mbox_dev *mdev = &m_box->dev[0]; @@ -91,6 +90,7 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; aura_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_init_req = (struct npa_aq_enq_req *)aura_init_req_cn20k; } else { @@ -104,6 +104,7 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura mbox_memcpy(&aura_init_req->aura, aura, sizeof(*aura)); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *pool_init_req_cn20k; pool_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); pool_init_req = (struct npa_aq_enq_req *)pool_init_req_cn20k; } else { @@ -139,7 +140,6 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura static int npa_aura_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura) { - struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; struct npa_aq_enq_req *aura_init_req; struct npa_aq_enq_rsp *aura_init_rsp; struct mbox *mbox; @@ -147,6 +147,7 @@ npa_aura_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura) mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; aura_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_init_req = (struct npa_aq_enq_req *)aura_init_req_cn20k; } else { @@ -209,10 +210,92 @@ npa_pool_multi_bp_reset(struct npa_cn20k_aq_enq_req *pool_req) pool_req->pool_mask.bp_ena_7 = ~(pool_req->pool_mask.bp_ena_7); } +static int +npa_halo_init(struct mbox *m_box, uint32_t aura_id, struct npa_cn20k_halo_s *halo) +{ + struct npa_cn20k_aq_enq_req *req; + struct npa_aq_enq_rsp *rsp; + struct mbox *mbox; + int rc = -ENOSPC; + + mbox = mbox_get(m_box); + req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); + if (req == NULL) + goto exit; + req->aura_id = aura_id; + req->ctype = NPA_AQ_CTYPE_HALO; + req->op = NPA_AQ_INSTOP_INIT; + mbox_memcpy(&req->halo, halo, sizeof(*halo)); + + rc = mbox_process_msg(mbox, (void **)&rsp); + if (rc < 0) + goto exit; + + if (rsp->hdr.rc == 0) + rc = 0; + else + rc = NPA_ERR_HALO_INIT; +exit: + mbox_put(mbox); + return rc; +} + +static int +npa_halo_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) +{ + struct mbox_dev *mdev = &m_box->dev[0]; + struct npa_cn20k_aq_enq_req *req; + struct npa_aq_enq_rsp *rsp; + int rc = -ENOSPC, off; + struct mbox *mbox; + uint64_t ptr; + + /* Procedure for disabling an aura/pool */ + plt_delay_us(10); + + /* Clear all the pointers from the aura */ + do { + ptr = roc_npa_aura_op_alloc(aura_handle, 0); + } while (ptr); + + mbox = mbox_get(m_box); + req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); + if (req == NULL) + goto exit; + + /* Disable backpressure on halo on CN20K */ + if (roc_model_is_cn20k()) + npa_pool_multi_bp_reset(req); + + req->aura_id = aura_id; + req->ctype = NPA_AQ_CTYPE_HALO; + req->op = NPA_AQ_INSTOP_WRITE; + req->halo.ena = 0; + req->halo_mask.ena = ~req->halo_mask.ena; + + rc = mbox_process(mbox); + if (rc < 0) + goto exit; + + off = mbox->rx_start + + PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); + rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off); + + if (rsp->hdr.rc != 0) { + rc = NPA_ERR_HALO_FINI; + goto exit; + } + + rc = 0; +exit: + mbox_put(mbox); + return rc; +} + static int npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k, *pool_req_cn20k = NULL; + struct npa_cn20k_aq_enq_req *pool_req_cn20k = NULL; struct npa_aq_enq_req *aura_req, *pool_req; struct npa_aq_enq_rsp *aura_rsp, *pool_rsp; struct mbox_dev *mdev = &m_box->dev[0]; @@ -249,6 +332,7 @@ npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) pool_req->pool_mask.ena = ~pool_req->pool_mask.ena; if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -318,7 +402,6 @@ npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) static int npa_aura_fini(struct mbox *m_box, uint32_t aura_id) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_aq_enq_rsp *aura_rsp; struct ndc_sync_op *ndc_req; @@ -330,6 +413,7 @@ npa_aura_fini(struct mbox *m_box, uint32_t aura_id) mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -439,10 +523,10 @@ roc_npa_pool_op_pc_reset(uint64_t aura_handle) int roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_lf *lf; struct mbox *mbox; + uint64_t aura_id; int rc; lf = idev_npa_obj_get(); @@ -450,6 +534,7 @@ roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) return NPA_ERR_DEVICE_NOT_BOUNDED; mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -459,8 +544,12 @@ roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) rc = -ENOMEM; goto exit; } - aura_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle); - aura_req->ctype = NPA_AQ_CTYPE_AURA; + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + aura_req->aura_id = aura_id; + if (lf->aura_attr[aura_id].halo) + aura_req->ctype = NPA_AQ_CTYPE_HALO; + else + aura_req->ctype = NPA_AQ_CTYPE_AURA; aura_req->op = NPA_AQ_INSTOP_WRITE; aura_req->aura.aura_drop_ena = ena; @@ -575,7 +664,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, /* Block size should be cache line aligned and in range of 128B-128KB */ if (block_size % ROC_ALIGN || block_size < 128 || - block_size > ROC_NPA_MAX_BLOCK_SZ) + block_size > roc_npa_max_block_size()) return NPA_ERR_INVALID_BLOCK_SZ; /* Get aura_id from resource bitmap */ @@ -627,11 +716,21 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, /* Update pool fields */ pool->stack_base = mz->iova; pool->ena = 1; + /* In opaque mode buffer size must be 0 */ - if (!pool->nat_align) + if (!pool->nat_align) { pool->buf_size = 0; - else - pool->buf_size = block_size / ROC_ALIGN; + } else { + uint64_t buf_sz = block_size / ROC_ALIGN; + if (roc_model_is_cn20k()) { + __io struct npa_cn20k_pool_s *cn20k_pool = + (__io struct npa_cn20k_pool_s *)pool; + cn20k_pool->buf_size = buf_sz; + } else { + pool->buf_size = buf_sz; + } + } + pool->stack_max_pages = stack_size; pool->shift = plt_log2_u32(block_count); pool->shift = pool->shift < 8 ? 0 : pool->shift - 8; @@ -653,6 +752,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, lf->aura_attr[aura_id].shift = aura->shift; lf->aura_attr[aura_id].limit = aura->limit; + lf->aura_attr[aura_id].halo = 0; *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); /* Update aura count */ roc_npa_aura_op_cnt_set(*aura_handle, 0, block_count); @@ -671,6 +771,86 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, return rc; } +static int +npa_halo_alloc(struct npa_lf *lf, const uint32_t block_size, const uint32_t block_count, + struct npa_cn20k_halo_s *halo, uint64_t *aura_handle, uint32_t flags) +{ + int rc, aura_id, stack_size, alloc_size, pool_id; + char name[PLT_MEMZONE_NAMESIZE]; + const struct plt_memzone *mz; + + /* Sanity check */ + if (!lf || !halo || !aura_handle) + return NPA_ERR_PARAM; + + roc_npa_dev_lock(); + /* Get aura_id from resource bitmap */ + aura_id = find_free_aura(lf, flags); + if (aura_id < 0) { + roc_npa_dev_unlock(); + return NPA_ERR_AURA_ID_ALLOC; + } + + /* Mark aura as reserved */ + plt_bitmap_clear(lf->npa_bmp, aura_id); + + roc_npa_dev_unlock(); + rc = (aura_id < 0 || aura_id >= (int)BIT_ULL(6 + lf->aura_sz)) ? NPA_ERR_AURA_ID_ALLOC : 0; + if (rc) + goto exit; + + /* Allocate stack memory */ + stack_size = (block_count + lf->stack_pg_ptrs - 1) / lf->stack_pg_ptrs; + alloc_size = stack_size * lf->stack_pg_bytes; + + pool_id = aura_id; + mz = npa_stack_dma_alloc(lf, name, pool_id, alloc_size); + if (mz == NULL) { + rc = NPA_ERR_ALLOC; + goto aura_res_put; + } + + /* Update halo fields */ + halo->ena = 1; + halo->shift = plt_log2_u32(block_count); + halo->shift = halo->shift < 8 ? 0 : halo->shift - 8; + halo->err_int_ena = BIT(NPA_AURA_ERR_INT_AURA_ADD_OVER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS); + halo->avg_con = 0; + /* Many to one reduction */ + halo->err_qint_idx = aura_id % lf->qints; + halo->stack_base = mz->iova; + /* In opaque mode buffer size must be 0 */ + halo->buf_size = !halo->nat_align ? 0 : block_size / ROC_ALIGN; + halo->stack_max_pages = stack_size; + halo->ptr_start = 0; + halo->ptr_end = ~0; + halo->stack_caching = 1; + halo->unified_ctx = 1; + + /* Issue HALO_INIT op */ + rc = npa_halo_init(lf->mbox, aura_id, halo); + if (rc) + goto stack_mem_free; + + lf->aura_attr[aura_id].shift = halo->shift; + lf->aura_attr[aura_id].halo = 1; + *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); + + return 0; + +stack_mem_free: + plt_memzone_free(mz); +aura_res_put: + roc_npa_dev_lock(); + plt_bitmap_set(lf->npa_bmp, aura_id); + roc_npa_dev_unlock(); +exit: + return rc; +} + int roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, uint32_t block_count, struct npa_aura_s *aura, @@ -713,10 +893,21 @@ roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, if (flags & ROC_NPA_FORCE_OPAQUE_MODE_F) pool->nat_align = 0; - rc = npa_aura_pool_pair_alloc(lf, block_size, block_count, aura, pool, - aura_handle, flags); + /* The pool argument will be a pointer to a npa_cn20k_halo_s structure + * when ROC_NPA_HALO_F flag is set. Note that halo and pool contexts + * are same in size and the fields that are modified here are 1:1 + * mapped in these structures. + */ + if (roc_model_is_cn20k() && (flags & ROC_NPA_HALO_F)) { + struct npa_cn20k_halo_s *halo = (struct npa_cn20k_halo_s *)pool; + rc = npa_halo_alloc(lf, block_size, block_count, halo, aura_handle, flags); + } else { + rc = npa_aura_pool_pair_alloc(lf, block_size, block_count, aura, pool, + aura_handle, flags); + } + if (rc) { - plt_err("Failed to alloc pool or aura rc=%d", rc); + plt_err("Failed to alloc pool/aura/halo rc=%d", rc); goto error; } @@ -773,7 +964,7 @@ npa_aura_alloc(struct npa_lf *lf, const uint32_t block_count, int pool_id, /* Many to one reduction */ aura->err_qint_idx = aura_id % lf->qints; - /* Issue AURA_INIT and POOL_INIT op */ + /* Issue AURA_INIT op */ rc = npa_aura_init(lf->mbox, aura_id, aura); if (rc) return rc; @@ -836,7 +1027,6 @@ roc_npa_aura_create(uint64_t *aura_handle, uint32_t block_count, int roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_lf *lf; struct mbox *mbox; @@ -848,6 +1038,7 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -872,6 +1063,28 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) return rc; } +static int +npa_halo_free(struct npa_lf *lf, uint64_t aura_handle) +{ + char name[PLT_MEMZONE_NAMESIZE]; + int aura_id, pool_id, rc; + + if (!lf || !aura_handle) + return NPA_ERR_PARAM; + + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + pool_id = aura_id; + rc = npa_halo_fini(lf->mbox, aura_id, aura_handle); + rc |= npa_stack_dma_free(lf, name, pool_id); + memset(&lf->aura_attr[aura_id], 0, sizeof(struct npa_aura_attr)); + + roc_npa_dev_lock(); + plt_bitmap_set(lf->npa_bmp, aura_id); + roc_npa_dev_unlock(); + + return rc; +} + static int npa_aura_pool_pair_free(struct npa_lf *lf, uint64_t aura_handle) { @@ -898,12 +1111,18 @@ int roc_npa_pool_destroy(uint64_t aura_handle) { struct npa_lf *lf = idev_npa_obj_get(); - int rc = 0; + int rc = 0, aura_id; plt_npa_dbg("lf=%p aura_handle=0x%" PRIx64, lf, aura_handle); - rc = npa_aura_pool_pair_free(lf, aura_handle); + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + + if (lf->aura_attr[aura_id].halo) + rc = npa_halo_free(lf, aura_handle); + else + rc = npa_aura_pool_pair_free(lf, aura_handle); + if (rc) - plt_err("Failed to destroy pool or aura rc=%d", rc); + plt_err("Failed to destroy pool/aura/halo rc=%d", rc); /* Release the reference of npa */ rc |= npa_lf_fini(); @@ -952,14 +1171,13 @@ roc_npa_aura_destroy(uint64_t aura_handle) int roc_npa_pool_range_update_check(uint64_t aura_handle) { - uint64_t aura_id = roc_npa_aura_handle_to_aura(aura_handle); - struct npa_cn20k_aq_enq_req *req_cn20k; __io struct npa_pool_s *pool; struct npa_aq_enq_req *req; struct npa_aq_enq_rsp *rsp; struct npa_aura_lim *lim; struct mbox *mbox; struct npa_lf *lf; + uint64_t aura_id; int rc; lf = idev_npa_obj_get(); @@ -970,6 +1188,7 @@ roc_npa_pool_range_update_check(uint64_t aura_handle) mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *req_cn20k; req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); req = (struct npa_aq_enq_req *)req_cn20k; } else { @@ -980,8 +1199,12 @@ roc_npa_pool_range_update_check(uint64_t aura_handle) goto exit; } + aura_id = roc_npa_aura_handle_to_aura(aura_handle); req->aura_id = aura_id; - req->ctype = NPA_AQ_CTYPE_POOL; + if (lf->aura_attr[aura_id].halo) + req->ctype = NPA_AQ_CTYPE_HALO; + else + req->ctype = NPA_AQ_CTYPE_POOL; req->op = NPA_AQ_INSTOP_READ; rc = mbox_process_msg(mbox, (void *)&rsp); @@ -1140,7 +1363,6 @@ int roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf, uint8_t bp_thresh, bool enable) { - /* TODO: Add support for CN20K */ uint32_t aura_id = roc_npa_aura_handle_to_aura(aura_handle); struct npa_lf *lf = idev_npa_obj_get(); struct npa_aq_enq_req *req; diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 336a43f95c..18808e5873 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -21,7 +21,9 @@ #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1) -#define ROC_NPA_MAX_BLOCK_SZ (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN9K (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN10K (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN20K (256 * 1024) #define ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS 512 #define ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS 15U #define ROC_CN10K_NPA_BATCH_FREE_BURST_MAX 16U @@ -36,6 +38,17 @@ */ #define ROC_CN9K_NPA_BULK_ALLOC_MAX_PTRS 30 +static inline uint32_t +roc_npa_max_block_size(void) +{ + if (roc_model_is_cn20k()) + return ROC_NPA_MAX_BLOCK_SZ_CN20K; + else if (roc_model_is_cn10k()) + return ROC_NPA_MAX_BLOCK_SZ_CN10K; + else + return ROC_NPA_MAX_BLOCK_SZ_CN9K; +} + /* * Generate 64bit handle to have optimized alloc and free aura operation. * 0 - ROC_AURA_ID_MASK for storing the aura_id. @@ -767,8 +780,9 @@ int __roc_api roc_npa_dev_init(struct roc_npa *roc_npa); int __roc_api roc_npa_dev_fini(struct roc_npa *roc_npa); /* Flags to pool create */ -#define ROC_NPA_ZERO_AURA_F BIT(0) -#define ROC_NPA_FORCE_OPAQUE_MODE_F BIT(1) +#define ROC_NPA_ZERO_AURA_F BIT(0) +#define ROC_NPA_FORCE_OPAQUE_MODE_F BIT(1) +#define ROC_NPA_HALO_F BIT(2) /* Enumerations */ enum roc_npa_buf_type { diff --git a/drivers/common/cnxk/roc_npa_debug.c b/drivers/common/cnxk/roc_npa_debug.c index 9a16f481a8..e64696730f 100644 --- a/drivers/common/cnxk/roc_npa_debug.c +++ b/drivers/common/cnxk/roc_npa_debug.c @@ -86,10 +86,171 @@ npa_aura_dump(__io struct npa_aura_s *aura) npa_dump("W6: thresh\t\t%" PRIx64 "\n", (uint64_t)aura->thresh); } +static inline void +npa_cn20k_pool_dump(__io struct npa_cn20k_pool_s *pool) +{ + npa_dump("W0: Stack base\t\t0x%" PRIx64 "\n", pool->stack_base); + npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d", + pool->ena, pool->nat_align, pool->stack_caching); + npa_dump("W1: buf_offset \t\t%d", pool->buf_offset); + npa_dump("W1: buf_size \t\t%d\nW1: ref_cnt_prof \t%d", + pool->buf_size, pool->ref_cnt_prof); + + npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n", + pool->stack_max_pages, pool->stack_pages); + + npa_dump("W3: bp_0 \t\t%d\nW3: bp_1 \t\t%d\nW3: bp_2 \t\t%d", + pool->bp_0, pool->bp_1, pool->bp_2); + npa_dump("W3: bp_3 \t\t%d\nW3: bp_4 \t\t%d\nW3: bp_5 \t\t%d", + pool->bp_3, pool->bp_4, pool->bp_5); + npa_dump("W3: bp_6 \t\t%d\nW3: bp_7 \t\t%d", pool->bp_6, pool->bp_7); + npa_dump("W3: bp_ena_0 \t\t%d\nW3: bp_ena_1 \t\t%d", pool->bp_ena_0, + pool->bp_ena_1); + npa_dump("W3: bp_ena_2 \t\t%d\nW3: bp_ena_3 \t\t%d", pool->bp_ena_2, + pool->bp_ena_3); + npa_dump("W3: bp_ena_4 \t\t%d\nW3: bp_ena_5 \t\t%d", pool->bp_ena_4, + pool->bp_ena_5); + npa_dump("W3: bp_ena_6 \t\t%d\nW3: bp_ena_7 \t\t%d\n", pool->bp_6, + pool->bp_7); + + npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d", + pool->stack_offset, pool->shift, pool->avg_level); + npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d", + pool->avg_con, pool->fc_ena, pool->fc_stype); + npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d", + pool->fc_hyst_bits, pool->fc_up_crossing); + npa_dump("W4: update_time\t\t%d\n", pool->update_time); + + npa_dump("W5: fc_addr\t\t0x%" PRIx64 "\n", pool->fc_addr); + + npa_dump("W6: ptr_start\t\t0x%" PRIx64 "\n", pool->ptr_start); + + npa_dump("W7: ptr_end\t\t0x%" PRIx64 "\n", pool->ptr_end); + + npa_dump("W8: bpid_0 \t\t%d", pool->bpid_0); + npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d", pool->err_int, + pool->err_int_ena); + npa_dump("W8: thresh_int\t\t%d", pool->thresh_int); + npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d", + pool->thresh_int_ena, pool->thresh_up); + npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n", + pool->thresh_qint_idx, pool->err_qint_idx); + npa_dump("W9: thresh\t\t%" PRIx64 "", (uint64_t)pool->thresh); + npa_dump("W9: fc_msh_dst \t\t%d", pool->fc_msh_dst); + npa_dump("W9: op_dpc_ena \t\t%d\nW9: op_dpc_set \t\t%d", + pool->op_dpc_ena, pool->op_dpc_set); + npa_dump("W9: stream_ctx \t\t%d", pool->stream_ctx); +} + +static inline void +npa_halo_dump(__io struct npa_cn20k_halo_s *halo) +{ + npa_dump("W0: Stack base\t\t0x%" PRIx64 "\n", halo->stack_base); + npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d", + halo->ena, halo->nat_align, halo->stack_caching); + npa_dump("W1: buf_offset\t\t%d\nW1: buf_size\t\t%d", + halo->buf_offset, halo->buf_size); + npa_dump("W1: ref_cnt_prof \t%d\n", halo->ref_cnt_prof); + + npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n", + halo->stack_max_pages, halo->stack_pages); + + npa_dump("W3: bp_0 \t\t%d\nW3: bp_1 \t\t%d\nW3: bp_2 \t\t%d", + halo->bp_0, halo->bp_1, halo->bp_2); + npa_dump("W3: bp_3 \t\t%d\nW3: bp_4 \t\t%d\nW3: bp_5 \t\t%d", + halo->bp_3, halo->bp_4, halo->bp_5); + npa_dump("W3: bp_6 \t\t%d\nW3: bp_7 \t\t%d", halo->bp_6, halo->bp_7); + + npa_dump("W3: bp_ena_0 \t\t%d\nW3: bp_ena_1 \t\t%d", halo->bp_ena_0, + halo->bp_ena_1); + npa_dump("W3: bp_ena_2 \t\t%d\nW3: bp_ena_3 \t\t%d", halo->bp_ena_2, + halo->bp_ena_3); + npa_dump("W3: bp_ena_4 \t\t%d\nW3: bp_ena_5 \t\t%d", halo->bp_ena_4, + halo->bp_ena_5); + npa_dump("W3: bp_ena_6 \t\t%d\nW3: bp_ena_7 \t\t%d\n", halo->bp_6, + halo->bp_7); + + npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d", + halo->stack_offset, halo->shift, halo->avg_level); + npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d", + halo->avg_con, halo->fc_ena, halo->fc_stype); + npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d", + halo->fc_hyst_bits, halo->fc_up_crossing); + npa_dump("W4: update_time\t\t%d\n", halo->update_time); + + npa_dump("W5: fc_addr\t\t0x%" PRIx64 "\n", halo->fc_addr); + + npa_dump("W6: ptr_start\t\t0x%" PRIx64 "\n", halo->ptr_start); + + npa_dump("W7: ptr_end\t\t0x%" PRIx64 "\n", halo->ptr_end); + npa_dump("W8: bpid_0 \t\t%d", halo->bpid_0); + npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d", halo->err_int, + halo->err_int_ena); + npa_dump("W8: thresh_int\t\t%d", halo->thresh_int); + + npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d", + halo->thresh_int_ena, halo->thresh_up); + npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n", + halo->thresh_qint_idx, halo->err_qint_idx); + npa_dump("W9: thresh \t\t%" PRIx64 "\nW9: fc_msh_dst \t\t%d", + (unsigned long)halo->thresh, halo->fc_msh_dst); + npa_dump("W9: op_dpc_ena \t\t%d\nW9: op_dpc_set \t\t%d", + halo->op_dpc_ena, halo->op_dpc_set); + npa_dump("W9: stream_ctx \t\t%d\nW9: unified_ctx \t%d", + halo->stream_ctx, halo->unified_ctx); +} + +static inline void +npa_cn20k_aura_dump(__io struct npa_cn20k_aura_s *aura) +{ + npa_dump("W0: Pool addr\t\t0x%" PRIx64 "\n", aura->pool_addr); + + npa_dump("W1: ena\t\t\t%d\nW1: pool caching\t%d", aura->ena, + aura->pool_caching); + npa_dump("W1: avg con\t\t%d\nW1: pool drop ena\t%d", aura->avg_con, + aura->pool_drop_ena); + npa_dump("W1: aura drop ena\t%d", aura->aura_drop_ena); + npa_dump("W1: bp_ena\t\t%d", aura->bp_ena); + npa_dump("W1: aura drop\t\t%d\nW1: aura shift\t\t%d", aura->aura_drop, + aura->shift); + npa_dump("W1: avg_level\t\t%d\n", aura->avg_level); + + npa_dump("W2: count\t\t%" PRIx64 "", (uint64_t)aura->count); + npa_dump("W2: bpid\t\t%d\n", aura->bpid); + + npa_dump("W3: limit\t\t%" PRIx64 "", (uint64_t)aura->limit); + npa_dump("W3: bp\t\t\t%d", aura->bp); + npa_dump("W3: fc_ena\t\t%d", aura->fc_ena); + npa_dump("W3: fc_up_crossing\t%d\nW3: fc_stype\t\t%d", + aura->fc_up_crossing, aura->fc_stype); + + npa_dump("W3: fc_hyst_bits\t%d\n", aura->fc_hyst_bits); + + npa_dump("W4: fc_addr\t\t0x%" PRIx64 "\n", aura->fc_addr); + + npa_dump("W5: pool_drop\t\t%d\nW5: update_time\t\t%d", aura->pool_drop, + aura->update_time); + npa_dump("W5: err_int\t\t%d", aura->err_int); + npa_dump("W5: err_int_ena\t\t%d\nW5: thresh_int\t\t%d", + aura->err_int_ena, aura->thresh_int); + npa_dump("W5: thresh_int_ena\t%d", aura->thresh_int_ena); + + npa_dump("W5: thresh_up\t\t%d\nW5: thresh_qint_idx\t%d", + aura->thresh_up, aura->thresh_qint_idx); + npa_dump("W5: err_qint_idx\t%d\n", aura->err_qint_idx); + + npa_dump("W6: thresh\t\t%" PRIx64 "", (uint64_t)aura->thresh); + npa_dump("W6: fc_msh_dst \t\t%d", aura->fc_msh_dst); + npa_dump("W6: op_dpc_ena \t\t%d\nW6: op_dpc_set \t\t%d", + aura->op_dpc_ena, aura->op_dpc_set); + npa_dump("W6: stream_ctx \t\t%d", aura->stream_ctx); +} + int roc_npa_ctx_dump(void) { struct npa_cn20k_aq_enq_req *aq_cn20k; + struct npa_cn20k_aq_enq_rsp *rsp_cn20k; struct npa_aq_enq_rsp *rsp; struct npa_aq_enq_req *aq; struct mbox *mbox; @@ -103,7 +264,7 @@ roc_npa_ctx_dump(void) mbox = mbox_get(lf->mbox); for (q = 0; q < lf->nr_pools; q++) { - /* Skip disabled POOL */ + /* Skip disabled AURA */ if (plt_bitmap_get(lf->npa_bmp, q)) continue; @@ -118,21 +279,34 @@ roc_npa_ctx_dump(void) goto exit; } aq->aura_id = q; - aq->ctype = NPA_AQ_CTYPE_POOL; aq->op = NPA_AQ_INSTOP_READ; + if (lf->aura_attr[q].halo) { + aq->ctype = NPA_AQ_CTYPE_HALO; + rc = mbox_process_msg(mbox, (void *)&rsp_cn20k); + } else { + aq->ctype = NPA_AQ_CTYPE_AURA; + rc = mbox_process_msg(mbox, (void *)&rsp); + } - rc = mbox_process_msg(mbox, (void *)&rsp); if (rc) { - plt_err("Failed to get pool(%d) context", q); + plt_err("Failed to get aura/halo(%d) context", q); goto exit; } - npa_dump("============== pool=%d ===============\n", q); - npa_pool_dump(&rsp->pool); + if (lf->aura_attr[q].halo) { + npa_dump("============== halo=%d ===============\n", q); + npa_halo_dump(&rsp_cn20k->halo); + } else { + npa_dump("============== aura=%d ===============\n", q); + if (roc_model_is_cn20k()) + npa_cn20k_aura_dump(&rsp_cn20k->aura); + else + npa_aura_dump(&rsp->aura); + } } for (q = 0; q < lf->nr_pools; q++) { - /* Skip disabled AURA */ - if (plt_bitmap_get(lf->npa_bmp, q)) + /* Skip halo and disabled POOL */ + if (plt_bitmap_get(lf->npa_bmp, q) || lf->aura_attr[q].halo) continue; if (roc_model_is_cn20k()) { @@ -146,16 +320,19 @@ roc_npa_ctx_dump(void) goto exit; } aq->aura_id = q; - aq->ctype = NPA_AQ_CTYPE_AURA; + aq->ctype = NPA_AQ_CTYPE_POOL; aq->op = NPA_AQ_INSTOP_READ; rc = mbox_process_msg(mbox, (void *)&rsp); if (rc) { - plt_err("Failed to get aura(%d) context", q); + plt_err("Failed to get pool(%d) context", q); goto exit; } - npa_dump("============== aura=%d ===============\n", q); - npa_aura_dump(&rsp->aura); + npa_dump("============== pool=%d ===============\n", q); + if (roc_model_is_cn20k()) + npa_cn20k_pool_dump(&rsp_cn20k->pool); + else + npa_pool_dump(&rsp->pool); } exit: diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h index 0223e4a438..e437fe831a 100644 --- a/drivers/common/cnxk/roc_npa_priv.h +++ b/drivers/common/cnxk/roc_npa_priv.h @@ -14,6 +14,8 @@ enum npa_error_status { NPA_ERR_AURA_POOL_FINI = -517, NPA_ERR_BASE_INVALID = -518, NPA_ERR_DEVICE_NOT_BOUNDED = -519, + NPA_ERR_HALO_INIT = -520, + NPA_ERR_HALO_FINI = -521, }; struct npa_lf { @@ -55,6 +57,7 @@ struct npa_aura_attr { uint64_t shift; uint64_t limit; uint8_t bp_ena; + bool halo; union { uint8_t bp; /* CN9K, CN10K */ uint8_t bp_thresh[8]; /* CN20K */ diff --git a/drivers/common/cnxk/roc_platform_base_symbols.c b/drivers/common/cnxk/roc_platform_base_symbols.c index 43095741f5..79dd18fbd7 100644 --- a/drivers/common/cnxk/roc_platform_base_symbols.c +++ b/drivers/common/cnxk/roc_platform_base_symbols.c @@ -85,6 +85,8 @@ RTE_EXPORT_INTERNAL_SYMBOL(roc_hash_sha256_gen) RTE_EXPORT_INTERNAL_SYMBOL(roc_hash_sha512_gen) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_maxpools_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_maxpools_set) +RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_halo_ena_get) +RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_halo_ena_set) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_lmt_base_addr_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_num_lmtlines_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_cpt_get) diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 1d82e5b978..b07454a7f0 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -834,8 +834,6 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, uint32_t nb_xae, uint32_t xae_waes, uint32_t xaq_buf_size, uint16_t nb_hwgrp) { - struct npa_pool_s pool; - struct npa_aura_s aura; plt_iova_t iova; uint32_t i; int rc; @@ -877,15 +875,32 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, goto free_fc; } - memset(&pool, 0, sizeof(struct npa_pool_s)); - pool.nat_align = 1; + if (roc_model_is_cn20k() && xaq->halo_ena) { + struct npa_cn20k_halo_s halo; + + memset(&halo, 0, sizeof(struct npa_cn20k_halo_s)); + halo.nat_align = 1; + halo.fc_ena = 1; + halo.fc_addr = (uint64_t)xaq->fc; + halo.fc_hyst_bits = 0; /* Store count on all updates */ + halo.unified_ctx = 1; + rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, + NULL, (struct npa_pool_s *)&halo, ROC_NPA_HALO_F); + } else { + struct npa_pool_s pool; + struct npa_aura_s aura; + + memset(&pool, 0, sizeof(struct npa_pool_s)); + pool.nat_align = 1; + + memset(&aura, 0, sizeof(aura)); + aura.fc_ena = 1; + aura.fc_addr = (uint64_t)xaq->fc; + aura.fc_hyst_bits = 0; /* Store count on all updates */ + rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, + &aura, &pool, 0); + } - memset(&aura, 0, sizeof(aura)); - aura.fc_ena = 1; - aura.fc_addr = (uint64_t)xaq->fc; - aura.fc_hyst_bits = 0; /* Store count on all updates */ - rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, - &aura, &pool, 0); if (rc) { plt_err("Failed to create XAQ pool"); goto npa_fail; diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index f1ad34bcc7..9d8356abb1 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -43,6 +43,7 @@ struct roc_sso_xaq_data { uint32_t nb_xae; uint32_t xaq_lmt; uint64_t aura_handle; + int halo_ena; void *fc; void *mem; }; -- 2.48.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 2/2] mempool/cnxk: add halo support in mempool 2025-12-05 5:51 ` [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool Nawal Kishor 2025-12-05 5:51 ` [PATCH v2 1/2] common/cnxk: add support for halos Nawal Kishor @ 2025-12-05 5:51 ` Nawal Kishor 2026-02-17 5:34 ` [PATCH v3 0/2] Add HALO support for CN20K mempool Nawal Kishor 2026-02-17 10:39 ` [PATCH v4 " Nawal Kishor 2026-01-14 6:04 ` [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool Stephen Hemminger 2 siblings, 2 replies; 18+ messages in thread From: Nawal Kishor @ 2025-12-05 5:51 UTC (permalink / raw) To: dev, Ashwin Sekhar T K, Pavan Nikhilesh; +Cc: jerinj, Nawal Kishor This patch adds the support of halos in CN20K mempool driver. It introduces a new devargs parameter "halo_ena" to enable or disable halo feature. If halo_ena is set to 1, halos will be enabled for NPA pools created by the mempool driver. Signed-off-by: Nawal Kishor <nkishor@marvell.com> --- v2: * Fixed compilation warnings. drivers/mempool/cnxk/cn10k_mempool_ops.c | 19 ++++---- drivers/mempool/cnxk/cn20k_mempool_ops.c | 60 ++++++++++++++++++++++++ drivers/mempool/cnxk/cn9k_mempool_ops.c | 2 +- drivers/mempool/cnxk/cnxk_mempool.c | 40 +++++++++++----- drivers/mempool/cnxk/cnxk_mempool.h | 16 ++++++- drivers/mempool/cnxk/cnxk_mempool_ops.c | 11 +++-- drivers/mempool/cnxk/meson.build | 1 + 7 files changed, 120 insertions(+), 29 deletions(-) create mode 100644 drivers/mempool/cnxk/cn20k_mempool_ops.c diff --git a/drivers/mempool/cnxk/cn10k_mempool_ops.c b/drivers/mempool/cnxk/cn10k_mempool_ops.c index a5be0ccafe..09f900a850 100644 --- a/drivers/mempool/cnxk/cn10k_mempool_ops.c +++ b/drivers/mempool/cnxk/cn10k_mempool_ops.c @@ -2,9 +2,6 @@ * Copyright(C) 2021 Marvell. */ -#include <rte_mempool.h> - -#include "roc_api.h" #include "cnxk_mempool.h" #define BATCH_ALLOC_SZ ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS @@ -79,7 +76,7 @@ batch_op_data_set(uint64_t pool_id, struct batch_op_data *op_data) batch_op_data_tbl[aura] = op_data; } -static int +int batch_op_init(struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -109,7 +106,7 @@ batch_op_init(struct rte_mempool *mp) return 0; } -static void +void batch_op_fini(struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -149,7 +146,7 @@ batch_op_fini(struct rte_mempool *mp) rte_wmb(); } -static int __rte_hot +int __rte_hot cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, unsigned int n) { @@ -181,7 +178,7 @@ cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, return 0; } -static unsigned int +unsigned int cn10k_mempool_get_count(const struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -326,7 +323,7 @@ mempool_deq_batch_sync(struct rte_mempool *mp, void **obj_table, unsigned int n) return count; } -static int __rte_hot +int __rte_hot cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n) { struct batch_op_data *op_data; @@ -353,7 +350,7 @@ cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n) return 0; } -static int +int cn10k_mempool_alloc(struct rte_mempool *mp) { uint32_t block_size; @@ -376,7 +373,7 @@ cn10k_mempool_alloc(struct rte_mempool *mp) block_size += padding; } - rc = cnxk_mempool_alloc(mp); + rc = cnxk_mempool_alloc(mp, 0); if (rc) return rc; @@ -392,7 +389,7 @@ cn10k_mempool_alloc(struct rte_mempool *mp) return rc; } -static void +void cn10k_mempool_free(struct rte_mempool *mp) { batch_op_fini(mp); diff --git a/drivers/mempool/cnxk/cn20k_mempool_ops.c b/drivers/mempool/cnxk/cn20k_mempool_ops.c new file mode 100644 index 0000000000..f8817d8743 --- /dev/null +++ b/drivers/mempool/cnxk/cn20k_mempool_ops.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2025 Marvell. + */ + +#include "cnxk_mempool.h" + +static int +cn20k_mempool_alloc(struct rte_mempool *mp) +{ + uint32_t block_size; + int halo_ena, rc; + size_t padding; + + block_size = mp->elt_size + mp->header_size + mp->trailer_size; + /* Align header size to ROC_ALIGN */ + if (mp->header_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(mp->header_size, ROC_ALIGN) - + mp->header_size; + mp->header_size += padding; + block_size += padding; + } + + /* Align block size to ROC_ALIGN */ + if (block_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(block_size, ROC_ALIGN) - block_size; + mp->trailer_size += padding; + block_size += padding; + } + + /* Get halo status */ + halo_ena = roc_idev_npa_halo_ena_get(); + + rc = cnxk_mempool_alloc(mp, halo_ena ? ROC_NPA_HALO_F : 0); + if (rc) + return rc; + + rc = batch_op_init(mp); + if (rc) { + plt_err("Failed to init batch alloc mem rc=%d", rc); + goto error; + } + + return 0; +error: + cnxk_mempool_free(mp); + return rc; +} + +static struct rte_mempool_ops cn20k_mempool_ops = { + .name = "cn20k_mempool_ops", + .alloc = cn20k_mempool_alloc, + .free = cn10k_mempool_free, + .enqueue = cn10k_mempool_enq, + .dequeue = cn10k_mempool_deq, + .get_count = cn10k_mempool_get_count, + .calc_mem_size = cnxk_mempool_calc_mem_size, + .populate = cnxk_mempool_populate, +}; + +RTE_MEMPOOL_REGISTER_OPS(cn20k_mempool_ops); diff --git a/drivers/mempool/cnxk/cn9k_mempool_ops.c b/drivers/mempool/cnxk/cn9k_mempool_ops.c index b7967f8085..8248071cb7 100644 --- a/drivers/mempool/cnxk/cn9k_mempool_ops.c +++ b/drivers/mempool/cnxk/cn9k_mempool_ops.c @@ -72,7 +72,7 @@ cn9k_mempool_alloc(struct rte_mempool *mp) padding = ((block_size / ROC_ALIGN) % 2) ? 0 : ROC_ALIGN; mp->trailer_size += padding; - return cnxk_mempool_alloc(mp); + return cnxk_mempool_alloc(mp, 0); } static struct rte_mempool_ops cn9k_mempool_ops = { diff --git a/drivers/mempool/cnxk/cnxk_mempool.c b/drivers/mempool/cnxk/cnxk_mempool.c index 6ff11d8004..6939fccff4 100644 --- a/drivers/mempool/cnxk/cnxk_mempool.c +++ b/drivers/mempool/cnxk/cnxk_mempool.c @@ -18,6 +18,7 @@ #define CNXK_NPA_DEV_NAME RTE_STR(cnxk_npa_dev_) #define CNXK_NPA_DEV_NAME_LEN (sizeof(CNXK_NPA_DEV_NAME) + PCI_PRI_STR_SIZE) #define CNXK_NPA_MAX_POOLS_PARAM "max_pools" +#define CNXK_NPA_HALO_ENA_PARAM "halo_ena" static inline uint32_t npa_aura_size_to_u32(uint8_t val) @@ -46,30 +47,46 @@ parse_max_pools_handler(const char *key, const char *value, void *extra_args) return 0; } -static inline uint32_t -parse_max_pools(struct rte_devargs *devargs) +static int +parse_halo_ena_handler(const char *key, const char *value, void *extra_args) +{ + RTE_SET_USED(key); + uint8_t val; + + val = atoi(value); + if (val != 0 && val != 1) + return -EINVAL; + + *(uint8_t *)extra_args = val; + return 0; +} + +static int +cnxk_mempool_plt_parse_devargs(struct rte_pci_device *pci_dev) { uint32_t max_pools = npa_aura_size_to_u32(NPA_AURA_SZ_128); + struct rte_devargs *devargs = pci_dev->device.devargs; struct rte_kvargs *kvlist; + uint32_t halo_ena = 0; if (devargs == NULL) - goto exit; + goto null_devargs; kvlist = rte_kvargs_parse(devargs->args, NULL); if (kvlist == NULL) goto exit; rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM, &parse_max_pools_handler, &max_pools); + rte_kvargs_process(kvlist, CNXK_NPA_HALO_ENA_PARAM, + &parse_halo_ena_handler, &halo_ena); rte_kvargs_free(kvlist); -exit: - return max_pools; -} -static int -cnxk_mempool_plt_parse_devargs(struct rte_pci_device *pci_dev) -{ - roc_idev_npa_maxpools_set(parse_max_pools(pci_dev->device.devargs)); +null_devargs: + roc_idev_npa_maxpools_set(max_pools); + roc_idev_npa_halo_ena_set(halo_ena); return 0; +exit: + return -EINVAL; } static inline char * @@ -201,7 +218,8 @@ RTE_PMD_REGISTER_PCI(mempool_cnxk, npa_pci); RTE_PMD_REGISTER_PCI_TABLE(mempool_cnxk, npa_pci_map); RTE_PMD_REGISTER_KMOD_DEP(mempool_cnxk, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(mempool_cnxk, - CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>"); + CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>" + CNXK_NPA_HALO_ENA_PARAM "=<0-1>"); RTE_INIT(cnxk_mempool_parse_devargs) { diff --git a/drivers/mempool/cnxk/cnxk_mempool.h b/drivers/mempool/cnxk/cnxk_mempool.h index 669e617952..941290061e 100644 --- a/drivers/mempool/cnxk/cnxk_mempool.h +++ b/drivers/mempool/cnxk/cnxk_mempool.h @@ -7,6 +7,8 @@ #include <rte_mempool.h> +#include "roc_api.h" + enum cnxk_mempool_flags { /* This flag is used to ensure that only aura zero is allocated. * If aura zero is not available, then mempool creation fails. @@ -47,7 +49,7 @@ int cnxk_mempool_populate(struct rte_mempool *mp, unsigned int max_objs, void *vaddr, rte_iova_t iova, size_t len, rte_mempool_populate_obj_cb_t *obj_cb, void *obj_cb_arg); -int cnxk_mempool_alloc(struct rte_mempool *mp); +int cnxk_mempool_alloc(struct rte_mempool *mp, uint64_t roc_flags); void cnxk_mempool_free(struct rte_mempool *mp); int __rte_hot cnxk_mempool_enq(struct rte_mempool *mp, void *const *obj_table, @@ -55,6 +57,16 @@ int __rte_hot cnxk_mempool_enq(struct rte_mempool *mp, void *const *obj_table, int __rte_hot cnxk_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n); +int batch_op_init(struct rte_mempool *mp); +void batch_op_fini(struct rte_mempool *mp); +int __rte_hot cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, + unsigned int n); +unsigned int cn10k_mempool_get_count(const struct rte_mempool *mp); +int __rte_hot cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, + unsigned int n); +int cn10k_mempool_alloc(struct rte_mempool *mp); +void cn10k_mempool_free(struct rte_mempool *mp); + int cn10k_mempool_plt_init(void); -#endif +#endif /* _CNXK_MEMPOOL_H_ */ diff --git a/drivers/mempool/cnxk/cnxk_mempool_ops.c b/drivers/mempool/cnxk/cnxk_mempool_ops.c index 5c7fcea487..01b6247fbb 100644 --- a/drivers/mempool/cnxk/cnxk_mempool_ops.c +++ b/drivers/mempool/cnxk/cnxk_mempool_ops.c @@ -70,9 +70,9 @@ cnxk_mempool_calc_mem_size(const struct rte_mempool *mp, uint32_t obj_num, } int -cnxk_mempool_alloc(struct rte_mempool *mp) +cnxk_mempool_alloc(struct rte_mempool *mp, uint64_t roc_flags) { - uint32_t block_count, flags, roc_flags = 0; + uint32_t block_count, flags; uint64_t aura_handle = 0; struct npa_aura_s aura; struct npa_pool_s pool; @@ -98,7 +98,7 @@ cnxk_mempool_alloc(struct rte_mempool *mp) flags = CNXK_MEMPOOL_FLAGS(mp); if (flags & CNXK_MEMPOOL_F_ZERO_AURA) { - roc_flags = ROC_NPA_ZERO_AURA_F; + roc_flags |= ROC_NPA_ZERO_AURA_F; } else if (flags & CNXK_MEMPOOL_F_CUSTOM_AURA) { struct npa_aura_s *paura; @@ -192,9 +192,12 @@ cnxk_mempool_plt_init(void) if (roc_model_is_cn9k()) { rte_mbuf_set_platform_mempool_ops("cn9k_mempool_ops"); - } else if (roc_model_is_cn10k() || roc_model_is_cn20k()) { + } else if (roc_model_is_cn10k()) { rte_mbuf_set_platform_mempool_ops("cn10k_mempool_ops"); rc = cn10k_mempool_plt_init(); + } else if (roc_model_is_cn20k()) { + rte_mbuf_set_platform_mempool_ops("cn20k_mempool_ops"); + rc = cn10k_mempool_plt_init(); } return rc; } diff --git a/drivers/mempool/cnxk/meson.build b/drivers/mempool/cnxk/meson.build index e388cce26a..7722264320 100644 --- a/drivers/mempool/cnxk/meson.build +++ b/drivers/mempool/cnxk/meson.build @@ -14,6 +14,7 @@ sources = files( 'cnxk_mempool_telemetry.c', 'cn9k_mempool_ops.c', 'cn10k_mempool_ops.c', + 'cn20k_mempool_ops.c', 'cn10k_hwpool_ops.c', ) -- 2.48.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 0/2] Add HALO support for CN20K mempool 2025-12-05 5:51 ` [PATCH v2 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor @ 2026-02-17 5:34 ` Nawal Kishor 2026-02-17 5:34 ` [PATCH v3 1/2] common/cnxk: add support for halos Nawal Kishor ` (2 more replies) 2026-02-17 10:39 ` [PATCH v4 " Nawal Kishor 1 sibling, 3 replies; 18+ messages in thread From: Nawal Kishor @ 2026-02-17 5:34 UTC (permalink / raw) To: dev; +Cc: jerinj, asekhar, Nawal Kishor This series of patches adds support for HALO in CNXK mempool driver. Changes in v3: * Added documentation for HALO support in CNXK mempool driver. Nawal Kishor (2): common/cnxk: add support for halos mempool/cnxk: add halo support in mempool doc/guides/mempool/cnxk.rst | 24 +- drivers/common/cnxk/hw/npa.h | 81 ++++++ drivers/common/cnxk/roc_idev.c | 25 ++ drivers/common/cnxk/roc_idev.h | 3 + drivers/common/cnxk/roc_idev_priv.h | 1 + drivers/common/cnxk/roc_mbox.h | 6 + drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 46 ++- drivers/common/cnxk/roc_npa.c | 268 ++++++++++++++++-- drivers/common/cnxk/roc_npa.h | 20 +- drivers/common/cnxk/roc_npa_debug.c | 201 ++++++++++++- drivers/common/cnxk/roc_npa_priv.h | 3 + .../common/cnxk/roc_platform_base_symbols.c | 2 + drivers/common/cnxk/roc_sso.c | 35 ++- drivers/common/cnxk/roc_sso.h | 1 + drivers/mempool/cnxk/cn10k_mempool_ops.c | 19 +- drivers/mempool/cnxk/cn20k_mempool_ops.c | 60 ++++ drivers/mempool/cnxk/cn9k_mempool_ops.c | 2 +- drivers/mempool/cnxk/cnxk_mempool.c | 40 ++- drivers/mempool/cnxk/cnxk_mempool.h | 16 +- drivers/mempool/cnxk/cnxk_mempool_ops.c | 11 +- drivers/mempool/cnxk/meson.build | 1 + 22 files changed, 771 insertions(+), 95 deletions(-) create mode 100644 drivers/mempool/cnxk/cn20k_mempool_ops.c -- 2.48.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 1/2] common/cnxk: add support for halos 2026-02-17 5:34 ` [PATCH v3 0/2] Add HALO support for CN20K mempool Nawal Kishor @ 2026-02-17 5:34 ` Nawal Kishor 2026-02-17 5:34 ` [PATCH v3 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor 2026-02-17 8:43 ` [PATCH v3 0/2] Add HALO support for CN20K mempool Jerin Jacob 2 siblings, 0 replies; 18+ messages in thread From: Nawal Kishor @ 2026-02-17 5:34 UTC (permalink / raw) To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao, Harman Kalra Cc: jerinj, asekhar, Nawal Kishor In cn9k/cn10k, NPA mempool creation required the creation of at least one aura and pool context. Even, if the mapping between aura and pool was 1:1 (i.e, one aura mapped to one pool), separate contexts were required for aura and pool. This wasted the context space and most of common use case for NPA mempool is 1:1 mapping between aura and pool. In cn20k, 1:1 aura pool mapping can now be replaced by using halos. Halos allow the creation of only one context which contains the information required for both aura and pool. This patch adds the support for creation of Halos in ROC. Signed-off-by: Nawal Kishor <nkishor@marvell.com> --- drivers/common/cnxk/hw/npa.h | 81 ++++++ drivers/common/cnxk/roc_idev.c | 25 ++ drivers/common/cnxk/roc_idev.h | 3 + drivers/common/cnxk/roc_idev_priv.h | 1 + drivers/common/cnxk/roc_mbox.h | 6 + drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 46 ++- drivers/common/cnxk/roc_npa.c | 268 ++++++++++++++++-- drivers/common/cnxk/roc_npa.h | 20 +- drivers/common/cnxk/roc_npa_debug.c | 201 ++++++++++++- drivers/common/cnxk/roc_npa_priv.h | 3 + .../common/cnxk/roc_platform_base_symbols.c | 2 + drivers/common/cnxk/roc_sso.c | 35 ++- drivers/common/cnxk/roc_sso.h | 1 + 14 files changed, 630 insertions(+), 63 deletions(-) diff --git a/drivers/common/cnxk/hw/npa.h b/drivers/common/cnxk/hw/npa.h index 4fd1f9a64b..e421c70e01 100644 --- a/drivers/common/cnxk/hw/npa.h +++ b/drivers/common/cnxk/hw/npa.h @@ -118,6 +118,7 @@ #define NPA_AQ_CTYPE_AURA (0x0ull) #define NPA_AQ_CTYPE_POOL (0x1ull) +#define NPA_AQ_CTYPE_HALO (0x2ull) #define NPA_BPINTF_NIX0_RX (0x0ull) #define NPA_BPINTF_NIX1_RX (0x1ull) @@ -456,6 +457,86 @@ struct npa_cn20k_pool_s { uint64_t rsvd_1023_960 : 64; /* W15 */ }; +/* NPA halo context structure [CN20K] */ +struct npa_cn20k_halo_s { + uint64_t stack_base : 64; /* W0 */ + uint64_t ena : 1; /* W1 */ + uint64_t nat_align : 1; + uint64_t reserved_67_66 : 2; + uint64_t stack_caching : 1; + uint64_t reserved_71_69 : 3; + uint64_t aura_drop_ena : 1; + uint64_t reserved_79_73 : 7; + uint64_t aura_drop : 8; + uint64_t buf_offset : 12; + uint64_t reserved_103_100 : 4; + uint64_t buf_size : 12; + uint64_t reserved_119_116 : 4; + uint64_t ref_cnt_prof : 3; + uint64_t reserved_127_123 : 5; + uint64_t stack_max_pages : 32; /* W2 */ + uint64_t stack_pages : 32; + uint64_t bp_0 : 7; /* W3 */ + uint64_t bp_1 : 7; + uint64_t bp_2 : 7; + uint64_t bp_3 : 7; + uint64_t bp_4 : 7; + uint64_t bp_5 : 7; + uint64_t bp_6 : 7; + uint64_t bp_7 : 7; + uint64_t bp_ena_0 : 1; + uint64_t bp_ena_1 : 1; + uint64_t bp_ena_2 : 1; + uint64_t bp_ena_3 : 1; + uint64_t bp_ena_4 : 1; + uint64_t bp_ena_5 : 1; + uint64_t bp_ena_6 : 1; + uint64_t bp_ena_7 : 1; + uint64_t stack_offset : 4; /* W4 */ + uint64_t reserved_263_260 : 4; + uint64_t shift : 6; + uint64_t reserved_271_270 : 2; + uint64_t avg_level : 8; + uint64_t avg_con : 9; + uint64_t fc_ena : 1; + uint64_t fc_stype : 2; + uint64_t fc_hyst_bits : 4; + uint64_t fc_up_crossing : 1; + uint64_t reserved_299_297 : 3; + uint64_t update_time : 16; + uint64_t reserved_319_316 : 4; + uint64_t fc_addr : 64; /* W5 */ + uint64_t ptr_start : 64; /* W6 */ + uint64_t ptr_end : 64; /* W7 */ + uint64_t bpid_0 : 12; /* W8 */ + uint64_t reserved_535_524 : 12; + uint64_t err_int : 8; + uint64_t err_int_ena : 8; + uint64_t thresh_int : 1; + uint64_t thresh_int_ena : 1; + uint64_t thresh_up : 1; + uint64_t reserved_555_555 : 1; + uint64_t thresh_qint_idx : 7; + uint64_t reserved_563_563 : 1; + uint64_t err_qint_idx : 7; + uint64_t reserved_575_571 : 5; + uint64_t thresh : 36; /* W9 */ + uint64_t reserved_615_612 : 4; + uint64_t fc_msh_dst : 11; + uint64_t reserved_630_627 : 4; + uint64_t op_dpc_ena : 1; + uint64_t op_dpc_set : 5; + uint64_t reserved_637_637 : 1; + uint64_t stream_ctx : 1; + uint64_t unified_ctx : 1; + uint64_t reserved_703_640 : 64; /* W10 */ + uint64_t reserved_767_704 : 64; /* W11 */ + uint64_t reserved_831_768 : 64; /* W12 */ + uint64_t reserved_895_832 : 64; /* W13 */ + uint64_t reserved_959_896 : 64; /* W14 */ + uint64_t reserved_1023_960 : 64; /* W15 */ +}; + /* NPA queue interrupt context hardware structure */ struct npa_qint_hw_s { uint32_t count : 22; diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c index 84812f73e0..6aa5b10ee9 100644 --- a/drivers/common/cnxk/roc_idev.c +++ b/drivers/common/cnxk/roc_idev.c @@ -33,6 +33,7 @@ idev_set_defaults(struct idev_cfg *idev) idev->npa = NULL; idev->npa_pf_func = 0; idev->max_pools = 128; + idev->halo_ena = 0; idev->lmt_pf_func = 0; idev->lmt_base_addr = 0; idev->num_lmtlines = 0; @@ -123,6 +124,30 @@ roc_idev_npa_maxpools_set(uint32_t max_pools) __atomic_store_n(&idev->max_pools, max_pools, __ATOMIC_RELEASE); } +int +roc_idev_npa_halo_ena_get(void) +{ + struct idev_cfg *idev; + int halo_ena; + + idev = idev_get_cfg(); + halo_ena = 0; + if (idev != NULL) + halo_ena = __atomic_load_n(&idev->halo_ena, __ATOMIC_ACQUIRE); + + return halo_ena; +} + +void +roc_idev_npa_halo_ena_set(int halo_ena) +{ + struct idev_cfg *idev; + + idev = idev_get_cfg(); + if (idev != NULL) + __atomic_store_n(&idev->halo_ena, halo_ena, __ATOMIC_RELEASE); +} + uint16_t idev_npa_lf_active(struct dev *dev) { diff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h index 6edb5f83b2..3803963b07 100644 --- a/drivers/common/cnxk/roc_idev.h +++ b/drivers/common/cnxk/roc_idev.h @@ -8,6 +8,9 @@ uint32_t __roc_api roc_idev_npa_maxpools_get(void); void __roc_api roc_idev_npa_maxpools_set(uint32_t max_pools); +int __roc_api roc_idev_npa_halo_ena_get(void); +void __roc_api roc_idev_npa_halo_ena_set(int halo_ena); + /* LMT */ uint64_t __roc_api roc_idev_lmt_base_addr_get(void); uint16_t __roc_api roc_idev_num_lmtlines_get(void); diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h index 98b6286bfe..dde555535b 100644 --- a/drivers/common/cnxk/roc_idev_priv.h +++ b/drivers/common/cnxk/roc_idev_priv.h @@ -30,6 +30,7 @@ struct idev_cfg { struct npa_lf *npa; uint16_t npa_refcnt; uint32_t max_pools; + int halo_ena; uint16_t lmt_pf_func; uint16_t num_lmtlines; uint64_t lmt_base_addr; diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 3e913fa13c..3176c87382 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1397,6 +1397,8 @@ struct npa_cn20k_aq_enq_req { __io struct npa_cn20k_aura_s aura; /* Valid when op == WRITE/INIT and ctype == POOL */ __io struct npa_cn20k_pool_s pool; + /* Valid when op == WRITE/INIT and ctype == HALO */ + __io struct npa_cn20k_halo_s halo; }; /* Mask data when op == WRITE (1=write, 0=don't write) */ union { @@ -1404,6 +1406,8 @@ struct npa_cn20k_aq_enq_req { __io struct npa_cn20k_aura_s aura_mask; /* Valid when op == WRITE and ctype == POOL */ __io struct npa_cn20k_pool_s pool_mask; + /* Valid when op == WRITE/INIT and ctype == HALO */ + __io struct npa_cn20k_halo_s halo_mask; }; }; @@ -1414,6 +1418,8 @@ struct npa_cn20k_aq_enq_rsp { __io struct npa_cn20k_aura_s aura; /* Valid when op == READ and ctype == POOL */ __io struct npa_cn20k_pool_s pool; + /* Valid when op == READ and ctype == HALO */ + __io struct npa_cn20k_halo_s halo; }; }; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 326decde2b..aa197eb95e 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -595,6 +595,7 @@ struct roc_nix { uintptr_t lmt_base; bool io_enabled; bool rx_ptp_ena; + bool sqb_halo_ena; uint16_t cints; uint32_t buf_sz; uint64_t meta_aura_handle; diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index c7e37abf32..a6f487fe08 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -1486,8 +1486,6 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); uint16_t sqes_per_sqb, count, nb_sqb_bufs; - struct npa_pool_s pool; - struct npa_aura_s aura; uint64_t blk_sz; uint64_t iova; int rc; @@ -1509,20 +1507,38 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) /* Explicitly set nat_align alone as by default pool is with both * nat_align and buf_offset = 1 which we don't want for SQB. */ - memset(&pool, 0, sizeof(struct npa_pool_s)); - pool.nat_align = 1; + if (roc_model_is_cn20k() && roc_nix->sqb_halo_ena) { + struct npa_cn20k_halo_s halo; + + memset(&halo, 0, sizeof(struct npa_cn20k_halo_s)); + halo.nat_align = 1; + halo.fc_ena = 1; + halo.fc_stype = 0x3; /* STSTP */ + halo.fc_addr = (uint64_t)sq->fc; + halo.fc_hyst_bits = 0; /* Store count on all updates */ + halo.unified_ctx = 1; + rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, NULL, + (struct npa_pool_s *)&halo, ROC_NPA_HALO_F); + } else { + struct npa_pool_s pool; + struct npa_aura_s aura; + + memset(&pool, 0, sizeof(struct npa_pool_s)); + pool.nat_align = 1; + + memset(&aura, 0, sizeof(aura)); + /* Disable SQ pool FC updates when SQ count updates are used */ + if (!sq->sq_cnt_ptr) + aura.fc_ena = 1; + if (roc_model_is_cn9k() || roc_errata_npa_has_no_fc_stype_ststp()) + aura.fc_stype = 0x0; /* STF */ + else + aura.fc_stype = 0x3; /* STSTP */ + aura.fc_addr = (uint64_t)sq->fc; + aura.fc_hyst_bits = sq->fc_hyst_bits & 0xF; + rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0); + } - memset(&aura, 0, sizeof(aura)); - /* Disable SQ pool FC updates when SQ count updates are used */ - if (!sq->sq_cnt_ptr) - aura.fc_ena = 1; - if (roc_model_is_cn9k() || roc_errata_npa_has_no_fc_stype_ststp()) - aura.fc_stype = 0x0; /* STF */ - else - aura.fc_stype = 0x3; /* STSTP */ - aura.fc_addr = (uint64_t)sq->fc; - aura.fc_hyst_bits = sq->fc_hyst_bits & 0xF; - rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0); if (rc) goto fail; diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index f9824f6656..e8df8ad077 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -82,7 +82,6 @@ static int npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura, struct npa_pool_s *pool) { - struct npa_cn20k_aq_enq_req *aura_init_req_cn20k, *pool_init_req_cn20k; struct npa_aq_enq_req *aura_init_req, *pool_init_req; struct npa_aq_enq_rsp *aura_init_rsp, *pool_init_rsp; struct mbox_dev *mdev = &m_box->dev[0]; @@ -91,6 +90,7 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; aura_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_init_req = (struct npa_aq_enq_req *)aura_init_req_cn20k; } else { @@ -104,6 +104,7 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura mbox_memcpy(&aura_init_req->aura, aura, sizeof(*aura)); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *pool_init_req_cn20k; pool_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); pool_init_req = (struct npa_aq_enq_req *)pool_init_req_cn20k; } else { @@ -139,7 +140,6 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura static int npa_aura_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura) { - struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; struct npa_aq_enq_req *aura_init_req; struct npa_aq_enq_rsp *aura_init_rsp; struct mbox *mbox; @@ -147,6 +147,7 @@ npa_aura_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura) mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; aura_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_init_req = (struct npa_aq_enq_req *)aura_init_req_cn20k; } else { @@ -209,10 +210,92 @@ npa_pool_multi_bp_reset(struct npa_cn20k_aq_enq_req *pool_req) pool_req->pool_mask.bp_ena_7 = ~(pool_req->pool_mask.bp_ena_7); } +static int +npa_halo_init(struct mbox *m_box, uint32_t aura_id, struct npa_cn20k_halo_s *halo) +{ + struct npa_cn20k_aq_enq_req *req; + struct npa_aq_enq_rsp *rsp; + struct mbox *mbox; + int rc = -ENOSPC; + + mbox = mbox_get(m_box); + req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); + if (req == NULL) + goto exit; + req->aura_id = aura_id; + req->ctype = NPA_AQ_CTYPE_HALO; + req->op = NPA_AQ_INSTOP_INIT; + mbox_memcpy(&req->halo, halo, sizeof(*halo)); + + rc = mbox_process_msg(mbox, (void **)&rsp); + if (rc < 0) + goto exit; + + if (rsp->hdr.rc == 0) + rc = 0; + else + rc = NPA_ERR_HALO_INIT; +exit: + mbox_put(mbox); + return rc; +} + +static int +npa_halo_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) +{ + struct mbox_dev *mdev = &m_box->dev[0]; + struct npa_cn20k_aq_enq_req *req; + struct npa_aq_enq_rsp *rsp; + int rc = -ENOSPC, off; + struct mbox *mbox; + uint64_t ptr; + + /* Procedure for disabling an aura/pool */ + plt_delay_us(10); + + /* Clear all the pointers from the aura */ + do { + ptr = roc_npa_aura_op_alloc(aura_handle, 0); + } while (ptr); + + mbox = mbox_get(m_box); + req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); + if (req == NULL) + goto exit; + + /* Disable backpressure on halo on CN20K */ + if (roc_model_is_cn20k()) + npa_pool_multi_bp_reset(req); + + req->aura_id = aura_id; + req->ctype = NPA_AQ_CTYPE_HALO; + req->op = NPA_AQ_INSTOP_WRITE; + req->halo.ena = 0; + req->halo_mask.ena = ~req->halo_mask.ena; + + rc = mbox_process(mbox); + if (rc < 0) + goto exit; + + off = mbox->rx_start + + PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); + rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off); + + if (rsp->hdr.rc != 0) { + rc = NPA_ERR_HALO_FINI; + goto exit; + } + + rc = 0; +exit: + mbox_put(mbox); + return rc; +} + static int npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k, *pool_req_cn20k = NULL; + struct npa_cn20k_aq_enq_req *pool_req_cn20k = NULL; struct npa_aq_enq_req *aura_req, *pool_req; struct npa_aq_enq_rsp *aura_rsp, *pool_rsp; struct mbox_dev *mdev = &m_box->dev[0]; @@ -249,6 +332,7 @@ npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) pool_req->pool_mask.ena = ~pool_req->pool_mask.ena; if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -318,7 +402,6 @@ npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) static int npa_aura_fini(struct mbox *m_box, uint32_t aura_id) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_aq_enq_rsp *aura_rsp; struct ndc_sync_op *ndc_req; @@ -330,6 +413,7 @@ npa_aura_fini(struct mbox *m_box, uint32_t aura_id) mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -439,10 +523,10 @@ roc_npa_pool_op_pc_reset(uint64_t aura_handle) int roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_lf *lf; struct mbox *mbox; + uint64_t aura_id; int rc; lf = idev_npa_obj_get(); @@ -450,6 +534,7 @@ roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) return NPA_ERR_DEVICE_NOT_BOUNDED; mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -459,8 +544,12 @@ roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) rc = -ENOMEM; goto exit; } - aura_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle); - aura_req->ctype = NPA_AQ_CTYPE_AURA; + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + aura_req->aura_id = aura_id; + if (lf->aura_attr[aura_id].halo) + aura_req->ctype = NPA_AQ_CTYPE_HALO; + else + aura_req->ctype = NPA_AQ_CTYPE_AURA; aura_req->op = NPA_AQ_INSTOP_WRITE; aura_req->aura.aura_drop_ena = ena; @@ -575,7 +664,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, /* Block size should be cache line aligned and in range of 128B-128KB */ if (block_size % ROC_ALIGN || block_size < 128 || - block_size > ROC_NPA_MAX_BLOCK_SZ) + block_size > roc_npa_max_block_size()) return NPA_ERR_INVALID_BLOCK_SZ; /* Get aura_id from resource bitmap */ @@ -627,11 +716,21 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, /* Update pool fields */ pool->stack_base = mz->iova; pool->ena = 1; + /* In opaque mode buffer size must be 0 */ - if (!pool->nat_align) + if (!pool->nat_align) { pool->buf_size = 0; - else - pool->buf_size = block_size / ROC_ALIGN; + } else { + uint64_t buf_sz = block_size / ROC_ALIGN; + if (roc_model_is_cn20k()) { + __io struct npa_cn20k_pool_s *cn20k_pool = + (__io struct npa_cn20k_pool_s *)pool; + cn20k_pool->buf_size = buf_sz; + } else { + pool->buf_size = buf_sz; + } + } + pool->stack_max_pages = stack_size; pool->shift = plt_log2_u32(block_count); pool->shift = pool->shift < 8 ? 0 : pool->shift - 8; @@ -653,6 +752,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, lf->aura_attr[aura_id].shift = aura->shift; lf->aura_attr[aura_id].limit = aura->limit; + lf->aura_attr[aura_id].halo = 0; *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); /* Update aura count */ roc_npa_aura_op_cnt_set(*aura_handle, 0, block_count); @@ -671,6 +771,86 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, return rc; } +static int +npa_halo_alloc(struct npa_lf *lf, const uint32_t block_size, const uint32_t block_count, + struct npa_cn20k_halo_s *halo, uint64_t *aura_handle, uint32_t flags) +{ + int rc, aura_id, stack_size, alloc_size, pool_id; + char name[PLT_MEMZONE_NAMESIZE]; + const struct plt_memzone *mz; + + /* Sanity check */ + if (!lf || !halo || !aura_handle) + return NPA_ERR_PARAM; + + roc_npa_dev_lock(); + /* Get aura_id from resource bitmap */ + aura_id = find_free_aura(lf, flags); + if (aura_id < 0) { + roc_npa_dev_unlock(); + return NPA_ERR_AURA_ID_ALLOC; + } + + /* Mark aura as reserved */ + plt_bitmap_clear(lf->npa_bmp, aura_id); + + roc_npa_dev_unlock(); + rc = (aura_id < 0 || aura_id >= (int)BIT_ULL(6 + lf->aura_sz)) ? NPA_ERR_AURA_ID_ALLOC : 0; + if (rc) + goto exit; + + /* Allocate stack memory */ + stack_size = (block_count + lf->stack_pg_ptrs - 1) / lf->stack_pg_ptrs; + alloc_size = stack_size * lf->stack_pg_bytes; + + pool_id = aura_id; + mz = npa_stack_dma_alloc(lf, name, pool_id, alloc_size); + if (mz == NULL) { + rc = NPA_ERR_ALLOC; + goto aura_res_put; + } + + /* Update halo fields */ + halo->ena = 1; + halo->shift = plt_log2_u32(block_count); + halo->shift = halo->shift < 8 ? 0 : halo->shift - 8; + halo->err_int_ena = BIT(NPA_AURA_ERR_INT_AURA_ADD_OVER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS); + halo->avg_con = 0; + /* Many to one reduction */ + halo->err_qint_idx = aura_id % lf->qints; + halo->stack_base = mz->iova; + /* In opaque mode buffer size must be 0 */ + halo->buf_size = !halo->nat_align ? 0 : block_size / ROC_ALIGN; + halo->stack_max_pages = stack_size; + halo->ptr_start = 0; + halo->ptr_end = ~0; + halo->stack_caching = 1; + halo->unified_ctx = 1; + + /* Issue HALO_INIT op */ + rc = npa_halo_init(lf->mbox, aura_id, halo); + if (rc) + goto stack_mem_free; + + lf->aura_attr[aura_id].shift = halo->shift; + lf->aura_attr[aura_id].halo = 1; + *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); + + return 0; + +stack_mem_free: + plt_memzone_free(mz); +aura_res_put: + roc_npa_dev_lock(); + plt_bitmap_set(lf->npa_bmp, aura_id); + roc_npa_dev_unlock(); +exit: + return rc; +} + int roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, uint32_t block_count, struct npa_aura_s *aura, @@ -713,10 +893,21 @@ roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, if (flags & ROC_NPA_FORCE_OPAQUE_MODE_F) pool->nat_align = 0; - rc = npa_aura_pool_pair_alloc(lf, block_size, block_count, aura, pool, - aura_handle, flags); + /* The pool argument will be a pointer to a npa_cn20k_halo_s structure + * when ROC_NPA_HALO_F flag is set. Note that halo and pool contexts + * are same in size and the fields that are modified here are 1:1 + * mapped in these structures. + */ + if (roc_model_is_cn20k() && (flags & ROC_NPA_HALO_F)) { + struct npa_cn20k_halo_s *halo = (struct npa_cn20k_halo_s *)pool; + rc = npa_halo_alloc(lf, block_size, block_count, halo, aura_handle, flags); + } else { + rc = npa_aura_pool_pair_alloc(lf, block_size, block_count, aura, pool, + aura_handle, flags); + } + if (rc) { - plt_err("Failed to alloc pool or aura rc=%d", rc); + plt_err("Failed to alloc pool/aura/halo rc=%d", rc); goto error; } @@ -773,7 +964,7 @@ npa_aura_alloc(struct npa_lf *lf, const uint32_t block_count, int pool_id, /* Many to one reduction */ aura->err_qint_idx = aura_id % lf->qints; - /* Issue AURA_INIT and POOL_INIT op */ + /* Issue AURA_INIT op */ rc = npa_aura_init(lf->mbox, aura_id, aura); if (rc) return rc; @@ -836,7 +1027,6 @@ roc_npa_aura_create(uint64_t *aura_handle, uint32_t block_count, int roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_lf *lf; struct mbox *mbox; @@ -848,6 +1038,7 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -872,6 +1063,28 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) return rc; } +static int +npa_halo_free(struct npa_lf *lf, uint64_t aura_handle) +{ + char name[PLT_MEMZONE_NAMESIZE]; + int aura_id, pool_id, rc; + + if (!lf || !aura_handle) + return NPA_ERR_PARAM; + + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + pool_id = aura_id; + rc = npa_halo_fini(lf->mbox, aura_id, aura_handle); + rc |= npa_stack_dma_free(lf, name, pool_id); + memset(&lf->aura_attr[aura_id], 0, sizeof(struct npa_aura_attr)); + + roc_npa_dev_lock(); + plt_bitmap_set(lf->npa_bmp, aura_id); + roc_npa_dev_unlock(); + + return rc; +} + static int npa_aura_pool_pair_free(struct npa_lf *lf, uint64_t aura_handle) { @@ -898,12 +1111,18 @@ int roc_npa_pool_destroy(uint64_t aura_handle) { struct npa_lf *lf = idev_npa_obj_get(); - int rc = 0; + int rc = 0, aura_id; plt_npa_dbg("lf=%p aura_handle=0x%" PRIx64, lf, aura_handle); - rc = npa_aura_pool_pair_free(lf, aura_handle); + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + + if (lf->aura_attr[aura_id].halo) + rc = npa_halo_free(lf, aura_handle); + else + rc = npa_aura_pool_pair_free(lf, aura_handle); + if (rc) - plt_err("Failed to destroy pool or aura rc=%d", rc); + plt_err("Failed to destroy pool/aura/halo rc=%d", rc); /* Release the reference of npa */ rc |= npa_lf_fini(); @@ -952,14 +1171,13 @@ roc_npa_aura_destroy(uint64_t aura_handle) int roc_npa_pool_range_update_check(uint64_t aura_handle) { - uint64_t aura_id = roc_npa_aura_handle_to_aura(aura_handle); - struct npa_cn20k_aq_enq_req *req_cn20k; __io struct npa_pool_s *pool; struct npa_aq_enq_req *req; struct npa_aq_enq_rsp *rsp; struct npa_aura_lim *lim; struct mbox *mbox; struct npa_lf *lf; + uint64_t aura_id; int rc; lf = idev_npa_obj_get(); @@ -970,6 +1188,7 @@ roc_npa_pool_range_update_check(uint64_t aura_handle) mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *req_cn20k; req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); req = (struct npa_aq_enq_req *)req_cn20k; } else { @@ -980,8 +1199,12 @@ roc_npa_pool_range_update_check(uint64_t aura_handle) goto exit; } + aura_id = roc_npa_aura_handle_to_aura(aura_handle); req->aura_id = aura_id; - req->ctype = NPA_AQ_CTYPE_POOL; + if (lf->aura_attr[aura_id].halo) + req->ctype = NPA_AQ_CTYPE_HALO; + else + req->ctype = NPA_AQ_CTYPE_POOL; req->op = NPA_AQ_INSTOP_READ; rc = mbox_process_msg(mbox, (void *)&rsp); @@ -1140,7 +1363,6 @@ int roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf, uint8_t bp_thresh, bool enable) { - /* TODO: Add support for CN20K */ uint32_t aura_id = roc_npa_aura_handle_to_aura(aura_handle); struct npa_lf *lf = idev_npa_obj_get(); struct npa_aq_enq_req *req; diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 336a43f95c..18808e5873 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -21,7 +21,9 @@ #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1) -#define ROC_NPA_MAX_BLOCK_SZ (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN9K (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN10K (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN20K (256 * 1024) #define ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS 512 #define ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS 15U #define ROC_CN10K_NPA_BATCH_FREE_BURST_MAX 16U @@ -36,6 +38,17 @@ */ #define ROC_CN9K_NPA_BULK_ALLOC_MAX_PTRS 30 +static inline uint32_t +roc_npa_max_block_size(void) +{ + if (roc_model_is_cn20k()) + return ROC_NPA_MAX_BLOCK_SZ_CN20K; + else if (roc_model_is_cn10k()) + return ROC_NPA_MAX_BLOCK_SZ_CN10K; + else + return ROC_NPA_MAX_BLOCK_SZ_CN9K; +} + /* * Generate 64bit handle to have optimized alloc and free aura operation. * 0 - ROC_AURA_ID_MASK for storing the aura_id. @@ -767,8 +780,9 @@ int __roc_api roc_npa_dev_init(struct roc_npa *roc_npa); int __roc_api roc_npa_dev_fini(struct roc_npa *roc_npa); /* Flags to pool create */ -#define ROC_NPA_ZERO_AURA_F BIT(0) -#define ROC_NPA_FORCE_OPAQUE_MODE_F BIT(1) +#define ROC_NPA_ZERO_AURA_F BIT(0) +#define ROC_NPA_FORCE_OPAQUE_MODE_F BIT(1) +#define ROC_NPA_HALO_F BIT(2) /* Enumerations */ enum roc_npa_buf_type { diff --git a/drivers/common/cnxk/roc_npa_debug.c b/drivers/common/cnxk/roc_npa_debug.c index 9a16f481a8..e64696730f 100644 --- a/drivers/common/cnxk/roc_npa_debug.c +++ b/drivers/common/cnxk/roc_npa_debug.c @@ -86,10 +86,171 @@ npa_aura_dump(__io struct npa_aura_s *aura) npa_dump("W6: thresh\t\t%" PRIx64 "\n", (uint64_t)aura->thresh); } +static inline void +npa_cn20k_pool_dump(__io struct npa_cn20k_pool_s *pool) +{ + npa_dump("W0: Stack base\t\t0x%" PRIx64 "\n", pool->stack_base); + npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d", + pool->ena, pool->nat_align, pool->stack_caching); + npa_dump("W1: buf_offset \t\t%d", pool->buf_offset); + npa_dump("W1: buf_size \t\t%d\nW1: ref_cnt_prof \t%d", + pool->buf_size, pool->ref_cnt_prof); + + npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n", + pool->stack_max_pages, pool->stack_pages); + + npa_dump("W3: bp_0 \t\t%d\nW3: bp_1 \t\t%d\nW3: bp_2 \t\t%d", + pool->bp_0, pool->bp_1, pool->bp_2); + npa_dump("W3: bp_3 \t\t%d\nW3: bp_4 \t\t%d\nW3: bp_5 \t\t%d", + pool->bp_3, pool->bp_4, pool->bp_5); + npa_dump("W3: bp_6 \t\t%d\nW3: bp_7 \t\t%d", pool->bp_6, pool->bp_7); + npa_dump("W3: bp_ena_0 \t\t%d\nW3: bp_ena_1 \t\t%d", pool->bp_ena_0, + pool->bp_ena_1); + npa_dump("W3: bp_ena_2 \t\t%d\nW3: bp_ena_3 \t\t%d", pool->bp_ena_2, + pool->bp_ena_3); + npa_dump("W3: bp_ena_4 \t\t%d\nW3: bp_ena_5 \t\t%d", pool->bp_ena_4, + pool->bp_ena_5); + npa_dump("W3: bp_ena_6 \t\t%d\nW3: bp_ena_7 \t\t%d\n", pool->bp_6, + pool->bp_7); + + npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d", + pool->stack_offset, pool->shift, pool->avg_level); + npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d", + pool->avg_con, pool->fc_ena, pool->fc_stype); + npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d", + pool->fc_hyst_bits, pool->fc_up_crossing); + npa_dump("W4: update_time\t\t%d\n", pool->update_time); + + npa_dump("W5: fc_addr\t\t0x%" PRIx64 "\n", pool->fc_addr); + + npa_dump("W6: ptr_start\t\t0x%" PRIx64 "\n", pool->ptr_start); + + npa_dump("W7: ptr_end\t\t0x%" PRIx64 "\n", pool->ptr_end); + + npa_dump("W8: bpid_0 \t\t%d", pool->bpid_0); + npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d", pool->err_int, + pool->err_int_ena); + npa_dump("W8: thresh_int\t\t%d", pool->thresh_int); + npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d", + pool->thresh_int_ena, pool->thresh_up); + npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n", + pool->thresh_qint_idx, pool->err_qint_idx); + npa_dump("W9: thresh\t\t%" PRIx64 "", (uint64_t)pool->thresh); + npa_dump("W9: fc_msh_dst \t\t%d", pool->fc_msh_dst); + npa_dump("W9: op_dpc_ena \t\t%d\nW9: op_dpc_set \t\t%d", + pool->op_dpc_ena, pool->op_dpc_set); + npa_dump("W9: stream_ctx \t\t%d", pool->stream_ctx); +} + +static inline void +npa_halo_dump(__io struct npa_cn20k_halo_s *halo) +{ + npa_dump("W0: Stack base\t\t0x%" PRIx64 "\n", halo->stack_base); + npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d", + halo->ena, halo->nat_align, halo->stack_caching); + npa_dump("W1: buf_offset\t\t%d\nW1: buf_size\t\t%d", + halo->buf_offset, halo->buf_size); + npa_dump("W1: ref_cnt_prof \t%d\n", halo->ref_cnt_prof); + + npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n", + halo->stack_max_pages, halo->stack_pages); + + npa_dump("W3: bp_0 \t\t%d\nW3: bp_1 \t\t%d\nW3: bp_2 \t\t%d", + halo->bp_0, halo->bp_1, halo->bp_2); + npa_dump("W3: bp_3 \t\t%d\nW3: bp_4 \t\t%d\nW3: bp_5 \t\t%d", + halo->bp_3, halo->bp_4, halo->bp_5); + npa_dump("W3: bp_6 \t\t%d\nW3: bp_7 \t\t%d", halo->bp_6, halo->bp_7); + + npa_dump("W3: bp_ena_0 \t\t%d\nW3: bp_ena_1 \t\t%d", halo->bp_ena_0, + halo->bp_ena_1); + npa_dump("W3: bp_ena_2 \t\t%d\nW3: bp_ena_3 \t\t%d", halo->bp_ena_2, + halo->bp_ena_3); + npa_dump("W3: bp_ena_4 \t\t%d\nW3: bp_ena_5 \t\t%d", halo->bp_ena_4, + halo->bp_ena_5); + npa_dump("W3: bp_ena_6 \t\t%d\nW3: bp_ena_7 \t\t%d\n", halo->bp_6, + halo->bp_7); + + npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d", + halo->stack_offset, halo->shift, halo->avg_level); + npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d", + halo->avg_con, halo->fc_ena, halo->fc_stype); + npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d", + halo->fc_hyst_bits, halo->fc_up_crossing); + npa_dump("W4: update_time\t\t%d\n", halo->update_time); + + npa_dump("W5: fc_addr\t\t0x%" PRIx64 "\n", halo->fc_addr); + + npa_dump("W6: ptr_start\t\t0x%" PRIx64 "\n", halo->ptr_start); + + npa_dump("W7: ptr_end\t\t0x%" PRIx64 "\n", halo->ptr_end); + npa_dump("W8: bpid_0 \t\t%d", halo->bpid_0); + npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d", halo->err_int, + halo->err_int_ena); + npa_dump("W8: thresh_int\t\t%d", halo->thresh_int); + + npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d", + halo->thresh_int_ena, halo->thresh_up); + npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n", + halo->thresh_qint_idx, halo->err_qint_idx); + npa_dump("W9: thresh \t\t%" PRIx64 "\nW9: fc_msh_dst \t\t%d", + (unsigned long)halo->thresh, halo->fc_msh_dst); + npa_dump("W9: op_dpc_ena \t\t%d\nW9: op_dpc_set \t\t%d", + halo->op_dpc_ena, halo->op_dpc_set); + npa_dump("W9: stream_ctx \t\t%d\nW9: unified_ctx \t%d", + halo->stream_ctx, halo->unified_ctx); +} + +static inline void +npa_cn20k_aura_dump(__io struct npa_cn20k_aura_s *aura) +{ + npa_dump("W0: Pool addr\t\t0x%" PRIx64 "\n", aura->pool_addr); + + npa_dump("W1: ena\t\t\t%d\nW1: pool caching\t%d", aura->ena, + aura->pool_caching); + npa_dump("W1: avg con\t\t%d\nW1: pool drop ena\t%d", aura->avg_con, + aura->pool_drop_ena); + npa_dump("W1: aura drop ena\t%d", aura->aura_drop_ena); + npa_dump("W1: bp_ena\t\t%d", aura->bp_ena); + npa_dump("W1: aura drop\t\t%d\nW1: aura shift\t\t%d", aura->aura_drop, + aura->shift); + npa_dump("W1: avg_level\t\t%d\n", aura->avg_level); + + npa_dump("W2: count\t\t%" PRIx64 "", (uint64_t)aura->count); + npa_dump("W2: bpid\t\t%d\n", aura->bpid); + + npa_dump("W3: limit\t\t%" PRIx64 "", (uint64_t)aura->limit); + npa_dump("W3: bp\t\t\t%d", aura->bp); + npa_dump("W3: fc_ena\t\t%d", aura->fc_ena); + npa_dump("W3: fc_up_crossing\t%d\nW3: fc_stype\t\t%d", + aura->fc_up_crossing, aura->fc_stype); + + npa_dump("W3: fc_hyst_bits\t%d\n", aura->fc_hyst_bits); + + npa_dump("W4: fc_addr\t\t0x%" PRIx64 "\n", aura->fc_addr); + + npa_dump("W5: pool_drop\t\t%d\nW5: update_time\t\t%d", aura->pool_drop, + aura->update_time); + npa_dump("W5: err_int\t\t%d", aura->err_int); + npa_dump("W5: err_int_ena\t\t%d\nW5: thresh_int\t\t%d", + aura->err_int_ena, aura->thresh_int); + npa_dump("W5: thresh_int_ena\t%d", aura->thresh_int_ena); + + npa_dump("W5: thresh_up\t\t%d\nW5: thresh_qint_idx\t%d", + aura->thresh_up, aura->thresh_qint_idx); + npa_dump("W5: err_qint_idx\t%d\n", aura->err_qint_idx); + + npa_dump("W6: thresh\t\t%" PRIx64 "", (uint64_t)aura->thresh); + npa_dump("W6: fc_msh_dst \t\t%d", aura->fc_msh_dst); + npa_dump("W6: op_dpc_ena \t\t%d\nW6: op_dpc_set \t\t%d", + aura->op_dpc_ena, aura->op_dpc_set); + npa_dump("W6: stream_ctx \t\t%d", aura->stream_ctx); +} + int roc_npa_ctx_dump(void) { struct npa_cn20k_aq_enq_req *aq_cn20k; + struct npa_cn20k_aq_enq_rsp *rsp_cn20k; struct npa_aq_enq_rsp *rsp; struct npa_aq_enq_req *aq; struct mbox *mbox; @@ -103,7 +264,7 @@ roc_npa_ctx_dump(void) mbox = mbox_get(lf->mbox); for (q = 0; q < lf->nr_pools; q++) { - /* Skip disabled POOL */ + /* Skip disabled AURA */ if (plt_bitmap_get(lf->npa_bmp, q)) continue; @@ -118,21 +279,34 @@ roc_npa_ctx_dump(void) goto exit; } aq->aura_id = q; - aq->ctype = NPA_AQ_CTYPE_POOL; aq->op = NPA_AQ_INSTOP_READ; + if (lf->aura_attr[q].halo) { + aq->ctype = NPA_AQ_CTYPE_HALO; + rc = mbox_process_msg(mbox, (void *)&rsp_cn20k); + } else { + aq->ctype = NPA_AQ_CTYPE_AURA; + rc = mbox_process_msg(mbox, (void *)&rsp); + } - rc = mbox_process_msg(mbox, (void *)&rsp); if (rc) { - plt_err("Failed to get pool(%d) context", q); + plt_err("Failed to get aura/halo(%d) context", q); goto exit; } - npa_dump("============== pool=%d ===============\n", q); - npa_pool_dump(&rsp->pool); + if (lf->aura_attr[q].halo) { + npa_dump("============== halo=%d ===============\n", q); + npa_halo_dump(&rsp_cn20k->halo); + } else { + npa_dump("============== aura=%d ===============\n", q); + if (roc_model_is_cn20k()) + npa_cn20k_aura_dump(&rsp_cn20k->aura); + else + npa_aura_dump(&rsp->aura); + } } for (q = 0; q < lf->nr_pools; q++) { - /* Skip disabled AURA */ - if (plt_bitmap_get(lf->npa_bmp, q)) + /* Skip halo and disabled POOL */ + if (plt_bitmap_get(lf->npa_bmp, q) || lf->aura_attr[q].halo) continue; if (roc_model_is_cn20k()) { @@ -146,16 +320,19 @@ roc_npa_ctx_dump(void) goto exit; } aq->aura_id = q; - aq->ctype = NPA_AQ_CTYPE_AURA; + aq->ctype = NPA_AQ_CTYPE_POOL; aq->op = NPA_AQ_INSTOP_READ; rc = mbox_process_msg(mbox, (void *)&rsp); if (rc) { - plt_err("Failed to get aura(%d) context", q); + plt_err("Failed to get pool(%d) context", q); goto exit; } - npa_dump("============== aura=%d ===============\n", q); - npa_aura_dump(&rsp->aura); + npa_dump("============== pool=%d ===============\n", q); + if (roc_model_is_cn20k()) + npa_cn20k_pool_dump(&rsp_cn20k->pool); + else + npa_pool_dump(&rsp->pool); } exit: diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h index 0223e4a438..e437fe831a 100644 --- a/drivers/common/cnxk/roc_npa_priv.h +++ b/drivers/common/cnxk/roc_npa_priv.h @@ -14,6 +14,8 @@ enum npa_error_status { NPA_ERR_AURA_POOL_FINI = -517, NPA_ERR_BASE_INVALID = -518, NPA_ERR_DEVICE_NOT_BOUNDED = -519, + NPA_ERR_HALO_INIT = -520, + NPA_ERR_HALO_FINI = -521, }; struct npa_lf { @@ -55,6 +57,7 @@ struct npa_aura_attr { uint64_t shift; uint64_t limit; uint8_t bp_ena; + bool halo; union { uint8_t bp; /* CN9K, CN10K */ uint8_t bp_thresh[8]; /* CN20K */ diff --git a/drivers/common/cnxk/roc_platform_base_symbols.c b/drivers/common/cnxk/roc_platform_base_symbols.c index 43095741f5..79dd18fbd7 100644 --- a/drivers/common/cnxk/roc_platform_base_symbols.c +++ b/drivers/common/cnxk/roc_platform_base_symbols.c @@ -85,6 +85,8 @@ RTE_EXPORT_INTERNAL_SYMBOL(roc_hash_sha256_gen) RTE_EXPORT_INTERNAL_SYMBOL(roc_hash_sha512_gen) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_maxpools_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_maxpools_set) +RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_halo_ena_get) +RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_halo_ena_set) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_lmt_base_addr_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_num_lmtlines_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_cpt_get) diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 1d82e5b978..b07454a7f0 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -834,8 +834,6 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, uint32_t nb_xae, uint32_t xae_waes, uint32_t xaq_buf_size, uint16_t nb_hwgrp) { - struct npa_pool_s pool; - struct npa_aura_s aura; plt_iova_t iova; uint32_t i; int rc; @@ -877,15 +875,32 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, goto free_fc; } - memset(&pool, 0, sizeof(struct npa_pool_s)); - pool.nat_align = 1; + if (roc_model_is_cn20k() && xaq->halo_ena) { + struct npa_cn20k_halo_s halo; + + memset(&halo, 0, sizeof(struct npa_cn20k_halo_s)); + halo.nat_align = 1; + halo.fc_ena = 1; + halo.fc_addr = (uint64_t)xaq->fc; + halo.fc_hyst_bits = 0; /* Store count on all updates */ + halo.unified_ctx = 1; + rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, + NULL, (struct npa_pool_s *)&halo, ROC_NPA_HALO_F); + } else { + struct npa_pool_s pool; + struct npa_aura_s aura; + + memset(&pool, 0, sizeof(struct npa_pool_s)); + pool.nat_align = 1; + + memset(&aura, 0, sizeof(aura)); + aura.fc_ena = 1; + aura.fc_addr = (uint64_t)xaq->fc; + aura.fc_hyst_bits = 0; /* Store count on all updates */ + rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, + &aura, &pool, 0); + } - memset(&aura, 0, sizeof(aura)); - aura.fc_ena = 1; - aura.fc_addr = (uint64_t)xaq->fc; - aura.fc_hyst_bits = 0; /* Store count on all updates */ - rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, - &aura, &pool, 0); if (rc) { plt_err("Failed to create XAQ pool"); goto npa_fail; diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index f1ad34bcc7..9d8356abb1 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -43,6 +43,7 @@ struct roc_sso_xaq_data { uint32_t nb_xae; uint32_t xaq_lmt; uint64_t aura_handle; + int halo_ena; void *fc; void *mem; }; -- 2.48.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 2/2] mempool/cnxk: add halo support in mempool 2026-02-17 5:34 ` [PATCH v3 0/2] Add HALO support for CN20K mempool Nawal Kishor 2026-02-17 5:34 ` [PATCH v3 1/2] common/cnxk: add support for halos Nawal Kishor @ 2026-02-17 5:34 ` Nawal Kishor 2026-02-17 8:43 ` [PATCH v3 0/2] Add HALO support for CN20K mempool Jerin Jacob 2 siblings, 0 replies; 18+ messages in thread From: Nawal Kishor @ 2026-02-17 5:34 UTC (permalink / raw) To: dev, Ashwin Sekhar T K, Pavan Nikhilesh; +Cc: jerinj, Nawal Kishor This patch adds the support of halos in CN20K mempool driver. It introduces a new devargs parameter "halo_ena" to enable or disable halo feature. If halo_ena is set to 1, halos will be enabled for NPA pools created by the mempool driver. Signed-off-by: Nawal Kishor <nkishor@marvell.com> --- v3: * Added details about the new "halo_ena" parameter in the documentation. doc/guides/mempool/cnxk.rst | 24 ++++++++-- drivers/mempool/cnxk/cn10k_mempool_ops.c | 19 ++++---- drivers/mempool/cnxk/cn20k_mempool_ops.c | 60 ++++++++++++++++++++++++ drivers/mempool/cnxk/cn9k_mempool_ops.c | 2 +- drivers/mempool/cnxk/cnxk_mempool.c | 40 +++++++++++----- drivers/mempool/cnxk/cnxk_mempool.h | 16 ++++++- drivers/mempool/cnxk/cnxk_mempool_ops.c | 11 +++-- drivers/mempool/cnxk/meson.build | 1 + 8 files changed, 141 insertions(+), 32 deletions(-) create mode 100644 drivers/mempool/cnxk/cn20k_mempool_ops.c diff --git a/doc/guides/mempool/cnxk.rst b/doc/guides/mempool/cnxk.rst index 3d0729245a..178ff99acf 100644 --- a/doc/guides/mempool/cnxk.rst +++ b/doc/guides/mempool/cnxk.rst @@ -5,7 +5,7 @@ cnxk NPA Mempool Driver ======================= The cnxk NPA PMD (**librte_mempool_cnxk**) provides mempool driver support for -the integrated mempool device found in **Marvell OCTEON CN9K/CN10K** SoC family. +the integrated mempool device found in **Marvell OCTEON CN9K/CN10K/CN20K** SoC family. More information about cnxk SoC can be found at `Marvell Official Website <https://www.marvell.com/embedded-processors/infrastructure-processors/>`_. @@ -30,6 +30,11 @@ CN10k NPA supports: - Batch dequeue of up to 512 pointers with single instruction. - Batch enqueue of up to 15 pointers with single instruction. +CN20k NPA supports: + +- HALO support for 1:1 aura-pool mapping, which uses a single unified context + instead of separate aura and pool contexts, saving HW context space. + Prerequisites and Compilation procedure --------------------------------------- @@ -56,11 +61,24 @@ Runtime Config Options With the above configuration, the driver will set up only 512 mempools for the given application to save HW resources. +- ``HALO enable`` (default ``0``) + + The HALO feature is available on CN20K platforms and allows 1:1 aura-pool + mapping to use a single unified context instead of separate aura and pool + contexts, saving HW context space. This parameter enables or disables HALO + support for NPA pools created by the mempool driver. + For example:: + + -a 0002:02:00.0,halo_ena=1 + + With the above configuration, HALO support will be enabled for mempools created + on CN20K platforms. + .. note:: Since this configuration is per application, the end user needs to - provide ``max_pools`` parameter to the first PCIe device probed by the given - application. + provide ``max_pools`` and/or ``halo_ena`` parameter to the first PCIe device + probed by the given application. Debugging Options ~~~~~~~~~~~~~~~~~ diff --git a/drivers/mempool/cnxk/cn10k_mempool_ops.c b/drivers/mempool/cnxk/cn10k_mempool_ops.c index a5be0ccafe..09f900a850 100644 --- a/drivers/mempool/cnxk/cn10k_mempool_ops.c +++ b/drivers/mempool/cnxk/cn10k_mempool_ops.c @@ -2,9 +2,6 @@ * Copyright(C) 2021 Marvell. */ -#include <rte_mempool.h> - -#include "roc_api.h" #include "cnxk_mempool.h" #define BATCH_ALLOC_SZ ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS @@ -79,7 +76,7 @@ batch_op_data_set(uint64_t pool_id, struct batch_op_data *op_data) batch_op_data_tbl[aura] = op_data; } -static int +int batch_op_init(struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -109,7 +106,7 @@ batch_op_init(struct rte_mempool *mp) return 0; } -static void +void batch_op_fini(struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -149,7 +146,7 @@ batch_op_fini(struct rte_mempool *mp) rte_wmb(); } -static int __rte_hot +int __rte_hot cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, unsigned int n) { @@ -181,7 +178,7 @@ cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, return 0; } -static unsigned int +unsigned int cn10k_mempool_get_count(const struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -326,7 +323,7 @@ mempool_deq_batch_sync(struct rte_mempool *mp, void **obj_table, unsigned int n) return count; } -static int __rte_hot +int __rte_hot cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n) { struct batch_op_data *op_data; @@ -353,7 +350,7 @@ cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n) return 0; } -static int +int cn10k_mempool_alloc(struct rte_mempool *mp) { uint32_t block_size; @@ -376,7 +373,7 @@ cn10k_mempool_alloc(struct rte_mempool *mp) block_size += padding; } - rc = cnxk_mempool_alloc(mp); + rc = cnxk_mempool_alloc(mp, 0); if (rc) return rc; @@ -392,7 +389,7 @@ cn10k_mempool_alloc(struct rte_mempool *mp) return rc; } -static void +void cn10k_mempool_free(struct rte_mempool *mp) { batch_op_fini(mp); diff --git a/drivers/mempool/cnxk/cn20k_mempool_ops.c b/drivers/mempool/cnxk/cn20k_mempool_ops.c new file mode 100644 index 0000000000..f8817d8743 --- /dev/null +++ b/drivers/mempool/cnxk/cn20k_mempool_ops.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2025 Marvell. + */ + +#include "cnxk_mempool.h" + +static int +cn20k_mempool_alloc(struct rte_mempool *mp) +{ + uint32_t block_size; + int halo_ena, rc; + size_t padding; + + block_size = mp->elt_size + mp->header_size + mp->trailer_size; + /* Align header size to ROC_ALIGN */ + if (mp->header_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(mp->header_size, ROC_ALIGN) - + mp->header_size; + mp->header_size += padding; + block_size += padding; + } + + /* Align block size to ROC_ALIGN */ + if (block_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(block_size, ROC_ALIGN) - block_size; + mp->trailer_size += padding; + block_size += padding; + } + + /* Get halo status */ + halo_ena = roc_idev_npa_halo_ena_get(); + + rc = cnxk_mempool_alloc(mp, halo_ena ? ROC_NPA_HALO_F : 0); + if (rc) + return rc; + + rc = batch_op_init(mp); + if (rc) { + plt_err("Failed to init batch alloc mem rc=%d", rc); + goto error; + } + + return 0; +error: + cnxk_mempool_free(mp); + return rc; +} + +static struct rte_mempool_ops cn20k_mempool_ops = { + .name = "cn20k_mempool_ops", + .alloc = cn20k_mempool_alloc, + .free = cn10k_mempool_free, + .enqueue = cn10k_mempool_enq, + .dequeue = cn10k_mempool_deq, + .get_count = cn10k_mempool_get_count, + .calc_mem_size = cnxk_mempool_calc_mem_size, + .populate = cnxk_mempool_populate, +}; + +RTE_MEMPOOL_REGISTER_OPS(cn20k_mempool_ops); diff --git a/drivers/mempool/cnxk/cn9k_mempool_ops.c b/drivers/mempool/cnxk/cn9k_mempool_ops.c index b7967f8085..8248071cb7 100644 --- a/drivers/mempool/cnxk/cn9k_mempool_ops.c +++ b/drivers/mempool/cnxk/cn9k_mempool_ops.c @@ -72,7 +72,7 @@ cn9k_mempool_alloc(struct rte_mempool *mp) padding = ((block_size / ROC_ALIGN) % 2) ? 0 : ROC_ALIGN; mp->trailer_size += padding; - return cnxk_mempool_alloc(mp); + return cnxk_mempool_alloc(mp, 0); } static struct rte_mempool_ops cn9k_mempool_ops = { diff --git a/drivers/mempool/cnxk/cnxk_mempool.c b/drivers/mempool/cnxk/cnxk_mempool.c index 6ff11d8004..6939fccff4 100644 --- a/drivers/mempool/cnxk/cnxk_mempool.c +++ b/drivers/mempool/cnxk/cnxk_mempool.c @@ -18,6 +18,7 @@ #define CNXK_NPA_DEV_NAME RTE_STR(cnxk_npa_dev_) #define CNXK_NPA_DEV_NAME_LEN (sizeof(CNXK_NPA_DEV_NAME) + PCI_PRI_STR_SIZE) #define CNXK_NPA_MAX_POOLS_PARAM "max_pools" +#define CNXK_NPA_HALO_ENA_PARAM "halo_ena" static inline uint32_t npa_aura_size_to_u32(uint8_t val) @@ -46,30 +47,46 @@ parse_max_pools_handler(const char *key, const char *value, void *extra_args) return 0; } -static inline uint32_t -parse_max_pools(struct rte_devargs *devargs) +static int +parse_halo_ena_handler(const char *key, const char *value, void *extra_args) +{ + RTE_SET_USED(key); + uint8_t val; + + val = atoi(value); + if (val != 0 && val != 1) + return -EINVAL; + + *(uint8_t *)extra_args = val; + return 0; +} + +static int +cnxk_mempool_plt_parse_devargs(struct rte_pci_device *pci_dev) { uint32_t max_pools = npa_aura_size_to_u32(NPA_AURA_SZ_128); + struct rte_devargs *devargs = pci_dev->device.devargs; struct rte_kvargs *kvlist; + uint32_t halo_ena = 0; if (devargs == NULL) - goto exit; + goto null_devargs; kvlist = rte_kvargs_parse(devargs->args, NULL); if (kvlist == NULL) goto exit; rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM, &parse_max_pools_handler, &max_pools); + rte_kvargs_process(kvlist, CNXK_NPA_HALO_ENA_PARAM, + &parse_halo_ena_handler, &halo_ena); rte_kvargs_free(kvlist); -exit: - return max_pools; -} -static int -cnxk_mempool_plt_parse_devargs(struct rte_pci_device *pci_dev) -{ - roc_idev_npa_maxpools_set(parse_max_pools(pci_dev->device.devargs)); +null_devargs: + roc_idev_npa_maxpools_set(max_pools); + roc_idev_npa_halo_ena_set(halo_ena); return 0; +exit: + return -EINVAL; } static inline char * @@ -201,7 +218,8 @@ RTE_PMD_REGISTER_PCI(mempool_cnxk, npa_pci); RTE_PMD_REGISTER_PCI_TABLE(mempool_cnxk, npa_pci_map); RTE_PMD_REGISTER_KMOD_DEP(mempool_cnxk, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(mempool_cnxk, - CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>"); + CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>" + CNXK_NPA_HALO_ENA_PARAM "=<0-1>"); RTE_INIT(cnxk_mempool_parse_devargs) { diff --git a/drivers/mempool/cnxk/cnxk_mempool.h b/drivers/mempool/cnxk/cnxk_mempool.h index 669e617952..941290061e 100644 --- a/drivers/mempool/cnxk/cnxk_mempool.h +++ b/drivers/mempool/cnxk/cnxk_mempool.h @@ -7,6 +7,8 @@ #include <rte_mempool.h> +#include "roc_api.h" + enum cnxk_mempool_flags { /* This flag is used to ensure that only aura zero is allocated. * If aura zero is not available, then mempool creation fails. @@ -47,7 +49,7 @@ int cnxk_mempool_populate(struct rte_mempool *mp, unsigned int max_objs, void *vaddr, rte_iova_t iova, size_t len, rte_mempool_populate_obj_cb_t *obj_cb, void *obj_cb_arg); -int cnxk_mempool_alloc(struct rte_mempool *mp); +int cnxk_mempool_alloc(struct rte_mempool *mp, uint64_t roc_flags); void cnxk_mempool_free(struct rte_mempool *mp); int __rte_hot cnxk_mempool_enq(struct rte_mempool *mp, void *const *obj_table, @@ -55,6 +57,16 @@ int __rte_hot cnxk_mempool_enq(struct rte_mempool *mp, void *const *obj_table, int __rte_hot cnxk_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n); +int batch_op_init(struct rte_mempool *mp); +void batch_op_fini(struct rte_mempool *mp); +int __rte_hot cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, + unsigned int n); +unsigned int cn10k_mempool_get_count(const struct rte_mempool *mp); +int __rte_hot cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, + unsigned int n); +int cn10k_mempool_alloc(struct rte_mempool *mp); +void cn10k_mempool_free(struct rte_mempool *mp); + int cn10k_mempool_plt_init(void); -#endif +#endif /* _CNXK_MEMPOOL_H_ */ diff --git a/drivers/mempool/cnxk/cnxk_mempool_ops.c b/drivers/mempool/cnxk/cnxk_mempool_ops.c index 5c7fcea487..01b6247fbb 100644 --- a/drivers/mempool/cnxk/cnxk_mempool_ops.c +++ b/drivers/mempool/cnxk/cnxk_mempool_ops.c @@ -70,9 +70,9 @@ cnxk_mempool_calc_mem_size(const struct rte_mempool *mp, uint32_t obj_num, } int -cnxk_mempool_alloc(struct rte_mempool *mp) +cnxk_mempool_alloc(struct rte_mempool *mp, uint64_t roc_flags) { - uint32_t block_count, flags, roc_flags = 0; + uint32_t block_count, flags; uint64_t aura_handle = 0; struct npa_aura_s aura; struct npa_pool_s pool; @@ -98,7 +98,7 @@ cnxk_mempool_alloc(struct rte_mempool *mp) flags = CNXK_MEMPOOL_FLAGS(mp); if (flags & CNXK_MEMPOOL_F_ZERO_AURA) { - roc_flags = ROC_NPA_ZERO_AURA_F; + roc_flags |= ROC_NPA_ZERO_AURA_F; } else if (flags & CNXK_MEMPOOL_F_CUSTOM_AURA) { struct npa_aura_s *paura; @@ -192,9 +192,12 @@ cnxk_mempool_plt_init(void) if (roc_model_is_cn9k()) { rte_mbuf_set_platform_mempool_ops("cn9k_mempool_ops"); - } else if (roc_model_is_cn10k() || roc_model_is_cn20k()) { + } else if (roc_model_is_cn10k()) { rte_mbuf_set_platform_mempool_ops("cn10k_mempool_ops"); rc = cn10k_mempool_plt_init(); + } else if (roc_model_is_cn20k()) { + rte_mbuf_set_platform_mempool_ops("cn20k_mempool_ops"); + rc = cn10k_mempool_plt_init(); } return rc; } diff --git a/drivers/mempool/cnxk/meson.build b/drivers/mempool/cnxk/meson.build index e388cce26a..7722264320 100644 --- a/drivers/mempool/cnxk/meson.build +++ b/drivers/mempool/cnxk/meson.build @@ -14,6 +14,7 @@ sources = files( 'cnxk_mempool_telemetry.c', 'cn9k_mempool_ops.c', 'cn10k_mempool_ops.c', + 'cn20k_mempool_ops.c', 'cn10k_hwpool_ops.c', ) -- 2.48.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v3 0/2] Add HALO support for CN20K mempool 2026-02-17 5:34 ` [PATCH v3 0/2] Add HALO support for CN20K mempool Nawal Kishor 2026-02-17 5:34 ` [PATCH v3 1/2] common/cnxk: add support for halos Nawal Kishor 2026-02-17 5:34 ` [PATCH v3 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor @ 2026-02-17 8:43 ` Jerin Jacob 2 siblings, 0 replies; 18+ messages in thread From: Jerin Jacob @ 2026-02-17 8:43 UTC (permalink / raw) To: Nawal Kishor; +Cc: dev, jerinj, asekhar On Tue, Feb 17, 2026 at 11:14 AM Nawal Kishor <nkishor@marvell.com> wrote: > > This series of patches adds support for HALO in CNXK mempool driver. > > Changes in v3: > * Added documentation for HALO support in CNXK mempool driver. > > Nawal Kishor (2): > common/cnxk: add support for halos > mempool/cnxk: add halo support in mempool > > doc/guides/mempool/cnxk.rst | 24 +- > drivers/common/cnxk/hw/npa.h | 81 ++++++ > drivers/common/cnxk/roc_idev.c | 25 ++ > drivers/common/cnxk/roc_idev.h | 3 + > drivers/common/cnxk/roc_idev_priv.h | 1 + > drivers/common/cnxk/roc_mbox.h | 6 + > drivers/common/cnxk/roc_nix.h | 1 + > drivers/common/cnxk/roc_nix_queue.c | 46 ++- > drivers/common/cnxk/roc_npa.c | 268 ++++++++++++++++-- > drivers/common/cnxk/roc_npa.h | 20 +- > drivers/common/cnxk/roc_npa_debug.c | 201 ++++++++++++- > drivers/common/cnxk/roc_npa_priv.h | 3 + > .../common/cnxk/roc_platform_base_symbols.c | 2 + > drivers/common/cnxk/roc_sso.c | 35 ++- > drivers/common/cnxk/roc_sso.h | 1 + > drivers/mempool/cnxk/cn10k_mempool_ops.c | 19 +- > drivers/mempool/cnxk/cn20k_mempool_ops.c | 60 ++++ > drivers/mempool/cnxk/cn9k_mempool_ops.c | 2 +- > drivers/mempool/cnxk/cnxk_mempool.c | 40 ++- > drivers/mempool/cnxk/cnxk_mempool.h | 16 +- > drivers/mempool/cnxk/cnxk_mempool_ops.c | 11 +- > drivers/mempool/cnxk/meson.build | 1 + Pleaesto add roc_feature_npa_has_halo() in drivers/common/cnxk/roc_features.h. instead of relying on cn20k() checks as applicable. Good to merge next version. > 22 files changed, 771 insertions(+), 95 deletions(-) > create mode 100644 drivers/mempool/cnxk/cn20k_mempool_ops.c > > -- > 2.48.1 > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 0/2] Add HALO support for CN20K mempool 2025-12-05 5:51 ` [PATCH v2 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor 2026-02-17 5:34 ` [PATCH v3 0/2] Add HALO support for CN20K mempool Nawal Kishor @ 2026-02-17 10:39 ` Nawal Kishor 2026-02-17 10:39 ` [PATCH v4 1/2] common/cnxk: add support for halos Nawal Kishor 2026-02-17 10:39 ` [PATCH v4 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor 1 sibling, 2 replies; 18+ messages in thread From: Nawal Kishor @ 2026-02-17 10:39 UTC (permalink / raw) To: dev; +Cc: jerinj, asekhar, Nawal Kishor This series of patches adds support for HALO in CNXK mempool driver. Changes in v4: * Added roc_feature_npa_has_halo() as per review comments. Nawal Kishor (2): common/cnxk: add support for halos mempool/cnxk: add halo support in mempool doc/guides/mempool/cnxk.rst | 24 +- drivers/common/cnxk/hw/npa.h | 81 ++++++ drivers/common/cnxk/roc_features.h | 7 + drivers/common/cnxk/roc_idev.c | 25 ++ drivers/common/cnxk/roc_idev.h | 3 + drivers/common/cnxk/roc_idev_priv.h | 1 + drivers/common/cnxk/roc_mbox.h | 6 + drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 46 ++- drivers/common/cnxk/roc_npa.c | 268 ++++++++++++++++-- drivers/common/cnxk/roc_npa.h | 20 +- drivers/common/cnxk/roc_npa_debug.c | 201 ++++++++++++- drivers/common/cnxk/roc_npa_priv.h | 3 + .../common/cnxk/roc_platform_base_symbols.c | 2 + drivers/common/cnxk/roc_sso.c | 35 ++- drivers/common/cnxk/roc_sso.h | 1 + drivers/mempool/cnxk/cn10k_mempool_ops.c | 19 +- drivers/mempool/cnxk/cn20k_mempool_ops.c | 60 ++++ drivers/mempool/cnxk/cn9k_mempool_ops.c | 2 +- drivers/mempool/cnxk/cnxk_mempool.c | 40 ++- drivers/mempool/cnxk/cnxk_mempool.h | 16 +- drivers/mempool/cnxk/cnxk_mempool_ops.c | 11 +- drivers/mempool/cnxk/meson.build | 1 + 23 files changed, 778 insertions(+), 95 deletions(-) create mode 100644 drivers/mempool/cnxk/cn20k_mempool_ops.c -- 2.48.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 1/2] common/cnxk: add support for halos 2026-02-17 10:39 ` [PATCH v4 " Nawal Kishor @ 2026-02-17 10:39 ` Nawal Kishor 2026-02-19 17:19 ` Stephen Hemminger 2026-02-17 10:39 ` [PATCH v4 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor 1 sibling, 1 reply; 18+ messages in thread From: Nawal Kishor @ 2026-02-17 10:39 UTC (permalink / raw) To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao, Harman Kalra Cc: jerinj, asekhar, Nawal Kishor In cn9k/cn10k NPA mempool creation required the creation of at least one aura and pool context. Even, if the mapping between aura and pool was 1:1 (i.e, one aura mapped to one pool), separate contexts were required for aura and pool. This wasted the context space and most of common use case for NPA mempool is 1:1 mapping between aura and pool. In cn20k, 1:1 aura pool mapping can now be replaced by using halos. Halos allow the creation of only one context which contains the information required for both aura and pool. This patch adds the support for creation of Halos in ROC. Signed-off-by: Nawal Kishor <nkishor@marvell.com> --- Changes in v4: * Addressed review comments. drivers/common/cnxk/hw/npa.h | 81 ++++++ drivers/common/cnxk/roc_features.h | 7 + drivers/common/cnxk/roc_idev.c | 25 ++ drivers/common/cnxk/roc_idev.h | 3 + drivers/common/cnxk/roc_idev_priv.h | 1 + drivers/common/cnxk/roc_mbox.h | 6 + drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 46 ++- drivers/common/cnxk/roc_npa.c | 268 ++++++++++++++++-- drivers/common/cnxk/roc_npa.h | 20 +- drivers/common/cnxk/roc_npa_debug.c | 201 ++++++++++++- drivers/common/cnxk/roc_npa_priv.h | 3 + .../common/cnxk/roc_platform_base_symbols.c | 2 + drivers/common/cnxk/roc_sso.c | 35 ++- drivers/common/cnxk/roc_sso.h | 1 + 15 files changed, 637 insertions(+), 63 deletions(-) diff --git a/drivers/common/cnxk/hw/npa.h b/drivers/common/cnxk/hw/npa.h index 4fd1f9a64b..e421c70e01 100644 --- a/drivers/common/cnxk/hw/npa.h +++ b/drivers/common/cnxk/hw/npa.h @@ -118,6 +118,7 @@ #define NPA_AQ_CTYPE_AURA (0x0ull) #define NPA_AQ_CTYPE_POOL (0x1ull) +#define NPA_AQ_CTYPE_HALO (0x2ull) #define NPA_BPINTF_NIX0_RX (0x0ull) #define NPA_BPINTF_NIX1_RX (0x1ull) @@ -456,6 +457,86 @@ struct npa_cn20k_pool_s { uint64_t rsvd_1023_960 : 64; /* W15 */ }; +/* NPA halo context structure [CN20K] */ +struct npa_cn20k_halo_s { + uint64_t stack_base : 64; /* W0 */ + uint64_t ena : 1; /* W1 */ + uint64_t nat_align : 1; + uint64_t reserved_67_66 : 2; + uint64_t stack_caching : 1; + uint64_t reserved_71_69 : 3; + uint64_t aura_drop_ena : 1; + uint64_t reserved_79_73 : 7; + uint64_t aura_drop : 8; + uint64_t buf_offset : 12; + uint64_t reserved_103_100 : 4; + uint64_t buf_size : 12; + uint64_t reserved_119_116 : 4; + uint64_t ref_cnt_prof : 3; + uint64_t reserved_127_123 : 5; + uint64_t stack_max_pages : 32; /* W2 */ + uint64_t stack_pages : 32; + uint64_t bp_0 : 7; /* W3 */ + uint64_t bp_1 : 7; + uint64_t bp_2 : 7; + uint64_t bp_3 : 7; + uint64_t bp_4 : 7; + uint64_t bp_5 : 7; + uint64_t bp_6 : 7; + uint64_t bp_7 : 7; + uint64_t bp_ena_0 : 1; + uint64_t bp_ena_1 : 1; + uint64_t bp_ena_2 : 1; + uint64_t bp_ena_3 : 1; + uint64_t bp_ena_4 : 1; + uint64_t bp_ena_5 : 1; + uint64_t bp_ena_6 : 1; + uint64_t bp_ena_7 : 1; + uint64_t stack_offset : 4; /* W4 */ + uint64_t reserved_263_260 : 4; + uint64_t shift : 6; + uint64_t reserved_271_270 : 2; + uint64_t avg_level : 8; + uint64_t avg_con : 9; + uint64_t fc_ena : 1; + uint64_t fc_stype : 2; + uint64_t fc_hyst_bits : 4; + uint64_t fc_up_crossing : 1; + uint64_t reserved_299_297 : 3; + uint64_t update_time : 16; + uint64_t reserved_319_316 : 4; + uint64_t fc_addr : 64; /* W5 */ + uint64_t ptr_start : 64; /* W6 */ + uint64_t ptr_end : 64; /* W7 */ + uint64_t bpid_0 : 12; /* W8 */ + uint64_t reserved_535_524 : 12; + uint64_t err_int : 8; + uint64_t err_int_ena : 8; + uint64_t thresh_int : 1; + uint64_t thresh_int_ena : 1; + uint64_t thresh_up : 1; + uint64_t reserved_555_555 : 1; + uint64_t thresh_qint_idx : 7; + uint64_t reserved_563_563 : 1; + uint64_t err_qint_idx : 7; + uint64_t reserved_575_571 : 5; + uint64_t thresh : 36; /* W9 */ + uint64_t reserved_615_612 : 4; + uint64_t fc_msh_dst : 11; + uint64_t reserved_630_627 : 4; + uint64_t op_dpc_ena : 1; + uint64_t op_dpc_set : 5; + uint64_t reserved_637_637 : 1; + uint64_t stream_ctx : 1; + uint64_t unified_ctx : 1; + uint64_t reserved_703_640 : 64; /* W10 */ + uint64_t reserved_767_704 : 64; /* W11 */ + uint64_t reserved_831_768 : 64; /* W12 */ + uint64_t reserved_895_832 : 64; /* W13 */ + uint64_t reserved_959_896 : 64; /* W14 */ + uint64_t reserved_1023_960 : 64; /* W15 */ +}; + /* NPA queue interrupt context hardware structure */ struct npa_qint_hw_s { uint32_t count : 22; diff --git a/drivers/common/cnxk/roc_features.h b/drivers/common/cnxk/roc_features.h index 9c6adfe058..3c34041d76 100644 --- a/drivers/common/cnxk/roc_features.h +++ b/drivers/common/cnxk/roc_features.h @@ -137,4 +137,11 @@ roc_feature_nix_has_16b_align(void) { return roc_model_is_cn20k(); } + +static inline bool +roc_feature_npa_has_halo(void) +{ + return roc_model_is_cn20k(); +} + #endif diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c index 84812f73e0..6aa5b10ee9 100644 --- a/drivers/common/cnxk/roc_idev.c +++ b/drivers/common/cnxk/roc_idev.c @@ -33,6 +33,7 @@ idev_set_defaults(struct idev_cfg *idev) idev->npa = NULL; idev->npa_pf_func = 0; idev->max_pools = 128; + idev->halo_ena = 0; idev->lmt_pf_func = 0; idev->lmt_base_addr = 0; idev->num_lmtlines = 0; @@ -123,6 +124,30 @@ roc_idev_npa_maxpools_set(uint32_t max_pools) __atomic_store_n(&idev->max_pools, max_pools, __ATOMIC_RELEASE); } +int +roc_idev_npa_halo_ena_get(void) +{ + struct idev_cfg *idev; + int halo_ena; + + idev = idev_get_cfg(); + halo_ena = 0; + if (idev != NULL) + halo_ena = __atomic_load_n(&idev->halo_ena, __ATOMIC_ACQUIRE); + + return halo_ena; +} + +void +roc_idev_npa_halo_ena_set(int halo_ena) +{ + struct idev_cfg *idev; + + idev = idev_get_cfg(); + if (idev != NULL) + __atomic_store_n(&idev->halo_ena, halo_ena, __ATOMIC_RELEASE); +} + uint16_t idev_npa_lf_active(struct dev *dev) { diff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h index 6edb5f83b2..3803963b07 100644 --- a/drivers/common/cnxk/roc_idev.h +++ b/drivers/common/cnxk/roc_idev.h @@ -8,6 +8,9 @@ uint32_t __roc_api roc_idev_npa_maxpools_get(void); void __roc_api roc_idev_npa_maxpools_set(uint32_t max_pools); +int __roc_api roc_idev_npa_halo_ena_get(void); +void __roc_api roc_idev_npa_halo_ena_set(int halo_ena); + /* LMT */ uint64_t __roc_api roc_idev_lmt_base_addr_get(void); uint16_t __roc_api roc_idev_num_lmtlines_get(void); diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h index 98b6286bfe..dde555535b 100644 --- a/drivers/common/cnxk/roc_idev_priv.h +++ b/drivers/common/cnxk/roc_idev_priv.h @@ -30,6 +30,7 @@ struct idev_cfg { struct npa_lf *npa; uint16_t npa_refcnt; uint32_t max_pools; + int halo_ena; uint16_t lmt_pf_func; uint16_t num_lmtlines; uint64_t lmt_base_addr; diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 3e913fa13c..3176c87382 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1397,6 +1397,8 @@ struct npa_cn20k_aq_enq_req { __io struct npa_cn20k_aura_s aura; /* Valid when op == WRITE/INIT and ctype == POOL */ __io struct npa_cn20k_pool_s pool; + /* Valid when op == WRITE/INIT and ctype == HALO */ + __io struct npa_cn20k_halo_s halo; }; /* Mask data when op == WRITE (1=write, 0=don't write) */ union { @@ -1404,6 +1406,8 @@ struct npa_cn20k_aq_enq_req { __io struct npa_cn20k_aura_s aura_mask; /* Valid when op == WRITE and ctype == POOL */ __io struct npa_cn20k_pool_s pool_mask; + /* Valid when op == WRITE/INIT and ctype == HALO */ + __io struct npa_cn20k_halo_s halo_mask; }; }; @@ -1414,6 +1418,8 @@ struct npa_cn20k_aq_enq_rsp { __io struct npa_cn20k_aura_s aura; /* Valid when op == READ and ctype == POOL */ __io struct npa_cn20k_pool_s pool; + /* Valid when op == READ and ctype == HALO */ + __io struct npa_cn20k_halo_s halo; }; }; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 326decde2b..aa197eb95e 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -595,6 +595,7 @@ struct roc_nix { uintptr_t lmt_base; bool io_enabled; bool rx_ptp_ena; + bool sqb_halo_ena; uint16_t cints; uint32_t buf_sz; uint64_t meta_aura_handle; diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index c7e37abf32..ab3a71ec60 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -1486,8 +1486,6 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); uint16_t sqes_per_sqb, count, nb_sqb_bufs; - struct npa_pool_s pool; - struct npa_aura_s aura; uint64_t blk_sz; uint64_t iova; int rc; @@ -1509,20 +1507,38 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) /* Explicitly set nat_align alone as by default pool is with both * nat_align and buf_offset = 1 which we don't want for SQB. */ - memset(&pool, 0, sizeof(struct npa_pool_s)); - pool.nat_align = 1; + if (roc_feature_npa_has_halo() && roc_nix->sqb_halo_ena) { + struct npa_cn20k_halo_s halo; + + memset(&halo, 0, sizeof(struct npa_cn20k_halo_s)); + halo.nat_align = 1; + halo.fc_ena = 1; + halo.fc_stype = 0x3; /* STSTP */ + halo.fc_addr = (uint64_t)sq->fc; + halo.fc_hyst_bits = 0; /* Store count on all updates */ + halo.unified_ctx = 1; + rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, NULL, + (struct npa_pool_s *)&halo, ROC_NPA_HALO_F); + } else { + struct npa_pool_s pool; + struct npa_aura_s aura; + + memset(&pool, 0, sizeof(struct npa_pool_s)); + pool.nat_align = 1; + + memset(&aura, 0, sizeof(aura)); + /* Disable SQ pool FC updates when SQ count updates are used */ + if (!sq->sq_cnt_ptr) + aura.fc_ena = 1; + if (roc_model_is_cn9k() || roc_errata_npa_has_no_fc_stype_ststp()) + aura.fc_stype = 0x0; /* STF */ + else + aura.fc_stype = 0x3; /* STSTP */ + aura.fc_addr = (uint64_t)sq->fc; + aura.fc_hyst_bits = sq->fc_hyst_bits & 0xF; + rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0); + } - memset(&aura, 0, sizeof(aura)); - /* Disable SQ pool FC updates when SQ count updates are used */ - if (!sq->sq_cnt_ptr) - aura.fc_ena = 1; - if (roc_model_is_cn9k() || roc_errata_npa_has_no_fc_stype_ststp()) - aura.fc_stype = 0x0; /* STF */ - else - aura.fc_stype = 0x3; /* STSTP */ - aura.fc_addr = (uint64_t)sq->fc; - aura.fc_hyst_bits = sq->fc_hyst_bits & 0xF; - rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0); if (rc) goto fail; diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index f9824f6656..10087e19ef 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -82,7 +82,6 @@ static int npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura, struct npa_pool_s *pool) { - struct npa_cn20k_aq_enq_req *aura_init_req_cn20k, *pool_init_req_cn20k; struct npa_aq_enq_req *aura_init_req, *pool_init_req; struct npa_aq_enq_rsp *aura_init_rsp, *pool_init_rsp; struct mbox_dev *mdev = &m_box->dev[0]; @@ -91,6 +90,7 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; aura_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_init_req = (struct npa_aq_enq_req *)aura_init_req_cn20k; } else { @@ -104,6 +104,7 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura mbox_memcpy(&aura_init_req->aura, aura, sizeof(*aura)); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *pool_init_req_cn20k; pool_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); pool_init_req = (struct npa_aq_enq_req *)pool_init_req_cn20k; } else { @@ -139,7 +140,6 @@ npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura static int npa_aura_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura) { - struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; struct npa_aq_enq_req *aura_init_req; struct npa_aq_enq_rsp *aura_init_rsp; struct mbox *mbox; @@ -147,6 +147,7 @@ npa_aura_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura) mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_init_req_cn20k; aura_init_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_init_req = (struct npa_aq_enq_req *)aura_init_req_cn20k; } else { @@ -209,10 +210,92 @@ npa_pool_multi_bp_reset(struct npa_cn20k_aq_enq_req *pool_req) pool_req->pool_mask.bp_ena_7 = ~(pool_req->pool_mask.bp_ena_7); } +static int +npa_halo_init(struct mbox *m_box, uint32_t aura_id, struct npa_cn20k_halo_s *halo) +{ + struct npa_cn20k_aq_enq_req *req; + struct npa_aq_enq_rsp *rsp; + struct mbox *mbox; + int rc = -ENOSPC; + + mbox = mbox_get(m_box); + req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); + if (req == NULL) + goto exit; + req->aura_id = aura_id; + req->ctype = NPA_AQ_CTYPE_HALO; + req->op = NPA_AQ_INSTOP_INIT; + mbox_memcpy(&req->halo, halo, sizeof(*halo)); + + rc = mbox_process_msg(mbox, (void **)&rsp); + if (rc < 0) + goto exit; + + if (rsp->hdr.rc == 0) + rc = 0; + else + rc = NPA_ERR_HALO_INIT; +exit: + mbox_put(mbox); + return rc; +} + +static int +npa_halo_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) +{ + struct mbox_dev *mdev = &m_box->dev[0]; + struct npa_cn20k_aq_enq_req *req; + struct npa_aq_enq_rsp *rsp; + int rc = -ENOSPC, off; + struct mbox *mbox; + uint64_t ptr; + + /* Procedure for disabling an aura/pool */ + plt_delay_us(10); + + /* Clear all the pointers from the aura */ + do { + ptr = roc_npa_aura_op_alloc(aura_handle, 0); + } while (ptr); + + mbox = mbox_get(m_box); + req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); + if (req == NULL) + goto exit; + + /* Disable backpressure on halo on CN20K */ + if (roc_model_is_cn20k()) + npa_pool_multi_bp_reset(req); + + req->aura_id = aura_id; + req->ctype = NPA_AQ_CTYPE_HALO; + req->op = NPA_AQ_INSTOP_WRITE; + req->halo.ena = 0; + req->halo_mask.ena = ~req->halo_mask.ena; + + rc = mbox_process(mbox); + if (rc < 0) + goto exit; + + off = mbox->rx_start + + PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); + rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off); + + if (rsp->hdr.rc != 0) { + rc = NPA_ERR_HALO_FINI; + goto exit; + } + + rc = 0; +exit: + mbox_put(mbox); + return rc; +} + static int npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k, *pool_req_cn20k = NULL; + struct npa_cn20k_aq_enq_req *pool_req_cn20k = NULL; struct npa_aq_enq_req *aura_req, *pool_req; struct npa_aq_enq_rsp *aura_rsp, *pool_rsp; struct mbox_dev *mdev = &m_box->dev[0]; @@ -249,6 +332,7 @@ npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) pool_req->pool_mask.ena = ~pool_req->pool_mask.ena; if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -318,7 +402,6 @@ npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) static int npa_aura_fini(struct mbox *m_box, uint32_t aura_id) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_aq_enq_rsp *aura_rsp; struct ndc_sync_op *ndc_req; @@ -330,6 +413,7 @@ npa_aura_fini(struct mbox *m_box, uint32_t aura_id) mbox = mbox_get(m_box); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -439,10 +523,10 @@ roc_npa_pool_op_pc_reset(uint64_t aura_handle) int roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_lf *lf; struct mbox *mbox; + uint64_t aura_id; int rc; lf = idev_npa_obj_get(); @@ -450,6 +534,7 @@ roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) return NPA_ERR_DEVICE_NOT_BOUNDED; mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -459,8 +544,12 @@ roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena) rc = -ENOMEM; goto exit; } - aura_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle); - aura_req->ctype = NPA_AQ_CTYPE_AURA; + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + aura_req->aura_id = aura_id; + if (lf->aura_attr[aura_id].halo) + aura_req->ctype = NPA_AQ_CTYPE_HALO; + else + aura_req->ctype = NPA_AQ_CTYPE_AURA; aura_req->op = NPA_AQ_INSTOP_WRITE; aura_req->aura.aura_drop_ena = ena; @@ -575,7 +664,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, /* Block size should be cache line aligned and in range of 128B-128KB */ if (block_size % ROC_ALIGN || block_size < 128 || - block_size > ROC_NPA_MAX_BLOCK_SZ) + block_size > roc_npa_max_block_size()) return NPA_ERR_INVALID_BLOCK_SZ; /* Get aura_id from resource bitmap */ @@ -627,11 +716,21 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, /* Update pool fields */ pool->stack_base = mz->iova; pool->ena = 1; + /* In opaque mode buffer size must be 0 */ - if (!pool->nat_align) + if (!pool->nat_align) { pool->buf_size = 0; - else - pool->buf_size = block_size / ROC_ALIGN; + } else { + uint64_t buf_sz = block_size / ROC_ALIGN; + if (roc_model_is_cn20k()) { + __io struct npa_cn20k_pool_s *cn20k_pool = + (__io struct npa_cn20k_pool_s *)pool; + cn20k_pool->buf_size = buf_sz; + } else { + pool->buf_size = buf_sz; + } + } + pool->stack_max_pages = stack_size; pool->shift = plt_log2_u32(block_count); pool->shift = pool->shift < 8 ? 0 : pool->shift - 8; @@ -653,6 +752,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, lf->aura_attr[aura_id].shift = aura->shift; lf->aura_attr[aura_id].limit = aura->limit; + lf->aura_attr[aura_id].halo = 0; *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); /* Update aura count */ roc_npa_aura_op_cnt_set(*aura_handle, 0, block_count); @@ -671,6 +771,86 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, return rc; } +static int +npa_halo_alloc(struct npa_lf *lf, const uint32_t block_size, const uint32_t block_count, + struct npa_cn20k_halo_s *halo, uint64_t *aura_handle, uint32_t flags) +{ + int rc, aura_id, stack_size, alloc_size, pool_id; + char name[PLT_MEMZONE_NAMESIZE]; + const struct plt_memzone *mz; + + /* Sanity check */ + if (!lf || !halo || !aura_handle) + return NPA_ERR_PARAM; + + roc_npa_dev_lock(); + /* Get aura_id from resource bitmap */ + aura_id = find_free_aura(lf, flags); + if (aura_id < 0) { + roc_npa_dev_unlock(); + return NPA_ERR_AURA_ID_ALLOC; + } + + /* Mark aura as reserved */ + plt_bitmap_clear(lf->npa_bmp, aura_id); + + roc_npa_dev_unlock(); + rc = (aura_id < 0 || aura_id >= (int)BIT_ULL(6 + lf->aura_sz)) ? NPA_ERR_AURA_ID_ALLOC : 0; + if (rc) + goto exit; + + /* Allocate stack memory */ + stack_size = (block_count + lf->stack_pg_ptrs - 1) / lf->stack_pg_ptrs; + alloc_size = stack_size * lf->stack_pg_bytes; + + pool_id = aura_id; + mz = npa_stack_dma_alloc(lf, name, pool_id, alloc_size); + if (mz == NULL) { + rc = NPA_ERR_ALLOC; + goto aura_res_put; + } + + /* Update halo fields */ + halo->ena = 1; + halo->shift = plt_log2_u32(block_count); + halo->shift = halo->shift < 8 ? 0 : halo->shift - 8; + halo->err_int_ena = BIT(NPA_AURA_ERR_INT_AURA_ADD_OVER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER); + halo->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS); + halo->avg_con = 0; + /* Many to one reduction */ + halo->err_qint_idx = aura_id % lf->qints; + halo->stack_base = mz->iova; + /* In opaque mode buffer size must be 0 */ + halo->buf_size = !halo->nat_align ? 0 : block_size / ROC_ALIGN; + halo->stack_max_pages = stack_size; + halo->ptr_start = 0; + halo->ptr_end = ~0; + halo->stack_caching = 1; + halo->unified_ctx = 1; + + /* Issue HALO_INIT op */ + rc = npa_halo_init(lf->mbox, aura_id, halo); + if (rc) + goto stack_mem_free; + + lf->aura_attr[aura_id].shift = halo->shift; + lf->aura_attr[aura_id].halo = 1; + *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); + + return 0; + +stack_mem_free: + plt_memzone_free(mz); +aura_res_put: + roc_npa_dev_lock(); + plt_bitmap_set(lf->npa_bmp, aura_id); + roc_npa_dev_unlock(); +exit: + return rc; +} + int roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, uint32_t block_count, struct npa_aura_s *aura, @@ -713,10 +893,21 @@ roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, if (flags & ROC_NPA_FORCE_OPAQUE_MODE_F) pool->nat_align = 0; - rc = npa_aura_pool_pair_alloc(lf, block_size, block_count, aura, pool, - aura_handle, flags); + /* The pool argument will be a pointer to a npa_cn20k_halo_s structure + * when ROC_NPA_HALO_F flag is set. Note that halo and pool contexts + * are same in size and the fields that are modified here are 1:1 + * mapped in these structures. + */ + if (roc_feature_npa_has_halo() && (flags & ROC_NPA_HALO_F)) { + struct npa_cn20k_halo_s *halo = (struct npa_cn20k_halo_s *)pool; + rc = npa_halo_alloc(lf, block_size, block_count, halo, aura_handle, flags); + } else { + rc = npa_aura_pool_pair_alloc(lf, block_size, block_count, aura, pool, + aura_handle, flags); + } + if (rc) { - plt_err("Failed to alloc pool or aura rc=%d", rc); + plt_err("Failed to alloc pool/aura/halo rc=%d", rc); goto error; } @@ -773,7 +964,7 @@ npa_aura_alloc(struct npa_lf *lf, const uint32_t block_count, int pool_id, /* Many to one reduction */ aura->err_qint_idx = aura_id % lf->qints; - /* Issue AURA_INIT and POOL_INIT op */ + /* Issue AURA_INIT op */ rc = npa_aura_init(lf->mbox, aura_id, aura); if (rc) return rc; @@ -836,7 +1027,6 @@ roc_npa_aura_create(uint64_t *aura_handle, uint32_t block_count, int roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) { - struct npa_cn20k_aq_enq_req *aura_req_cn20k; struct npa_aq_enq_req *aura_req; struct npa_lf *lf; struct mbox *mbox; @@ -848,6 +1038,7 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *aura_req_cn20k; aura_req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); aura_req = (struct npa_aq_enq_req *)aura_req_cn20k; } else { @@ -872,6 +1063,28 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) return rc; } +static int +npa_halo_free(struct npa_lf *lf, uint64_t aura_handle) +{ + char name[PLT_MEMZONE_NAMESIZE]; + int aura_id, pool_id, rc; + + if (!lf || !aura_handle) + return NPA_ERR_PARAM; + + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + pool_id = aura_id; + rc = npa_halo_fini(lf->mbox, aura_id, aura_handle); + rc |= npa_stack_dma_free(lf, name, pool_id); + memset(&lf->aura_attr[aura_id], 0, sizeof(struct npa_aura_attr)); + + roc_npa_dev_lock(); + plt_bitmap_set(lf->npa_bmp, aura_id); + roc_npa_dev_unlock(); + + return rc; +} + static int npa_aura_pool_pair_free(struct npa_lf *lf, uint64_t aura_handle) { @@ -898,12 +1111,18 @@ int roc_npa_pool_destroy(uint64_t aura_handle) { struct npa_lf *lf = idev_npa_obj_get(); - int rc = 0; + int rc = 0, aura_id; plt_npa_dbg("lf=%p aura_handle=0x%" PRIx64, lf, aura_handle); - rc = npa_aura_pool_pair_free(lf, aura_handle); + aura_id = roc_npa_aura_handle_to_aura(aura_handle); + + if (lf->aura_attr[aura_id].halo) + rc = npa_halo_free(lf, aura_handle); + else + rc = npa_aura_pool_pair_free(lf, aura_handle); + if (rc) - plt_err("Failed to destroy pool or aura rc=%d", rc); + plt_err("Failed to destroy pool/aura/halo rc=%d", rc); /* Release the reference of npa */ rc |= npa_lf_fini(); @@ -952,14 +1171,13 @@ roc_npa_aura_destroy(uint64_t aura_handle) int roc_npa_pool_range_update_check(uint64_t aura_handle) { - uint64_t aura_id = roc_npa_aura_handle_to_aura(aura_handle); - struct npa_cn20k_aq_enq_req *req_cn20k; __io struct npa_pool_s *pool; struct npa_aq_enq_req *req; struct npa_aq_enq_rsp *rsp; struct npa_aura_lim *lim; struct mbox *mbox; struct npa_lf *lf; + uint64_t aura_id; int rc; lf = idev_npa_obj_get(); @@ -970,6 +1188,7 @@ roc_npa_pool_range_update_check(uint64_t aura_handle) mbox = mbox_get(lf->mbox); if (roc_model_is_cn20k()) { + struct npa_cn20k_aq_enq_req *req_cn20k; req_cn20k = mbox_alloc_msg_npa_cn20k_aq_enq(mbox); req = (struct npa_aq_enq_req *)req_cn20k; } else { @@ -980,8 +1199,12 @@ roc_npa_pool_range_update_check(uint64_t aura_handle) goto exit; } + aura_id = roc_npa_aura_handle_to_aura(aura_handle); req->aura_id = aura_id; - req->ctype = NPA_AQ_CTYPE_POOL; + if (lf->aura_attr[aura_id].halo) + req->ctype = NPA_AQ_CTYPE_HALO; + else + req->ctype = NPA_AQ_CTYPE_POOL; req->op = NPA_AQ_INSTOP_READ; rc = mbox_process_msg(mbox, (void *)&rsp); @@ -1140,7 +1363,6 @@ int roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf, uint8_t bp_thresh, bool enable) { - /* TODO: Add support for CN20K */ uint32_t aura_id = roc_npa_aura_handle_to_aura(aura_handle); struct npa_lf *lf = idev_npa_obj_get(); struct npa_aq_enq_req *req; diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 336a43f95c..18808e5873 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -21,7 +21,9 @@ #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1) -#define ROC_NPA_MAX_BLOCK_SZ (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN9K (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN10K (128 * 1024) +#define ROC_NPA_MAX_BLOCK_SZ_CN20K (256 * 1024) #define ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS 512 #define ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS 15U #define ROC_CN10K_NPA_BATCH_FREE_BURST_MAX 16U @@ -36,6 +38,17 @@ */ #define ROC_CN9K_NPA_BULK_ALLOC_MAX_PTRS 30 +static inline uint32_t +roc_npa_max_block_size(void) +{ + if (roc_model_is_cn20k()) + return ROC_NPA_MAX_BLOCK_SZ_CN20K; + else if (roc_model_is_cn10k()) + return ROC_NPA_MAX_BLOCK_SZ_CN10K; + else + return ROC_NPA_MAX_BLOCK_SZ_CN9K; +} + /* * Generate 64bit handle to have optimized alloc and free aura operation. * 0 - ROC_AURA_ID_MASK for storing the aura_id. @@ -767,8 +780,9 @@ int __roc_api roc_npa_dev_init(struct roc_npa *roc_npa); int __roc_api roc_npa_dev_fini(struct roc_npa *roc_npa); /* Flags to pool create */ -#define ROC_NPA_ZERO_AURA_F BIT(0) -#define ROC_NPA_FORCE_OPAQUE_MODE_F BIT(1) +#define ROC_NPA_ZERO_AURA_F BIT(0) +#define ROC_NPA_FORCE_OPAQUE_MODE_F BIT(1) +#define ROC_NPA_HALO_F BIT(2) /* Enumerations */ enum roc_npa_buf_type { diff --git a/drivers/common/cnxk/roc_npa_debug.c b/drivers/common/cnxk/roc_npa_debug.c index 9a16f481a8..e64696730f 100644 --- a/drivers/common/cnxk/roc_npa_debug.c +++ b/drivers/common/cnxk/roc_npa_debug.c @@ -86,10 +86,171 @@ npa_aura_dump(__io struct npa_aura_s *aura) npa_dump("W6: thresh\t\t%" PRIx64 "\n", (uint64_t)aura->thresh); } +static inline void +npa_cn20k_pool_dump(__io struct npa_cn20k_pool_s *pool) +{ + npa_dump("W0: Stack base\t\t0x%" PRIx64 "\n", pool->stack_base); + npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d", + pool->ena, pool->nat_align, pool->stack_caching); + npa_dump("W1: buf_offset \t\t%d", pool->buf_offset); + npa_dump("W1: buf_size \t\t%d\nW1: ref_cnt_prof \t%d", + pool->buf_size, pool->ref_cnt_prof); + + npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n", + pool->stack_max_pages, pool->stack_pages); + + npa_dump("W3: bp_0 \t\t%d\nW3: bp_1 \t\t%d\nW3: bp_2 \t\t%d", + pool->bp_0, pool->bp_1, pool->bp_2); + npa_dump("W3: bp_3 \t\t%d\nW3: bp_4 \t\t%d\nW3: bp_5 \t\t%d", + pool->bp_3, pool->bp_4, pool->bp_5); + npa_dump("W3: bp_6 \t\t%d\nW3: bp_7 \t\t%d", pool->bp_6, pool->bp_7); + npa_dump("W3: bp_ena_0 \t\t%d\nW3: bp_ena_1 \t\t%d", pool->bp_ena_0, + pool->bp_ena_1); + npa_dump("W3: bp_ena_2 \t\t%d\nW3: bp_ena_3 \t\t%d", pool->bp_ena_2, + pool->bp_ena_3); + npa_dump("W3: bp_ena_4 \t\t%d\nW3: bp_ena_5 \t\t%d", pool->bp_ena_4, + pool->bp_ena_5); + npa_dump("W3: bp_ena_6 \t\t%d\nW3: bp_ena_7 \t\t%d\n", pool->bp_6, + pool->bp_7); + + npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d", + pool->stack_offset, pool->shift, pool->avg_level); + npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d", + pool->avg_con, pool->fc_ena, pool->fc_stype); + npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d", + pool->fc_hyst_bits, pool->fc_up_crossing); + npa_dump("W4: update_time\t\t%d\n", pool->update_time); + + npa_dump("W5: fc_addr\t\t0x%" PRIx64 "\n", pool->fc_addr); + + npa_dump("W6: ptr_start\t\t0x%" PRIx64 "\n", pool->ptr_start); + + npa_dump("W7: ptr_end\t\t0x%" PRIx64 "\n", pool->ptr_end); + + npa_dump("W8: bpid_0 \t\t%d", pool->bpid_0); + npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d", pool->err_int, + pool->err_int_ena); + npa_dump("W8: thresh_int\t\t%d", pool->thresh_int); + npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d", + pool->thresh_int_ena, pool->thresh_up); + npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n", + pool->thresh_qint_idx, pool->err_qint_idx); + npa_dump("W9: thresh\t\t%" PRIx64 "", (uint64_t)pool->thresh); + npa_dump("W9: fc_msh_dst \t\t%d", pool->fc_msh_dst); + npa_dump("W9: op_dpc_ena \t\t%d\nW9: op_dpc_set \t\t%d", + pool->op_dpc_ena, pool->op_dpc_set); + npa_dump("W9: stream_ctx \t\t%d", pool->stream_ctx); +} + +static inline void +npa_halo_dump(__io struct npa_cn20k_halo_s *halo) +{ + npa_dump("W0: Stack base\t\t0x%" PRIx64 "\n", halo->stack_base); + npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d", + halo->ena, halo->nat_align, halo->stack_caching); + npa_dump("W1: buf_offset\t\t%d\nW1: buf_size\t\t%d", + halo->buf_offset, halo->buf_size); + npa_dump("W1: ref_cnt_prof \t%d\n", halo->ref_cnt_prof); + + npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n", + halo->stack_max_pages, halo->stack_pages); + + npa_dump("W3: bp_0 \t\t%d\nW3: bp_1 \t\t%d\nW3: bp_2 \t\t%d", + halo->bp_0, halo->bp_1, halo->bp_2); + npa_dump("W3: bp_3 \t\t%d\nW3: bp_4 \t\t%d\nW3: bp_5 \t\t%d", + halo->bp_3, halo->bp_4, halo->bp_5); + npa_dump("W3: bp_6 \t\t%d\nW3: bp_7 \t\t%d", halo->bp_6, halo->bp_7); + + npa_dump("W3: bp_ena_0 \t\t%d\nW3: bp_ena_1 \t\t%d", halo->bp_ena_0, + halo->bp_ena_1); + npa_dump("W3: bp_ena_2 \t\t%d\nW3: bp_ena_3 \t\t%d", halo->bp_ena_2, + halo->bp_ena_3); + npa_dump("W3: bp_ena_4 \t\t%d\nW3: bp_ena_5 \t\t%d", halo->bp_ena_4, + halo->bp_ena_5); + npa_dump("W3: bp_ena_6 \t\t%d\nW3: bp_ena_7 \t\t%d\n", halo->bp_6, + halo->bp_7); + + npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d", + halo->stack_offset, halo->shift, halo->avg_level); + npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d", + halo->avg_con, halo->fc_ena, halo->fc_stype); + npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d", + halo->fc_hyst_bits, halo->fc_up_crossing); + npa_dump("W4: update_time\t\t%d\n", halo->update_time); + + npa_dump("W5: fc_addr\t\t0x%" PRIx64 "\n", halo->fc_addr); + + npa_dump("W6: ptr_start\t\t0x%" PRIx64 "\n", halo->ptr_start); + + npa_dump("W7: ptr_end\t\t0x%" PRIx64 "\n", halo->ptr_end); + npa_dump("W8: bpid_0 \t\t%d", halo->bpid_0); + npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d", halo->err_int, + halo->err_int_ena); + npa_dump("W8: thresh_int\t\t%d", halo->thresh_int); + + npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d", + halo->thresh_int_ena, halo->thresh_up); + npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n", + halo->thresh_qint_idx, halo->err_qint_idx); + npa_dump("W9: thresh \t\t%" PRIx64 "\nW9: fc_msh_dst \t\t%d", + (unsigned long)halo->thresh, halo->fc_msh_dst); + npa_dump("W9: op_dpc_ena \t\t%d\nW9: op_dpc_set \t\t%d", + halo->op_dpc_ena, halo->op_dpc_set); + npa_dump("W9: stream_ctx \t\t%d\nW9: unified_ctx \t%d", + halo->stream_ctx, halo->unified_ctx); +} + +static inline void +npa_cn20k_aura_dump(__io struct npa_cn20k_aura_s *aura) +{ + npa_dump("W0: Pool addr\t\t0x%" PRIx64 "\n", aura->pool_addr); + + npa_dump("W1: ena\t\t\t%d\nW1: pool caching\t%d", aura->ena, + aura->pool_caching); + npa_dump("W1: avg con\t\t%d\nW1: pool drop ena\t%d", aura->avg_con, + aura->pool_drop_ena); + npa_dump("W1: aura drop ena\t%d", aura->aura_drop_ena); + npa_dump("W1: bp_ena\t\t%d", aura->bp_ena); + npa_dump("W1: aura drop\t\t%d\nW1: aura shift\t\t%d", aura->aura_drop, + aura->shift); + npa_dump("W1: avg_level\t\t%d\n", aura->avg_level); + + npa_dump("W2: count\t\t%" PRIx64 "", (uint64_t)aura->count); + npa_dump("W2: bpid\t\t%d\n", aura->bpid); + + npa_dump("W3: limit\t\t%" PRIx64 "", (uint64_t)aura->limit); + npa_dump("W3: bp\t\t\t%d", aura->bp); + npa_dump("W3: fc_ena\t\t%d", aura->fc_ena); + npa_dump("W3: fc_up_crossing\t%d\nW3: fc_stype\t\t%d", + aura->fc_up_crossing, aura->fc_stype); + + npa_dump("W3: fc_hyst_bits\t%d\n", aura->fc_hyst_bits); + + npa_dump("W4: fc_addr\t\t0x%" PRIx64 "\n", aura->fc_addr); + + npa_dump("W5: pool_drop\t\t%d\nW5: update_time\t\t%d", aura->pool_drop, + aura->update_time); + npa_dump("W5: err_int\t\t%d", aura->err_int); + npa_dump("W5: err_int_ena\t\t%d\nW5: thresh_int\t\t%d", + aura->err_int_ena, aura->thresh_int); + npa_dump("W5: thresh_int_ena\t%d", aura->thresh_int_ena); + + npa_dump("W5: thresh_up\t\t%d\nW5: thresh_qint_idx\t%d", + aura->thresh_up, aura->thresh_qint_idx); + npa_dump("W5: err_qint_idx\t%d\n", aura->err_qint_idx); + + npa_dump("W6: thresh\t\t%" PRIx64 "", (uint64_t)aura->thresh); + npa_dump("W6: fc_msh_dst \t\t%d", aura->fc_msh_dst); + npa_dump("W6: op_dpc_ena \t\t%d\nW6: op_dpc_set \t\t%d", + aura->op_dpc_ena, aura->op_dpc_set); + npa_dump("W6: stream_ctx \t\t%d", aura->stream_ctx); +} + int roc_npa_ctx_dump(void) { struct npa_cn20k_aq_enq_req *aq_cn20k; + struct npa_cn20k_aq_enq_rsp *rsp_cn20k; struct npa_aq_enq_rsp *rsp; struct npa_aq_enq_req *aq; struct mbox *mbox; @@ -103,7 +264,7 @@ roc_npa_ctx_dump(void) mbox = mbox_get(lf->mbox); for (q = 0; q < lf->nr_pools; q++) { - /* Skip disabled POOL */ + /* Skip disabled AURA */ if (plt_bitmap_get(lf->npa_bmp, q)) continue; @@ -118,21 +279,34 @@ roc_npa_ctx_dump(void) goto exit; } aq->aura_id = q; - aq->ctype = NPA_AQ_CTYPE_POOL; aq->op = NPA_AQ_INSTOP_READ; + if (lf->aura_attr[q].halo) { + aq->ctype = NPA_AQ_CTYPE_HALO; + rc = mbox_process_msg(mbox, (void *)&rsp_cn20k); + } else { + aq->ctype = NPA_AQ_CTYPE_AURA; + rc = mbox_process_msg(mbox, (void *)&rsp); + } - rc = mbox_process_msg(mbox, (void *)&rsp); if (rc) { - plt_err("Failed to get pool(%d) context", q); + plt_err("Failed to get aura/halo(%d) context", q); goto exit; } - npa_dump("============== pool=%d ===============\n", q); - npa_pool_dump(&rsp->pool); + if (lf->aura_attr[q].halo) { + npa_dump("============== halo=%d ===============\n", q); + npa_halo_dump(&rsp_cn20k->halo); + } else { + npa_dump("============== aura=%d ===============\n", q); + if (roc_model_is_cn20k()) + npa_cn20k_aura_dump(&rsp_cn20k->aura); + else + npa_aura_dump(&rsp->aura); + } } for (q = 0; q < lf->nr_pools; q++) { - /* Skip disabled AURA */ - if (plt_bitmap_get(lf->npa_bmp, q)) + /* Skip halo and disabled POOL */ + if (plt_bitmap_get(lf->npa_bmp, q) || lf->aura_attr[q].halo) continue; if (roc_model_is_cn20k()) { @@ -146,16 +320,19 @@ roc_npa_ctx_dump(void) goto exit; } aq->aura_id = q; - aq->ctype = NPA_AQ_CTYPE_AURA; + aq->ctype = NPA_AQ_CTYPE_POOL; aq->op = NPA_AQ_INSTOP_READ; rc = mbox_process_msg(mbox, (void *)&rsp); if (rc) { - plt_err("Failed to get aura(%d) context", q); + plt_err("Failed to get pool(%d) context", q); goto exit; } - npa_dump("============== aura=%d ===============\n", q); - npa_aura_dump(&rsp->aura); + npa_dump("============== pool=%d ===============\n", q); + if (roc_model_is_cn20k()) + npa_cn20k_pool_dump(&rsp_cn20k->pool); + else + npa_pool_dump(&rsp->pool); } exit: diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h index 0223e4a438..e437fe831a 100644 --- a/drivers/common/cnxk/roc_npa_priv.h +++ b/drivers/common/cnxk/roc_npa_priv.h @@ -14,6 +14,8 @@ enum npa_error_status { NPA_ERR_AURA_POOL_FINI = -517, NPA_ERR_BASE_INVALID = -518, NPA_ERR_DEVICE_NOT_BOUNDED = -519, + NPA_ERR_HALO_INIT = -520, + NPA_ERR_HALO_FINI = -521, }; struct npa_lf { @@ -55,6 +57,7 @@ struct npa_aura_attr { uint64_t shift; uint64_t limit; uint8_t bp_ena; + bool halo; union { uint8_t bp; /* CN9K, CN10K */ uint8_t bp_thresh[8]; /* CN20K */ diff --git a/drivers/common/cnxk/roc_platform_base_symbols.c b/drivers/common/cnxk/roc_platform_base_symbols.c index 43095741f5..79dd18fbd7 100644 --- a/drivers/common/cnxk/roc_platform_base_symbols.c +++ b/drivers/common/cnxk/roc_platform_base_symbols.c @@ -85,6 +85,8 @@ RTE_EXPORT_INTERNAL_SYMBOL(roc_hash_sha256_gen) RTE_EXPORT_INTERNAL_SYMBOL(roc_hash_sha512_gen) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_maxpools_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_maxpools_set) +RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_halo_ena_get) +RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_npa_halo_ena_set) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_lmt_base_addr_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_num_lmtlines_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_cpt_get) diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 1d82e5b978..b674dcf70c 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -834,8 +834,6 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, uint32_t nb_xae, uint32_t xae_waes, uint32_t xaq_buf_size, uint16_t nb_hwgrp) { - struct npa_pool_s pool; - struct npa_aura_s aura; plt_iova_t iova; uint32_t i; int rc; @@ -877,15 +875,32 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, goto free_fc; } - memset(&pool, 0, sizeof(struct npa_pool_s)); - pool.nat_align = 1; + if (roc_feature_npa_has_halo() && xaq->halo_ena) { + struct npa_cn20k_halo_s halo; + + memset(&halo, 0, sizeof(struct npa_cn20k_halo_s)); + halo.nat_align = 1; + halo.fc_ena = 1; + halo.fc_addr = (uint64_t)xaq->fc; + halo.fc_hyst_bits = 0; /* Store count on all updates */ + halo.unified_ctx = 1; + rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, + NULL, (struct npa_pool_s *)&halo, ROC_NPA_HALO_F); + } else { + struct npa_pool_s pool; + struct npa_aura_s aura; + + memset(&pool, 0, sizeof(struct npa_pool_s)); + pool.nat_align = 1; + + memset(&aura, 0, sizeof(aura)); + aura.fc_ena = 1; + aura.fc_addr = (uint64_t)xaq->fc; + aura.fc_hyst_bits = 0; /* Store count on all updates */ + rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, + &aura, &pool, 0); + } - memset(&aura, 0, sizeof(aura)); - aura.fc_ena = 1; - aura.fc_addr = (uint64_t)xaq->fc; - aura.fc_hyst_bits = 0; /* Store count on all updates */ - rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, - &aura, &pool, 0); if (rc) { plt_err("Failed to create XAQ pool"); goto npa_fail; diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index f1ad34bcc7..9d8356abb1 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -43,6 +43,7 @@ struct roc_sso_xaq_data { uint32_t nb_xae; uint32_t xaq_lmt; uint64_t aura_handle; + int halo_ena; void *fc; void *mem; }; -- 2.48.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v4 1/2] common/cnxk: add support for halos 2026-02-17 10:39 ` [PATCH v4 1/2] common/cnxk: add support for halos Nawal Kishor @ 2026-02-19 17:19 ` Stephen Hemminger 0 siblings, 0 replies; 18+ messages in thread From: Stephen Hemminger @ 2026-02-19 17:19 UTC (permalink / raw) To: Nawal Kishor Cc: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao, Harman Kalra, jerinj, asekhar On Tue, 17 Feb 2026 16:09:21 +0530 Nawal Kishor <nkishor@marvell.com> wrote: > +int > +roc_idev_npa_halo_ena_get(void) > +{ > + struct idev_cfg *idev; > + int halo_ena; > + > + idev = idev_get_cfg(); > + halo_ena = 0; > + if (idev != NULL) > + halo_ena = __atomic_load_n(&idev->halo_ena, __ATOMIC_ACQUIRE); Do not use __atomic_load_n, DPDK has migrated to rte_atomic_load_explicit > diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h > index 98b6286bfe..dde555535b 100644 > --- a/drivers/common/cnxk/roc_idev_priv.h > +++ b/drivers/common/cnxk/roc_idev_priv.h > @@ -30,6 +30,7 @@ struct idev_cfg { > struct npa_lf *npa; > uint16_t npa_refcnt; > uint32_t max_pools; > + int halo_ena; Using int for a flag value is legacy C code style. Use bool to save space and have some type safety. > + if (roc_feature_npa_has_halo() && roc_nix->sqb_halo_ena) { > + struct npa_cn20k_halo_s halo; > + > + memset(&halo, 0, sizeof(struct npa_cn20k_halo_s)); > + halo.nat_align = 1; > + halo.fc_ena = 1; > + halo.fc_stype = 0x3; /* STSTP */ > + halo.fc_addr = (uint64_t)sq->fc; > + halo.fc_hyst_bits = 0; /* Store count on all updates */ > + halo.unified_ctx = 1; Using structure initialization is preferred over memset and individual values. ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 2/2] mempool/cnxk: add halo support in mempool 2026-02-17 10:39 ` [PATCH v4 " Nawal Kishor 2026-02-17 10:39 ` [PATCH v4 1/2] common/cnxk: add support for halos Nawal Kishor @ 2026-02-17 10:39 ` Nawal Kishor 2026-02-19 17:33 ` Stephen Hemminger 1 sibling, 1 reply; 18+ messages in thread From: Nawal Kishor @ 2026-02-17 10:39 UTC (permalink / raw) To: dev, Ashwin Sekhar T K, Pavan Nikhilesh; +Cc: jerinj, Nawal Kishor This patch adds the support of halos in CN20K mempool driver. It introduces a new devargs parameter "halo_ena" to enable or disable halo feature. If halo_ena is set to 1, halos will be enabled for NPA pools created by the mempool driver. Signed-off-by: Nawal Kishor <nkishor@marvell.com> --- doc/guides/mempool/cnxk.rst | 24 ++++++++-- drivers/mempool/cnxk/cn10k_mempool_ops.c | 19 ++++---- drivers/mempool/cnxk/cn20k_mempool_ops.c | 60 ++++++++++++++++++++++++ drivers/mempool/cnxk/cn9k_mempool_ops.c | 2 +- drivers/mempool/cnxk/cnxk_mempool.c | 40 +++++++++++----- drivers/mempool/cnxk/cnxk_mempool.h | 16 ++++++- drivers/mempool/cnxk/cnxk_mempool_ops.c | 11 +++-- drivers/mempool/cnxk/meson.build | 1 + 8 files changed, 141 insertions(+), 32 deletions(-) create mode 100644 drivers/mempool/cnxk/cn20k_mempool_ops.c diff --git a/doc/guides/mempool/cnxk.rst b/doc/guides/mempool/cnxk.rst index 3d0729245a..178ff99acf 100644 --- a/doc/guides/mempool/cnxk.rst +++ b/doc/guides/mempool/cnxk.rst @@ -5,7 +5,7 @@ cnxk NPA Mempool Driver ======================= The cnxk NPA PMD (**librte_mempool_cnxk**) provides mempool driver support for -the integrated mempool device found in **Marvell OCTEON CN9K/CN10K** SoC family. +the integrated mempool device found in **Marvell OCTEON CN9K/CN10K/CN20K** SoC family. More information about cnxk SoC can be found at `Marvell Official Website <https://www.marvell.com/embedded-processors/infrastructure-processors/>`_. @@ -30,6 +30,11 @@ CN10k NPA supports: - Batch dequeue of up to 512 pointers with single instruction. - Batch enqueue of up to 15 pointers with single instruction. +CN20k NPA supports: + +- HALO support for 1:1 aura-pool mapping, which uses a single unified context + instead of separate aura and pool contexts, saving HW context space. + Prerequisites and Compilation procedure --------------------------------------- @@ -56,11 +61,24 @@ Runtime Config Options With the above configuration, the driver will set up only 512 mempools for the given application to save HW resources. +- ``HALO enable`` (default ``0``) + + The HALO feature is available on CN20K platforms and allows 1:1 aura-pool + mapping to use a single unified context instead of separate aura and pool + contexts, saving HW context space. This parameter enables or disables HALO + support for NPA pools created by the mempool driver. + For example:: + + -a 0002:02:00.0,halo_ena=1 + + With the above configuration, HALO support will be enabled for mempools created + on CN20K platforms. + .. note:: Since this configuration is per application, the end user needs to - provide ``max_pools`` parameter to the first PCIe device probed by the given - application. + provide ``max_pools`` and/or ``halo_ena`` parameter to the first PCIe device + probed by the given application. Debugging Options ~~~~~~~~~~~~~~~~~ diff --git a/drivers/mempool/cnxk/cn10k_mempool_ops.c b/drivers/mempool/cnxk/cn10k_mempool_ops.c index a5be0ccafe..09f900a850 100644 --- a/drivers/mempool/cnxk/cn10k_mempool_ops.c +++ b/drivers/mempool/cnxk/cn10k_mempool_ops.c @@ -2,9 +2,6 @@ * Copyright(C) 2021 Marvell. */ -#include <rte_mempool.h> - -#include "roc_api.h" #include "cnxk_mempool.h" #define BATCH_ALLOC_SZ ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS @@ -79,7 +76,7 @@ batch_op_data_set(uint64_t pool_id, struct batch_op_data *op_data) batch_op_data_tbl[aura] = op_data; } -static int +int batch_op_init(struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -109,7 +106,7 @@ batch_op_init(struct rte_mempool *mp) return 0; } -static void +void batch_op_fini(struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -149,7 +146,7 @@ batch_op_fini(struct rte_mempool *mp) rte_wmb(); } -static int __rte_hot +int __rte_hot cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, unsigned int n) { @@ -181,7 +178,7 @@ cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, return 0; } -static unsigned int +unsigned int cn10k_mempool_get_count(const struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -326,7 +323,7 @@ mempool_deq_batch_sync(struct rte_mempool *mp, void **obj_table, unsigned int n) return count; } -static int __rte_hot +int __rte_hot cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n) { struct batch_op_data *op_data; @@ -353,7 +350,7 @@ cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n) return 0; } -static int +int cn10k_mempool_alloc(struct rte_mempool *mp) { uint32_t block_size; @@ -376,7 +373,7 @@ cn10k_mempool_alloc(struct rte_mempool *mp) block_size += padding; } - rc = cnxk_mempool_alloc(mp); + rc = cnxk_mempool_alloc(mp, 0); if (rc) return rc; @@ -392,7 +389,7 @@ cn10k_mempool_alloc(struct rte_mempool *mp) return rc; } -static void +void cn10k_mempool_free(struct rte_mempool *mp) { batch_op_fini(mp); diff --git a/drivers/mempool/cnxk/cn20k_mempool_ops.c b/drivers/mempool/cnxk/cn20k_mempool_ops.c new file mode 100644 index 0000000000..f8817d8743 --- /dev/null +++ b/drivers/mempool/cnxk/cn20k_mempool_ops.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2025 Marvell. + */ + +#include "cnxk_mempool.h" + +static int +cn20k_mempool_alloc(struct rte_mempool *mp) +{ + uint32_t block_size; + int halo_ena, rc; + size_t padding; + + block_size = mp->elt_size + mp->header_size + mp->trailer_size; + /* Align header size to ROC_ALIGN */ + if (mp->header_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(mp->header_size, ROC_ALIGN) - + mp->header_size; + mp->header_size += padding; + block_size += padding; + } + + /* Align block size to ROC_ALIGN */ + if (block_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(block_size, ROC_ALIGN) - block_size; + mp->trailer_size += padding; + block_size += padding; + } + + /* Get halo status */ + halo_ena = roc_idev_npa_halo_ena_get(); + + rc = cnxk_mempool_alloc(mp, halo_ena ? ROC_NPA_HALO_F : 0); + if (rc) + return rc; + + rc = batch_op_init(mp); + if (rc) { + plt_err("Failed to init batch alloc mem rc=%d", rc); + goto error; + } + + return 0; +error: + cnxk_mempool_free(mp); + return rc; +} + +static struct rte_mempool_ops cn20k_mempool_ops = { + .name = "cn20k_mempool_ops", + .alloc = cn20k_mempool_alloc, + .free = cn10k_mempool_free, + .enqueue = cn10k_mempool_enq, + .dequeue = cn10k_mempool_deq, + .get_count = cn10k_mempool_get_count, + .calc_mem_size = cnxk_mempool_calc_mem_size, + .populate = cnxk_mempool_populate, +}; + +RTE_MEMPOOL_REGISTER_OPS(cn20k_mempool_ops); diff --git a/drivers/mempool/cnxk/cn9k_mempool_ops.c b/drivers/mempool/cnxk/cn9k_mempool_ops.c index b7967f8085..8248071cb7 100644 --- a/drivers/mempool/cnxk/cn9k_mempool_ops.c +++ b/drivers/mempool/cnxk/cn9k_mempool_ops.c @@ -72,7 +72,7 @@ cn9k_mempool_alloc(struct rte_mempool *mp) padding = ((block_size / ROC_ALIGN) % 2) ? 0 : ROC_ALIGN; mp->trailer_size += padding; - return cnxk_mempool_alloc(mp); + return cnxk_mempool_alloc(mp, 0); } static struct rte_mempool_ops cn9k_mempool_ops = { diff --git a/drivers/mempool/cnxk/cnxk_mempool.c b/drivers/mempool/cnxk/cnxk_mempool.c index 6ff11d8004..6939fccff4 100644 --- a/drivers/mempool/cnxk/cnxk_mempool.c +++ b/drivers/mempool/cnxk/cnxk_mempool.c @@ -18,6 +18,7 @@ #define CNXK_NPA_DEV_NAME RTE_STR(cnxk_npa_dev_) #define CNXK_NPA_DEV_NAME_LEN (sizeof(CNXK_NPA_DEV_NAME) + PCI_PRI_STR_SIZE) #define CNXK_NPA_MAX_POOLS_PARAM "max_pools" +#define CNXK_NPA_HALO_ENA_PARAM "halo_ena" static inline uint32_t npa_aura_size_to_u32(uint8_t val) @@ -46,30 +47,46 @@ parse_max_pools_handler(const char *key, const char *value, void *extra_args) return 0; } -static inline uint32_t -parse_max_pools(struct rte_devargs *devargs) +static int +parse_halo_ena_handler(const char *key, const char *value, void *extra_args) +{ + RTE_SET_USED(key); + uint8_t val; + + val = atoi(value); + if (val != 0 && val != 1) + return -EINVAL; + + *(uint8_t *)extra_args = val; + return 0; +} + +static int +cnxk_mempool_plt_parse_devargs(struct rte_pci_device *pci_dev) { uint32_t max_pools = npa_aura_size_to_u32(NPA_AURA_SZ_128); + struct rte_devargs *devargs = pci_dev->device.devargs; struct rte_kvargs *kvlist; + uint32_t halo_ena = 0; if (devargs == NULL) - goto exit; + goto null_devargs; kvlist = rte_kvargs_parse(devargs->args, NULL); if (kvlist == NULL) goto exit; rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM, &parse_max_pools_handler, &max_pools); + rte_kvargs_process(kvlist, CNXK_NPA_HALO_ENA_PARAM, + &parse_halo_ena_handler, &halo_ena); rte_kvargs_free(kvlist); -exit: - return max_pools; -} -static int -cnxk_mempool_plt_parse_devargs(struct rte_pci_device *pci_dev) -{ - roc_idev_npa_maxpools_set(parse_max_pools(pci_dev->device.devargs)); +null_devargs: + roc_idev_npa_maxpools_set(max_pools); + roc_idev_npa_halo_ena_set(halo_ena); return 0; +exit: + return -EINVAL; } static inline char * @@ -201,7 +218,8 @@ RTE_PMD_REGISTER_PCI(mempool_cnxk, npa_pci); RTE_PMD_REGISTER_PCI_TABLE(mempool_cnxk, npa_pci_map); RTE_PMD_REGISTER_KMOD_DEP(mempool_cnxk, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(mempool_cnxk, - CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>"); + CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>" + CNXK_NPA_HALO_ENA_PARAM "=<0-1>"); RTE_INIT(cnxk_mempool_parse_devargs) { diff --git a/drivers/mempool/cnxk/cnxk_mempool.h b/drivers/mempool/cnxk/cnxk_mempool.h index 669e617952..941290061e 100644 --- a/drivers/mempool/cnxk/cnxk_mempool.h +++ b/drivers/mempool/cnxk/cnxk_mempool.h @@ -7,6 +7,8 @@ #include <rte_mempool.h> +#include "roc_api.h" + enum cnxk_mempool_flags { /* This flag is used to ensure that only aura zero is allocated. * If aura zero is not available, then mempool creation fails. @@ -47,7 +49,7 @@ int cnxk_mempool_populate(struct rte_mempool *mp, unsigned int max_objs, void *vaddr, rte_iova_t iova, size_t len, rte_mempool_populate_obj_cb_t *obj_cb, void *obj_cb_arg); -int cnxk_mempool_alloc(struct rte_mempool *mp); +int cnxk_mempool_alloc(struct rte_mempool *mp, uint64_t roc_flags); void cnxk_mempool_free(struct rte_mempool *mp); int __rte_hot cnxk_mempool_enq(struct rte_mempool *mp, void *const *obj_table, @@ -55,6 +57,16 @@ int __rte_hot cnxk_mempool_enq(struct rte_mempool *mp, void *const *obj_table, int __rte_hot cnxk_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n); +int batch_op_init(struct rte_mempool *mp); +void batch_op_fini(struct rte_mempool *mp); +int __rte_hot cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, + unsigned int n); +unsigned int cn10k_mempool_get_count(const struct rte_mempool *mp); +int __rte_hot cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, + unsigned int n); +int cn10k_mempool_alloc(struct rte_mempool *mp); +void cn10k_mempool_free(struct rte_mempool *mp); + int cn10k_mempool_plt_init(void); -#endif +#endif /* _CNXK_MEMPOOL_H_ */ diff --git a/drivers/mempool/cnxk/cnxk_mempool_ops.c b/drivers/mempool/cnxk/cnxk_mempool_ops.c index 5c7fcea487..01b6247fbb 100644 --- a/drivers/mempool/cnxk/cnxk_mempool_ops.c +++ b/drivers/mempool/cnxk/cnxk_mempool_ops.c @@ -70,9 +70,9 @@ cnxk_mempool_calc_mem_size(const struct rte_mempool *mp, uint32_t obj_num, } int -cnxk_mempool_alloc(struct rte_mempool *mp) +cnxk_mempool_alloc(struct rte_mempool *mp, uint64_t roc_flags) { - uint32_t block_count, flags, roc_flags = 0; + uint32_t block_count, flags; uint64_t aura_handle = 0; struct npa_aura_s aura; struct npa_pool_s pool; @@ -98,7 +98,7 @@ cnxk_mempool_alloc(struct rte_mempool *mp) flags = CNXK_MEMPOOL_FLAGS(mp); if (flags & CNXK_MEMPOOL_F_ZERO_AURA) { - roc_flags = ROC_NPA_ZERO_AURA_F; + roc_flags |= ROC_NPA_ZERO_AURA_F; } else if (flags & CNXK_MEMPOOL_F_CUSTOM_AURA) { struct npa_aura_s *paura; @@ -192,9 +192,12 @@ cnxk_mempool_plt_init(void) if (roc_model_is_cn9k()) { rte_mbuf_set_platform_mempool_ops("cn9k_mempool_ops"); - } else if (roc_model_is_cn10k() || roc_model_is_cn20k()) { + } else if (roc_model_is_cn10k()) { rte_mbuf_set_platform_mempool_ops("cn10k_mempool_ops"); rc = cn10k_mempool_plt_init(); + } else if (roc_model_is_cn20k()) { + rte_mbuf_set_platform_mempool_ops("cn20k_mempool_ops"); + rc = cn10k_mempool_plt_init(); } return rc; } diff --git a/drivers/mempool/cnxk/meson.build b/drivers/mempool/cnxk/meson.build index e388cce26a..7722264320 100644 --- a/drivers/mempool/cnxk/meson.build +++ b/drivers/mempool/cnxk/meson.build @@ -14,6 +14,7 @@ sources = files( 'cnxk_mempool_telemetry.c', 'cn9k_mempool_ops.c', 'cn10k_mempool_ops.c', + 'cn20k_mempool_ops.c', 'cn10k_hwpool_ops.c', ) -- 2.48.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v4 2/2] mempool/cnxk: add halo support in mempool 2026-02-17 10:39 ` [PATCH v4 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor @ 2026-02-19 17:33 ` Stephen Hemminger 0 siblings, 0 replies; 18+ messages in thread From: Stephen Hemminger @ 2026-02-19 17:33 UTC (permalink / raw) To: Nawal Kishor; +Cc: dev, Ashwin Sekhar T K, Pavan Nikhilesh, jerinj On Tue, 17 Feb 2026 16:09:22 +0530 Nawal Kishor <nkishor@marvell.com> wrote: > +static struct rte_mempool_ops cn20k_mempool_ops = { > + .name = "cn20k_mempool_ops", > + .alloc = cn20k_mempool_alloc, > + .free = cn10k_mempool_free, > + .enqueue = cn10k_mempool_enq, > + .dequeue = cn10k_mempool_deq, > + .get_count = cn10k_mempool_get_count, > + .calc_mem_size = cnxk_mempool_calc_mem_size, > + .populate = cnxk_mempool_populate, > +}; > + If possible ops structures should be const to protect from modification. > +static int > +parse_halo_ena_handler(const char *key, const char *value, void *extra_args) > +{ > + RTE_SET_USED(key); Prefer __rte_unused attribute > + uint8_t val; > + > + val = atoi(value); > + if (val != 0 && val != 1) > + return -EINVAL; > + > + *(uint8_t *)extra_args = val; > + return 0; > +} Using atoi() allows non-string values. You should be using a more robust handler. Actually kvargs should have handlers for common types, but that is an enhancement. ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool 2025-12-05 5:51 ` [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool Nawal Kishor 2025-12-05 5:51 ` [PATCH v2 1/2] common/cnxk: add support for halos Nawal Kishor 2025-12-05 5:51 ` [PATCH v2 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor @ 2026-01-14 6:04 ` Stephen Hemminger 2026-01-14 7:52 ` Morten Brørup 2026-01-19 5:21 ` [EXTERNAL] " Nawal Kishor 2 siblings, 2 replies; 18+ messages in thread From: Stephen Hemminger @ 2026-01-14 6:04 UTC (permalink / raw) To: Nawal Kishor; +Cc: dev, jerinj, asekhar On Fri, 5 Dec 2025 11:21:32 +0530 Nawal Kishor <nkishor@marvell.com> wrote: > This series of patches adds support for HALO in CNXK mempool driver. > > Changes in v2: > * Fixed compilation warnings. > > Nawal Kishor (2): > common/cnxk: add support for halos > mempool/cnxk: add halo support in mempool > > drivers/common/cnxk/hw/npa.h | 81 ++++++ > drivers/common/cnxk/roc_idev.c | 25 ++ > drivers/common/cnxk/roc_idev.h | 3 + > drivers/common/cnxk/roc_idev_priv.h | 1 + > drivers/common/cnxk/roc_mbox.h | 6 + > drivers/common/cnxk/roc_nix.h | 1 + > drivers/common/cnxk/roc_nix_queue.c | 46 ++- > drivers/common/cnxk/roc_npa.c | 268 ++++++++++++++++-- > drivers/common/cnxk/roc_npa.h | 20 +- > drivers/common/cnxk/roc_npa_debug.c | 201 ++++++++++++- > drivers/common/cnxk/roc_npa_priv.h | 3 + > .../common/cnxk/roc_platform_base_symbols.c | 2 + > drivers/common/cnxk/roc_sso.c | 35 ++- > drivers/common/cnxk/roc_sso.h | 1 + > drivers/mempool/cnxk/cn10k_mempool_ops.c | 19 +- > drivers/mempool/cnxk/cn20k_mempool_ops.c | 60 ++++ > drivers/mempool/cnxk/cn9k_mempool_ops.c | 2 +- > drivers/mempool/cnxk/cnxk_mempool.c | 40 ++- > drivers/mempool/cnxk/cnxk_mempool.h | 16 +- > drivers/mempool/cnxk/cnxk_mempool_ops.c | 11 +- > drivers/mempool/cnxk/meson.build | 1 + > 21 files changed, 750 insertions(+), 92 deletions(-) > create mode 100644 drivers/mempool/cnxk/cn20k_mempool_ops.c > This patch never got merged because of CI build failures. Fix and resubmit. AI review also says: ## Patch Review: cnxk halo support (2-patch series) ### Patch 1/2: `common/cnxk: add support for halos` #### Commit Message ✓ | Criterion | Status | Notes | |-----------|--------|-------| | Subject ≤60 chars | ✓ | 33 characters | | Correct prefix | ✓ | `common/cnxk:` is appropriate | | Lowercase after colon | ✓ | | | Imperative mood | ✓ | "add support" | | No trailing period | ✓ | | | Body wrapped ≤75 chars | ✓ | | | Body not starting with "It" | ✓ | Starts with "In cn9k/cn10k..." | | Signed-off-by present | ✓ | Real name and valid email | #### Code Issues **Warning: Implicit pointer comparison (multiple locations)** The AGENTS.md specifies: > `if (!p) /* Bad - don't use ! on pointers */` Several instances use `!ptr` style: ```c // roc_npa.c - npa_halo_alloc() if (!lf || !halo || !aura_handle) return NPA_ERR_PARAM; // roc_npa.c - npa_halo_free() if (!lf || !aura_handle) return NPA_ERR_PARAM; ``` **Suggested fix:** ```c if (lf == NULL || halo == NULL || aura_handle == NULL) return NPA_ERR_PARAM; ``` --- **Warning: Non-portable format specifier** In `roc_npa_debug.c`, function `npa_halo_dump()`: ```c npa_dump("W9: thresh \t\t%lu\nW9: fc_msh_dst \t\t%d", (unsigned long)halo->thresh, halo->fc_msh_dst); ``` The AGENTS.md specifies: > Forbidden: `%lld`, `%llu`, `%llx` → Preferred: `%PRId64`, `%PRIu64`, `%PRIx64` While `%lu` with an explicit cast is technically different, for consistency with the rest of the file (which uses `%"PRIx64"` patterns), this should use: ```c npa_dump("W9: thresh \t\t%" PRIu64 "\nW9: fc_msh_dst \t\t%d", (uint64_t)halo->thresh, halo->fc_msh_dst); ``` --- **Warning: New API functions not marked `__rte_experimental`** New public APIs added to `roc_idev.h`: ```c int __roc_api roc_idev_npa_halo_ena_get(void); void __roc_api roc_idev_npa_halo_ena_set(int halo_ena); ``` And new inline function in `roc_npa.h`: ```c static inline uint32_t roc_npa_max_block_size(void) ``` Per AGENTS.md: > New APIs must be marked as `__rte_experimental` **Note:** These are internal (`__roc_api`) functions in the ROC layer, so `__rte_experimental` may not strictly apply - this depends on whether the ROC API is considered public. However, the pattern in other ROC files should be followed. --- **Info: Good practices observed** - Proper error code additions (`NPA_ERR_HALO_INIT`, `NPA_ERR_HALO_FINI`) - Symbol exports added via `RTE_EXPORT_INTERNAL_SYMBOL` - Hardware structure properly defined with bitfields - Consistent use of `mbox_get()`/`mbox_put()` patterns --- ### Patch 2/2: `mempool/cnxk: add halo support in mempool` #### Commit Message ✓ | Criterion | Status | Notes | |-----------|--------|-------| | Subject ≤60 chars | ✓ | 40 characters | | Correct prefix | ✓ | `mempool/cnxk:` is appropriate | | Lowercase after colon | ✓ | | | Imperative mood | ✓ | "add" | | No trailing period | ✓ | | | Body wrapped ≤75 chars | ✓ | | | Body not starting with "It" | ✓ | Starts with "This patch..." | | Signed-off-by present | ✓ | | #### License ✓ New file `cn20k_mempool_ops.c`: ```c /* SPDX-License-Identifier: BSD-3-Clause * Copyright(C) 2025 Marvell. */ ``` - SPDX on first line ✓ - Copyright follows ✓ - Blank line before includes ✓ - BSD-3-Clause appropriate for driver ✓ #### Code Issues **Warning: Devargs parameter string formatting** In `cnxk_mempool.c`: ```c RTE_PMD_REGISTER_PARAM_STRING(mempool_cnxk, CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>" CNXK_NPA_HALO_ENA_PARAM "=<0-1>"); ``` The two parameter strings will concatenate without a space separator, resulting in: `max_pools=<128-1048576>halo_ena=<0-1>` **Suggested fix:** ```c RTE_PMD_REGISTER_PARAM_STRING(mempool_cnxk, CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576> " CNXK_NPA_HALO_ENA_PARAM "=<0-1>"); ``` --- **Info: meson.build ordering** The file list in `meson.build` is not alphabetically ordered: ```python sources = files( ... 'cn9k_mempool_ops.c', 'cn10k_mempool_ops.c', 'cn20k_mempool_ops.c', 'cn10k_hwpool_ops.c', ) ``` Per AGENTS.md: "Lists alphabetically ordered". However, this follows the existing convention in the file (which was already non-alphabetical), so this is an existing technical debt rather than a new issue introduced by this patch. --- **Info: Documentation consideration** The new `halo_ena` devargs parameter should ideally be documented in the driver documentation (`doc/guides/mempool/cnxk.rst` or similar) so users understand what it does and when to use it. --- ### Summary | Severity | Count | Items | |----------|-------|-------| | **Error** | 0 | None | | **Warning** | 4 | Implicit pointer checks, format specifier, experimental marking, devargs spacing | | **Info** | 2 | meson.build ordering (pre-existing), documentation gap | #### Recommended Actions 1. **Should fix:** Change `!ptr` to `ptr == NULL` for pointer comparisons 2. **Should fix:** Use `PRIu64` format specifier in `npa_halo_dump()` 3. **Should fix:** Add space between devargs parameter strings 4. **Consider:** Add documentation for the new `halo_ena` parameter 5. **Consider:** Verify `__rte_experimental` policy for internal ROC APIs The patches are generally well-structured and follow DPDK conventions. The issues identified are relatively minor style/consistency items rather than functional problems. ^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool 2026-01-14 6:04 ` [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool Stephen Hemminger @ 2026-01-14 7:52 ` Morten Brørup 2026-01-19 5:21 ` [EXTERNAL] " Nawal Kishor 1 sibling, 0 replies; 18+ messages in thread From: Morten Brørup @ 2026-01-14 7:52 UTC (permalink / raw) To: Stephen Hemminger, Nawal Kishor; +Cc: dev, jerinj, asekhar > **Warning: Non-portable format specifier** > > In `roc_npa_debug.c`, function `npa_halo_dump()`: > ```c > npa_dump("W9: thresh \t\t%lu\nW9: fc_msh_dst \t\t%d", > (unsigned long)halo->thresh, halo->fc_msh_dst); > ``` > > The AGENTS.md specifies: > > Forbidden: `%lld`, `%llu`, `%llx` → Preferred: `%PRId64`, `%PRIu64`, > `%PRIx64` > > While `%lu` with an explicit cast is technically different, for > consistency with the rest of the file (which uses `%"PRIx64"` > patterns), this should use: > ```c > npa_dump("W9: thresh \t\t%" PRIu64 "\nW9: fc_msh_dst \t\t%d", > (uint64_t)halo->thresh, halo->fc_msh_dst); > ``` I'm not sure I agree with this, because the AI suggested fix casts halo->thresh to 64 bit on 32 bit architectures (which there is no need for). ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [EXTERNAL] Re: [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool 2026-01-14 6:04 ` [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool Stephen Hemminger 2026-01-14 7:52 ` Morten Brørup @ 2026-01-19 5:21 ` Nawal Kishor 1 sibling, 0 replies; 18+ messages in thread From: Nawal Kishor @ 2026-01-19 5:21 UTC (permalink / raw) To: Stephen Hemminger; +Cc: dev@dpdk.org, Jerin Jacob, Ashwin Sekhar T K Hi Stephen, > This patch never got merged because of CI build failures. > Fix and resubmit. Acknowledged, I will fix and push v3. Thanks Nawal Kishor ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/2] mempool/cnxk: add halo support in mempool 2025-12-04 6:51 [PATCH 0/2] cnxk: Add HALO support for CN20K mempool Nawal Kishor 2025-12-04 6:51 ` [PATCH 1/2] common/cnxk: add support for halos Nawal Kishor @ 2025-12-04 6:51 ` Nawal Kishor 1 sibling, 0 replies; 18+ messages in thread From: Nawal Kishor @ 2025-12-04 6:51 UTC (permalink / raw) To: dev, Ashwin Sekhar T K, Pavan Nikhilesh; +Cc: jerinj, Nawal Kishor This patch adds the support of halos in CN20K mempool driver. It introduces a new devargs parameter "halo_ena" to enable or disable halo feature. If halo_ena is set to 1, halos will be enabled for NPA pools created by the mempool driver. Signed-off-by: Nawal Kishor <nkishor@marvell.com> --- drivers/mempool/cnxk/cn10k_mempool_ops.c | 19 ++++---- drivers/mempool/cnxk/cn20k_mempool_ops.c | 60 ++++++++++++++++++++++++ drivers/mempool/cnxk/cn9k_mempool_ops.c | 2 +- drivers/mempool/cnxk/cnxk_mempool.c | 40 +++++++++++----- drivers/mempool/cnxk/cnxk_mempool.h | 16 ++++++- drivers/mempool/cnxk/cnxk_mempool_ops.c | 11 +++-- drivers/mempool/cnxk/meson.build | 1 + 7 files changed, 120 insertions(+), 29 deletions(-) create mode 100644 drivers/mempool/cnxk/cn20k_mempool_ops.c diff --git a/drivers/mempool/cnxk/cn10k_mempool_ops.c b/drivers/mempool/cnxk/cn10k_mempool_ops.c index a5be0ccafe..09f900a850 100644 --- a/drivers/mempool/cnxk/cn10k_mempool_ops.c +++ b/drivers/mempool/cnxk/cn10k_mempool_ops.c @@ -2,9 +2,6 @@ * Copyright(C) 2021 Marvell. */ -#include <rte_mempool.h> - -#include "roc_api.h" #include "cnxk_mempool.h" #define BATCH_ALLOC_SZ ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS @@ -79,7 +76,7 @@ batch_op_data_set(uint64_t pool_id, struct batch_op_data *op_data) batch_op_data_tbl[aura] = op_data; } -static int +int batch_op_init(struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -109,7 +106,7 @@ batch_op_init(struct rte_mempool *mp) return 0; } -static void +void batch_op_fini(struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -149,7 +146,7 @@ batch_op_fini(struct rte_mempool *mp) rte_wmb(); } -static int __rte_hot +int __rte_hot cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, unsigned int n) { @@ -181,7 +178,7 @@ cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, return 0; } -static unsigned int +unsigned int cn10k_mempool_get_count(const struct rte_mempool *mp) { struct batch_op_data *op_data; @@ -326,7 +323,7 @@ mempool_deq_batch_sync(struct rte_mempool *mp, void **obj_table, unsigned int n) return count; } -static int __rte_hot +int __rte_hot cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n) { struct batch_op_data *op_data; @@ -353,7 +350,7 @@ cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n) return 0; } -static int +int cn10k_mempool_alloc(struct rte_mempool *mp) { uint32_t block_size; @@ -376,7 +373,7 @@ cn10k_mempool_alloc(struct rte_mempool *mp) block_size += padding; } - rc = cnxk_mempool_alloc(mp); + rc = cnxk_mempool_alloc(mp, 0); if (rc) return rc; @@ -392,7 +389,7 @@ cn10k_mempool_alloc(struct rte_mempool *mp) return rc; } -static void +void cn10k_mempool_free(struct rte_mempool *mp) { batch_op_fini(mp); diff --git a/drivers/mempool/cnxk/cn20k_mempool_ops.c b/drivers/mempool/cnxk/cn20k_mempool_ops.c new file mode 100644 index 0000000000..f8817d8743 --- /dev/null +++ b/drivers/mempool/cnxk/cn20k_mempool_ops.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2025 Marvell. + */ + +#include "cnxk_mempool.h" + +static int +cn20k_mempool_alloc(struct rte_mempool *mp) +{ + uint32_t block_size; + int halo_ena, rc; + size_t padding; + + block_size = mp->elt_size + mp->header_size + mp->trailer_size; + /* Align header size to ROC_ALIGN */ + if (mp->header_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(mp->header_size, ROC_ALIGN) - + mp->header_size; + mp->header_size += padding; + block_size += padding; + } + + /* Align block size to ROC_ALIGN */ + if (block_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(block_size, ROC_ALIGN) - block_size; + mp->trailer_size += padding; + block_size += padding; + } + + /* Get halo status */ + halo_ena = roc_idev_npa_halo_ena_get(); + + rc = cnxk_mempool_alloc(mp, halo_ena ? ROC_NPA_HALO_F : 0); + if (rc) + return rc; + + rc = batch_op_init(mp); + if (rc) { + plt_err("Failed to init batch alloc mem rc=%d", rc); + goto error; + } + + return 0; +error: + cnxk_mempool_free(mp); + return rc; +} + +static struct rte_mempool_ops cn20k_mempool_ops = { + .name = "cn20k_mempool_ops", + .alloc = cn20k_mempool_alloc, + .free = cn10k_mempool_free, + .enqueue = cn10k_mempool_enq, + .dequeue = cn10k_mempool_deq, + .get_count = cn10k_mempool_get_count, + .calc_mem_size = cnxk_mempool_calc_mem_size, + .populate = cnxk_mempool_populate, +}; + +RTE_MEMPOOL_REGISTER_OPS(cn20k_mempool_ops); diff --git a/drivers/mempool/cnxk/cn9k_mempool_ops.c b/drivers/mempool/cnxk/cn9k_mempool_ops.c index b7967f8085..8248071cb7 100644 --- a/drivers/mempool/cnxk/cn9k_mempool_ops.c +++ b/drivers/mempool/cnxk/cn9k_mempool_ops.c @@ -72,7 +72,7 @@ cn9k_mempool_alloc(struct rte_mempool *mp) padding = ((block_size / ROC_ALIGN) % 2) ? 0 : ROC_ALIGN; mp->trailer_size += padding; - return cnxk_mempool_alloc(mp); + return cnxk_mempool_alloc(mp, 0); } static struct rte_mempool_ops cn9k_mempool_ops = { diff --git a/drivers/mempool/cnxk/cnxk_mempool.c b/drivers/mempool/cnxk/cnxk_mempool.c index 6ff11d8004..6939fccff4 100644 --- a/drivers/mempool/cnxk/cnxk_mempool.c +++ b/drivers/mempool/cnxk/cnxk_mempool.c @@ -18,6 +18,7 @@ #define CNXK_NPA_DEV_NAME RTE_STR(cnxk_npa_dev_) #define CNXK_NPA_DEV_NAME_LEN (sizeof(CNXK_NPA_DEV_NAME) + PCI_PRI_STR_SIZE) #define CNXK_NPA_MAX_POOLS_PARAM "max_pools" +#define CNXK_NPA_HALO_ENA_PARAM "halo_ena" static inline uint32_t npa_aura_size_to_u32(uint8_t val) @@ -46,30 +47,46 @@ parse_max_pools_handler(const char *key, const char *value, void *extra_args) return 0; } -static inline uint32_t -parse_max_pools(struct rte_devargs *devargs) +static int +parse_halo_ena_handler(const char *key, const char *value, void *extra_args) +{ + RTE_SET_USED(key); + uint8_t val; + + val = atoi(value); + if (val != 0 && val != 1) + return -EINVAL; + + *(uint8_t *)extra_args = val; + return 0; +} + +static int +cnxk_mempool_plt_parse_devargs(struct rte_pci_device *pci_dev) { uint32_t max_pools = npa_aura_size_to_u32(NPA_AURA_SZ_128); + struct rte_devargs *devargs = pci_dev->device.devargs; struct rte_kvargs *kvlist; + uint32_t halo_ena = 0; if (devargs == NULL) - goto exit; + goto null_devargs; kvlist = rte_kvargs_parse(devargs->args, NULL); if (kvlist == NULL) goto exit; rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM, &parse_max_pools_handler, &max_pools); + rte_kvargs_process(kvlist, CNXK_NPA_HALO_ENA_PARAM, + &parse_halo_ena_handler, &halo_ena); rte_kvargs_free(kvlist); -exit: - return max_pools; -} -static int -cnxk_mempool_plt_parse_devargs(struct rte_pci_device *pci_dev) -{ - roc_idev_npa_maxpools_set(parse_max_pools(pci_dev->device.devargs)); +null_devargs: + roc_idev_npa_maxpools_set(max_pools); + roc_idev_npa_halo_ena_set(halo_ena); return 0; +exit: + return -EINVAL; } static inline char * @@ -201,7 +218,8 @@ RTE_PMD_REGISTER_PCI(mempool_cnxk, npa_pci); RTE_PMD_REGISTER_PCI_TABLE(mempool_cnxk, npa_pci_map); RTE_PMD_REGISTER_KMOD_DEP(mempool_cnxk, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(mempool_cnxk, - CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>"); + CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>" + CNXK_NPA_HALO_ENA_PARAM "=<0-1>"); RTE_INIT(cnxk_mempool_parse_devargs) { diff --git a/drivers/mempool/cnxk/cnxk_mempool.h b/drivers/mempool/cnxk/cnxk_mempool.h index 669e617952..941290061e 100644 --- a/drivers/mempool/cnxk/cnxk_mempool.h +++ b/drivers/mempool/cnxk/cnxk_mempool.h @@ -7,6 +7,8 @@ #include <rte_mempool.h> +#include "roc_api.h" + enum cnxk_mempool_flags { /* This flag is used to ensure that only aura zero is allocated. * If aura zero is not available, then mempool creation fails. @@ -47,7 +49,7 @@ int cnxk_mempool_populate(struct rte_mempool *mp, unsigned int max_objs, void *vaddr, rte_iova_t iova, size_t len, rte_mempool_populate_obj_cb_t *obj_cb, void *obj_cb_arg); -int cnxk_mempool_alloc(struct rte_mempool *mp); +int cnxk_mempool_alloc(struct rte_mempool *mp, uint64_t roc_flags); void cnxk_mempool_free(struct rte_mempool *mp); int __rte_hot cnxk_mempool_enq(struct rte_mempool *mp, void *const *obj_table, @@ -55,6 +57,16 @@ int __rte_hot cnxk_mempool_enq(struct rte_mempool *mp, void *const *obj_table, int __rte_hot cnxk_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n); +int batch_op_init(struct rte_mempool *mp); +void batch_op_fini(struct rte_mempool *mp); +int __rte_hot cn10k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, + unsigned int n); +unsigned int cn10k_mempool_get_count(const struct rte_mempool *mp); +int __rte_hot cn10k_mempool_deq(struct rte_mempool *mp, void **obj_table, + unsigned int n); +int cn10k_mempool_alloc(struct rte_mempool *mp); +void cn10k_mempool_free(struct rte_mempool *mp); + int cn10k_mempool_plt_init(void); -#endif +#endif /* _CNXK_MEMPOOL_H_ */ diff --git a/drivers/mempool/cnxk/cnxk_mempool_ops.c b/drivers/mempool/cnxk/cnxk_mempool_ops.c index 5c7fcea487..01b6247fbb 100644 --- a/drivers/mempool/cnxk/cnxk_mempool_ops.c +++ b/drivers/mempool/cnxk/cnxk_mempool_ops.c @@ -70,9 +70,9 @@ cnxk_mempool_calc_mem_size(const struct rte_mempool *mp, uint32_t obj_num, } int -cnxk_mempool_alloc(struct rte_mempool *mp) +cnxk_mempool_alloc(struct rte_mempool *mp, uint64_t roc_flags) { - uint32_t block_count, flags, roc_flags = 0; + uint32_t block_count, flags; uint64_t aura_handle = 0; struct npa_aura_s aura; struct npa_pool_s pool; @@ -98,7 +98,7 @@ cnxk_mempool_alloc(struct rte_mempool *mp) flags = CNXK_MEMPOOL_FLAGS(mp); if (flags & CNXK_MEMPOOL_F_ZERO_AURA) { - roc_flags = ROC_NPA_ZERO_AURA_F; + roc_flags |= ROC_NPA_ZERO_AURA_F; } else if (flags & CNXK_MEMPOOL_F_CUSTOM_AURA) { struct npa_aura_s *paura; @@ -192,9 +192,12 @@ cnxk_mempool_plt_init(void) if (roc_model_is_cn9k()) { rte_mbuf_set_platform_mempool_ops("cn9k_mempool_ops"); - } else if (roc_model_is_cn10k() || roc_model_is_cn20k()) { + } else if (roc_model_is_cn10k()) { rte_mbuf_set_platform_mempool_ops("cn10k_mempool_ops"); rc = cn10k_mempool_plt_init(); + } else if (roc_model_is_cn20k()) { + rte_mbuf_set_platform_mempool_ops("cn20k_mempool_ops"); + rc = cn10k_mempool_plt_init(); } return rc; } diff --git a/drivers/mempool/cnxk/meson.build b/drivers/mempool/cnxk/meson.build index e388cce26a..7722264320 100644 --- a/drivers/mempool/cnxk/meson.build +++ b/drivers/mempool/cnxk/meson.build @@ -14,6 +14,7 @@ sources = files( 'cnxk_mempool_telemetry.c', 'cn9k_mempool_ops.c', 'cn10k_mempool_ops.c', + 'cn20k_mempool_ops.c', 'cn10k_hwpool_ops.c', ) -- 2.48.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
end of thread, other threads:[~2026-02-19 17:52 UTC | newest] Thread overview: 18+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-12-04 6:51 [PATCH 0/2] cnxk: Add HALO support for CN20K mempool Nawal Kishor 2025-12-04 6:51 ` [PATCH 1/2] common/cnxk: add support for halos Nawal Kishor 2025-12-05 5:51 ` [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool Nawal Kishor 2025-12-05 5:51 ` [PATCH v2 1/2] common/cnxk: add support for halos Nawal Kishor 2025-12-05 5:51 ` [PATCH v2 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor 2026-02-17 5:34 ` [PATCH v3 0/2] Add HALO support for CN20K mempool Nawal Kishor 2026-02-17 5:34 ` [PATCH v3 1/2] common/cnxk: add support for halos Nawal Kishor 2026-02-17 5:34 ` [PATCH v3 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor 2026-02-17 8:43 ` [PATCH v3 0/2] Add HALO support for CN20K mempool Jerin Jacob 2026-02-17 10:39 ` [PATCH v4 " Nawal Kishor 2026-02-17 10:39 ` [PATCH v4 1/2] common/cnxk: add support for halos Nawal Kishor 2026-02-19 17:19 ` Stephen Hemminger 2026-02-17 10:39 ` [PATCH v4 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor 2026-02-19 17:33 ` Stephen Hemminger 2026-01-14 6:04 ` [PATCH v2 0/2] cnxk: add HALO support for CN20K mempool Stephen Hemminger 2026-01-14 7:52 ` Morten Brørup 2026-01-19 5:21 ` [EXTERNAL] " Nawal Kishor 2025-12-04 6:51 ` [PATCH 2/2] mempool/cnxk: add halo support in mempool Nawal Kishor
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