* Re: [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support
@ 2026-01-22 4:41 kernel test robot
0 siblings, 0 replies; 6+ messages in thread
From: kernel test robot @ 2026-01-22 4:41 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "low confidence static check warning: drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c:202:1: sparse: sparse: bad integer constant expression"
::::::
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20260121-a733-rtc-v1-7-d359437f23a7@pigmoral.tech>
References: <20260121-a733-rtc-v1-7-d359437f23a7@pigmoral.tech>
TO: Junhui Liu <junhui.liu@pigmoral.tech>
TO: Michael Turquette <mturquette@baylibre.com>
TO: Stephen Boyd <sboyd@kernel.org>
TO: "Chen-Yu Tsai" <wens@kernel.org>
TO: Jernej Skrabec <jernej.skrabec@gmail.com>
TO: Samuel Holland <samuel@sholland.org>
TO: Alexandre Belloni <alexandre.belloni@bootlin.com>
TO: Rob Herring <robh@kernel.org>
TO: Krzysztof Kozlowski <krzk@kernel.org>
TO: Conor Dooley <conor+dt@kernel.org>
TO: Maxime Ripard <mripard@kernel.org>
CC: linux-clk@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-sunxi@lists.linux.dev
CC: linux-kernel@vger.kernel.org
CC: linux-rtc@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: Junhui Liu <junhui.liu@pigmoral.tech>
Hi Junhui,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 24d479d26b25bce5faea3ddd9fa8f3a6c3129ea7]
url: https://github.com/intel-lab-lkp/linux/commits/Junhui-Liu/dt-bindings-rtc-sun6i-Add-Allwinner-A733-support/20260121-192151
base: 24d479d26b25bce5faea3ddd9fa8f3a6c3129ea7
patch link: https://lore.kernel.org/r/20260121-a733-rtc-v1-7-d359437f23a7%40pigmoral.tech
patch subject: [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support
:::::: branch date: 17 hours ago
:::::: commit date: 17 hours ago
config: riscv-randconfig-r133-20260122 (https://download.01.org/0day-ci/archive/20260122/202601221232.7AERi6Wa-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 9b8addffa70cee5b2acc5454712d9cf78ce45710)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260122/202601221232.7AERi6Wa-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202601221232.7AERi6Wa-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
WARNING: invalid argument to '-march': '_zacas_zabha'
>> drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c:202:1: sparse: sparse: bad integer constant expression
drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c:202:1: sparse: sparse: static assertion failed: "MODULE_INFO(import_ns, ...) contains embedded NUL byte"
drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c:203:1: sparse: sparse: bad integer constant expression
drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c:203:1: sparse: sparse: static assertion failed: "MODULE_INFO(description, ...) contains embedded NUL byte"
drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c:204:1: sparse: sparse: bad integer constant expression
drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c:204:1: sparse: sparse: static assertion failed: "MODULE_INFO(file, ...) contains embedded NUL byte"
drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c:204:1: sparse: sparse: bad integer constant expression
drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c:204:1: sparse: sparse: static assertion failed: "MODULE_INFO(license, ...) contains embedded NUL byte"
vim +202 drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c
4d3467b15a1dcec Junhui Liu 2026-01-21 201
4d3467b15a1dcec Junhui Liu 2026-01-21 @202 MODULE_IMPORT_NS("SUNXI_CCU");
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 0/7] rtc: sun6i: Add support for Allwinner A733 SoC
@ 2026-01-21 10:59 Junhui Liu
2026-01-21 10:59 ` [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support Junhui Liu
0 siblings, 1 reply; 6+ messages in thread
From: Junhui Liu @ 2026-01-21 10:59 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Alexandre Belloni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Maxime Ripard
Cc: linux-clk, linux-arm-kernel, linux-sunxi, linux-kernel, linux-rtc,
devicetree, Junhui Liu
Add support for the Allwinner A733 RTC and its internal Clock Control
Unit (CCU). Reuse the rtc-sun6i rtc driver while introducing a new
SoC-specific RTC CCU driver to handle the hardware's evolved clock
structure.
To facilitate this addition and improve driver modularity, transition
the binding between the RTC and its internal CCU from direct
cross-subsystem function calls to the auxiliary bus. Also extract shared
IOSC and 32kHz clock logic into a standalone ccu_rtc module for reuse
across newer SoC generations.
The A733 implementation supports hardware detection of three external
crystal frequencies (19.2MHz, 24MHz and 26MHz), which is represented in
the driver via read-only mux operations. Implement logic to derive a
normalized 32kHz reference from these DCXO sources using fixed
pre-dividers. Additionally, provide several new DCXO gate clocks for
peripherals, including SerDes, HDMI, and UFS.
---
Junhui Liu (7):
dt-bindings: rtc: sun6i: Add Allwinner A733 support
rtc: sun6i: Bind internal CCU via auxiliary bus
clk: sunxi-ng: sun6i-rtc: Add feature bit for IOSC calibration
clk: sunxi-ng: Extract common RTC CCU clock logic
clk: sunxi-ng: mux: Add mux read-only clock operations
rtc: sun6i: Add support for A733 RTC
clk: sunxi-ng: Add Allwinner A733 RTC CCU support
.../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 38 +++-
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 5 +
drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c | 204 +++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h | 18 ++
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 184 +++----------------
drivers/clk/sunxi-ng/ccu_common.h | 1 +
drivers/clk/sunxi-ng/ccu_mux.c | 11 ++
drivers/clk/sunxi-ng/ccu_mux.h | 1 +
drivers/clk/sunxi-ng/ccu_rtc.c | 136 ++++++++++++++
drivers/clk/sunxi-ng/ccu_rtc.h | 44 +++++
drivers/rtc/rtc-sun6i.c | 38 +++-
include/dt-bindings/clock/sun60i-a733-rtc.h | 16 ++
include/linux/clk/sunxi-ng.h | 2 -
14 files changed, 533 insertions(+), 170 deletions(-)
---
base-commit: 24d479d26b25bce5faea3ddd9fa8f3a6c3129ea7
change-id: 20251226-a733-rtc-c5167df14e6e
Best regards,
--
Junhui Liu <junhui.liu@pigmoral.tech>
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support 2026-01-21 10:59 [PATCH 0/7] rtc: sun6i: Add support for Allwinner A733 SoC Junhui Liu @ 2026-01-21 10:59 ` Junhui Liu 2026-03-28 14:41 ` Chen-Yu Tsai 0 siblings, 1 reply; 6+ messages in thread From: Junhui Liu @ 2026-01-21 10:59 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Ripard Cc: linux-clk, linux-arm-kernel, linux-sunxi, linux-kernel, linux-rtc, devicetree, Junhui Liu Add support for the internal CCU found in the RTC module of the Allwinner A733 SoC. While the basic 16MHz (IOSC) and 32kHz logic remains compatible with older SoCs like the sun6i, the A733 introduces several new features. The A733 RTC CCU supports choosing one of three external crystal frequencies: 19.2MHz, 24MHz, and 26MHz. It features hardware detection logic to automatically identify the frequency used on the board and exports this DCXO signal as the "hosc" clock. Furthermore, the driver implements logic to derive a 32kHz reference from the HOSC. This is achieved through a muxed clock path using fixed pre-dividers to normalize the different crystal frequencies to ~32kHz. This path reuses the same hardware mux registers as the HOSC clock. Additionally, this CCU provides several gate clocks for specific peripherals, including SerDes, HDMI, and UFS. The driver is implemented as an auxiliary driver to be bound to the sun6i-rtc driver. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c | 204 +++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h | 18 +++ drivers/clk/sunxi-ng/ccu_rtc.h | 7 + 5 files changed, 236 insertions(+) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 6af2d020e03e..16afbf249f26 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST +config SUN60I_A733_RTC_CCU + tristate "Support for the Allwinner A733 RTC CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN4I_A10_CCU tristate "Support for the Allwinner A10/A20 CCU" default ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index c3f810a025a8..b0d823440c33 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o obj-$(CONFIG_SUN55I_A523_MCU_CCU) += sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o +obj-$(CONFIG_SUN60I_A733_RTC_CCU) += sun60i-a733-rtc-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o @@ -67,6 +68,7 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o sun55i-a523-ccu-y += ccu-sun55i-a523.o sun55i-a523-mcu-ccu-y += ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o +sun60i-a733-rtc-ccu-y += ccu-sun60i-a733-rtc.o sun4i-a10-ccu-y += ccu-sun4i-a10.o sun5i-ccu-y += ccu-sun5i.o sun6i-a31-ccu-y += ccu-sun6i-a31.o diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c new file mode 100644 index 000000000000..d17aceffa16e --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech> + */ + +#include <linux/array_size.h> +#include <linux/auxiliary_bus.h> +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/module.h> + +#include "ccu_common.h" + +#include "ccu_gate.h" +#include "ccu_mux.h" +#include "ccu_rtc.h" + +#include "ccu-sun60i-a733-rtc.h" + +static struct ccu_common iosc_clk = { + .reg = DCXO_CTRL_REG, + .features = CCU_FEATURE_IOSC_CALIBRATION, + .hw.init = CLK_HW_INIT_NO_PARENT("iosc", &ccu_iosc_ops, + CLK_GET_RATE_NOCACHE), +}; + +static struct ccu_common iosc_32k_clk = { + .features = CCU_FEATURE_IOSC_CALIBRATION, + .hw.init = CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw, + &ccu_iosc_32k_ops, + CLK_GET_RATE_NOCACHE), +}; + +static SUNXI_CCU_GATE_FW(ext_osc32k_gate_clk, "ext-osc32k-gate", + "ext-osc32k", 0x0, BIT(4), 0); + +static const struct clk_hw *osc32k_parents[] = { + &iosc_32k_clk.hw, + &ext_osc32k_gate_clk.common.hw, +}; + +static struct ccu_mux osc32k_clk = { + .mux = _SUNXI_CCU_MUX(0, 1), + .common = { + .reg = LOSC_CTRL_REG, + .features = CCU_FEATURE_KEY_FIELD, + .hw.init = CLK_HW_INIT_PARENTS_HW("osc32k", + osc32k_parents, + &ccu_mux_ops, + 0), + }, +}; + +static const struct clk_parent_data hosc_parents[] = { + { .fw_name = "osc24M" }, + { .fw_name = "osc19M" }, + { .fw_name = "osc26M" }, + { .fw_name = "osc24M" }, +}; + +struct ccu_mux hosc_clk = { + .enable = DCXO_CTRL_DCXO_EN, + .mux = _SUNXI_CCU_MUX(14, 2), + .common = { + .reg = DCXO_CTRL_REG, + .hw.init = CLK_HW_INIT_PARENTS_DATA("hosc", + hosc_parents, + &ccu_mux_ro_ops, + 0), + }, +}; + +static const struct ccu_mux_fixed_prediv hosc_32k_predivs[] = { + { .index = 0, .div = 732 }, + { .index = 1, .div = 586 }, + { .index = 2, .div = 793 }, + { .index = 3, .div = 732 }, +}; + +static struct ccu_mux hosc_32k_mux_clk = { + .enable = DCXO_CTRL_DCXO_EN, + .mux = { + .shift = 14, + .width = 2, + .fixed_predivs = hosc_32k_predivs, + .n_predivs = ARRAY_SIZE(hosc_32k_predivs), + }, + .common = { + .reg = DCXO_CTRL_REG, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS_DATA("hosc-32k-mux", + hosc_parents, + &ccu_mux_ro_ops, + 0), + }, +}; + +static SUNXI_CCU_GATE_HW(hosc_32k_clk, "hosc-32k", &hosc_32k_mux_clk.common.hw, + LOSC_OUT_GATING_REG, BIT(16), 0); + +static const struct clk_hw *rtc_32k_parents[] = { + &osc32k_clk.common.hw, + &hosc_32k_clk.common.hw, +}; + +static struct ccu_mux rtc_32k_clk = { + .mux = _SUNXI_CCU_MUX(1, 1), + .common = { + .reg = LOSC_CTRL_REG, + .features = CCU_FEATURE_KEY_FIELD, + .hw.init = CLK_HW_INIT_PARENTS_HW("rtc-32k", + rtc_32k_parents, + &ccu_mux_ops, + 0), + }, +}; + +static const struct clk_parent_data osc32k_fanout_parents[] = { + { .hw = &osc32k_clk.common.hw }, + { .hw = &ext_osc32k_gate_clk.common.hw }, + { .hw = &hosc_32k_clk.common.hw }, +}; + +static SUNXI_CCU_MUX_DATA_WITH_GATE(osc32k_fanout_clk, "osc32k-fanout", osc32k_fanout_parents, + LOSC_OUT_GATING_REG, + 1, 2, /* mux */ + BIT(0), /* gate */ + 0); + +static SUNXI_CCU_GATE_HW(hosc_serdes1_clk, "hosc-serdes1", &hosc_clk.common.hw, + DCXO_GATING_REG, DCXO_SERDES1_GATING, 0); +static SUNXI_CCU_GATE_HW(hosc_serdes0_clk, "hosc-serdes0", &hosc_clk.common.hw, + DCXO_GATING_REG, DCXO_SERDES0_GATING, 0); +static SUNXI_CCU_GATE_HW(hosc_hdmi_clk, "hosc-hdmi", &hosc_clk.common.hw, + DCXO_GATING_REG, DCXO_HDMI_GATING, 0); +static SUNXI_CCU_GATE_HW(hosc_ufs_clk, "hosc-ufs", &hosc_clk.common.hw, + DCXO_GATING_REG, DCXO_UFS_GATING, 0); + +static struct ccu_common *sun60i_rtc_ccu_clks[] = { + &iosc_clk, + &iosc_32k_clk, + &ext_osc32k_gate_clk.common, + &osc32k_clk.common, + &hosc_clk.common, + &hosc_32k_mux_clk.common, + &hosc_32k_clk.common, + &rtc_32k_clk.common, + &osc32k_fanout_clk.common, + &hosc_serdes1_clk.common, + &hosc_serdes0_clk.common, + &hosc_hdmi_clk.common, + &hosc_ufs_clk.common, +}; + +static struct clk_hw_onecell_data sun60i_rtc_ccu_hw_clks = { + .num = CLK_NUMBER, + .hws = { + [CLK_IOSC] = &iosc_clk.hw, + [CLK_OSC32K] = &osc32k_clk.common.hw, + [CLK_HOSC] = &hosc_clk.common.hw, + [CLK_RTC_32K] = &rtc_32k_clk.common.hw, + [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw, + [CLK_HOSC_SERDES1] = &hosc_serdes1_clk.common.hw, + [CLK_HOSC_SERDES0] = &hosc_serdes0_clk.common.hw, + [CLK_HOSC_HDMI] = &hosc_hdmi_clk.common.hw, + [CLK_HOSC_UFS] = &hosc_ufs_clk.common.hw, + [CLK_IOSC_32K] = &iosc_32k_clk.hw, + [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw, + [CLK_HOSC_32K_MUX] = &hosc_32k_mux_clk.common.hw, + [CLK_HOSC_32K] = &hosc_32k_clk.common.hw, + }, +}; + +static const struct sunxi_ccu_desc sun60i_rtc_ccu_desc = { + .ccu_clks = sun60i_rtc_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun60i_rtc_ccu_clks), + + .hw_clks = &sun60i_rtc_ccu_hw_clks, +}; + +static int sun60i_rtc_ccu_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev = &adev->dev; + void __iomem *reg = dev->platform_data; + + return devm_sunxi_ccu_probe(dev, reg, &sun60i_rtc_ccu_desc); +} + +static const struct auxiliary_device_id sun60i_ccu_rtc_ids[] = { + { .name = SUN6I_RTC_AUX_ID(sun60i) }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, sun60i_ccu_rtc_ids); + +static struct auxiliary_driver sun60i_ccu_rtc_driver = { + .probe = sun60i_rtc_ccu_probe, + .id_table = sun60i_ccu_rtc_ids, +}; +module_auxiliary_driver(sun60i_ccu_rtc_driver); + +MODULE_IMPORT_NS("SUNXI_CCU"); +MODULE_DESCRIPTION("Support for the Allwinner A733 RTC CCU"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h new file mode 100644 index 000000000000..41ec6195b5e7 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech> + */ + +#ifndef _CCU_SUN60I_A733_RTC_H_ +#define _CCU_SUN60I_A733_RTC_H_ + +#include <dt-bindings/clock/sun60i-a733-rtc.h> + +#define CLK_IOSC_32K 9 +#define CLK_EXT_OSC32K_GATE 10 +#define CLK_HOSC_32K_MUX 11 +#define CLK_HOSC_32K 12 + +#define CLK_NUMBER (CLK_HOSC_32K + 1) + +#endif /* _CCU_SUN60I_A733_RTC_H_ */ diff --git a/drivers/clk/sunxi-ng/ccu_rtc.h b/drivers/clk/sunxi-ng/ccu_rtc.h index 1c44c2206a25..665162723796 100644 --- a/drivers/clk/sunxi-ng/ccu_rtc.h +++ b/drivers/clk/sunxi-ng/ccu_rtc.h @@ -27,8 +27,15 @@ #define LOSC_OUT_GATING_REG 0x60 #define DCXO_CTRL_REG 0x160 +#define DCXO_CTRL_DCXO_EN BIT(1) #define DCXO_CTRL_CLK16M_RC_EN BIT(0) +#define DCXO_GATING_REG 0x16c +#define DCXO_SERDES1_GATING BIT(5) +#define DCXO_SERDES0_GATING BIT(4) +#define DCXO_HDMI_GATING BIT(1) +#define DCXO_UFS_GATING BIT(0) + #define SUN6I_RTC_AUX_ID(_name) "rtc_sun6i." #_name extern const struct clk_ops ccu_iosc_ops; -- 2.52.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support 2026-01-21 10:59 ` [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support Junhui Liu @ 2026-03-28 14:41 ` Chen-Yu Tsai 2026-04-10 9:49 ` Junhui Liu 2026-06-15 17:56 ` Jerome Brunet 0 siblings, 2 replies; 6+ messages in thread From: Chen-Yu Tsai @ 2026-03-28 14:41 UTC (permalink / raw) To: Junhui Liu Cc: Michael Turquette, Stephen Boyd, Jernej Skrabec, Samuel Holland, Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Ripard, linux-clk, linux-arm-kernel, linux-sunxi, linux-kernel, linux-rtc, devicetree, André Przywara On Wed, Jan 21, 2026 at 7:04 PM Junhui Liu <junhui.liu@pigmoral.tech> wrote: > > Add support for the internal CCU found in the RTC module of the Allwinner > A733 SoC. While the basic 16MHz (IOSC) and 32kHz logic remains compatible > with older SoCs like the sun6i, the A733 introduces several new features. > > The A733 RTC CCU supports choosing one of three external crystal > frequencies: 19.2MHz, 24MHz, and 26MHz. It features hardware detection > logic to automatically identify the frequency used on the board and > exports this DCXO signal as the "hosc" clock. > > Furthermore, the driver implements logic to derive a 32kHz reference > from the HOSC. This is achieved through a muxed clock path using fixed > pre-dividers to normalize the different crystal frequencies to ~32kHz. Have you tested whether the actually normalizes the frequency, i.e. selects a different divider based on the DCXO frequency? Otherwise we're just lying about the frequency. > This path reuses the same hardware mux registers as the HOSC clock. > > Additionally, this CCU provides several gate clocks for specific > peripherals, including SerDes, HDMI, and UFS. The driver is implemented > as an auxiliary driver to be bound to the sun6i-rtc driver. > > Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> > --- > drivers/clk/sunxi-ng/Kconfig | 5 + > drivers/clk/sunxi-ng/Makefile | 2 + > drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c | 204 +++++++++++++++++++++++++++++ > drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h | 18 +++ > drivers/clk/sunxi-ng/ccu_rtc.h | 7 + > 5 files changed, 236 insertions(+) > > diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig > index 6af2d020e03e..16afbf249f26 100644 > --- a/drivers/clk/sunxi-ng/Kconfig > +++ b/drivers/clk/sunxi-ng/Kconfig > @@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU > default ARCH_SUNXI > depends on ARM64 || COMPILE_TEST > > +config SUN60I_A733_RTC_CCU > + tristate "Support for the Allwinner A733 RTC CCU" > + default ARCH_SUNXI > + depends on ARM64 || COMPILE_TEST > + > config SUN4I_A10_CCU > tristate "Support for the Allwinner A10/A20 CCU" > default ARCH_SUNXI > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > index c3f810a025a8..b0d823440c33 100644 > --- a/drivers/clk/sunxi-ng/Makefile > +++ b/drivers/clk/sunxi-ng/Makefile > @@ -39,6 +39,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o > obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o > obj-$(CONFIG_SUN55I_A523_MCU_CCU) += sun55i-a523-mcu-ccu.o > obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o > +obj-$(CONFIG_SUN60I_A733_RTC_CCU) += sun60i-a733-rtc-ccu.o > obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o > obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o > obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o > @@ -67,6 +68,7 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o > sun55i-a523-ccu-y += ccu-sun55i-a523.o > sun55i-a523-mcu-ccu-y += ccu-sun55i-a523-mcu.o > sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o > +sun60i-a733-rtc-ccu-y += ccu-sun60i-a733-rtc.o > sun4i-a10-ccu-y += ccu-sun4i-a10.o > sun5i-ccu-y += ccu-sun5i.o > sun6i-a31-ccu-y += ccu-sun6i-a31.o > diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c > new file mode 100644 > index 000000000000..d17aceffa16e > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c > @@ -0,0 +1,204 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech> > + */ > + > +#include <linux/array_size.h> > +#include <linux/auxiliary_bus.h> > +#include <linux/clk-provider.h> > +#include <linux/device.h> > +#include <linux/module.h> > + > +#include "ccu_common.h" > + > +#include "ccu_gate.h" > +#include "ccu_mux.h" > +#include "ccu_rtc.h" > + > +#include "ccu-sun60i-a733-rtc.h" > + > +static struct ccu_common iosc_clk = { > + .reg = DCXO_CTRL_REG, > + .features = CCU_FEATURE_IOSC_CALIBRATION, > + .hw.init = CLK_HW_INIT_NO_PARENT("iosc", &ccu_iosc_ops, > + CLK_GET_RATE_NOCACHE), > +}; > + > +static struct ccu_common iosc_32k_clk = { > + .features = CCU_FEATURE_IOSC_CALIBRATION, > + .hw.init = CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw, > + &ccu_iosc_32k_ops, > + CLK_GET_RATE_NOCACHE), > +}; > + > +static SUNXI_CCU_GATE_FW(ext_osc32k_gate_clk, "ext-osc32k-gate", > + "ext-osc32k", 0x0, BIT(4), 0); > + > +static const struct clk_hw *osc32k_parents[] = { > + &iosc_32k_clk.hw, > + &ext_osc32k_gate_clk.common.hw, > +}; > + > +static struct ccu_mux osc32k_clk = { > + .mux = _SUNXI_CCU_MUX(0, 1), > + .common = { > + .reg = LOSC_CTRL_REG, > + .features = CCU_FEATURE_KEY_FIELD, > + .hw.init = CLK_HW_INIT_PARENTS_HW("osc32k", > + osc32k_parents, > + &ccu_mux_ops, > + 0), > + }, > +}; > + > +static const struct clk_parent_data hosc_parents[] = { > + { .fw_name = "osc24M" }, > + { .fw_name = "osc19M" }, > + { .fw_name = "osc26M" }, > + { .fw_name = "osc24M" }, > +}; As mentioned in my reply to the binding, this is wrong. There is only one input. The most you can do is check the rate of the parent clock against the detected one, and _scream_ that the DT is wrong. And maybe override the reported frequency. If you want to do the latter, you could add a new fixed rate gated clock type to our library. You would fill in the rate before the clocks get registered. I probably wouldn't go that far. We want people to have correct hardware descriptions. Funnily enough Allwinner's BSP actually implements a fixed rate gate for the next 24M-to-32k divider clock. > + > +struct ccu_mux hosc_clk = { > + .enable = DCXO_CTRL_DCXO_EN, > + .mux = _SUNXI_CCU_MUX(14, 2), > + .common = { > + .reg = DCXO_CTRL_REG, > + .hw.init = CLK_HW_INIT_PARENTS_DATA("hosc", > + hosc_parents, > + &ccu_mux_ro_ops, > + 0), > + }, > +}; So this is wrong. > + > +static const struct ccu_mux_fixed_prediv hosc_32k_predivs[] = { > + { .index = 0, .div = 732 }, Why is it 732 instead of 750? > + { .index = 1, .div = 586 }, > + { .index = 2, .div = 793 }, > + { .index = 3, .div = 732 }, > +}; > + > +static struct ccu_mux hosc_32k_mux_clk = { > + .enable = DCXO_CTRL_DCXO_EN, No. The parent "hosc" clock owns this. The enable bit for this clock is actually bit 16 of LOSC_OUT_GATING_REG, which you model below as a separate gate. > + .mux = { > + .shift = 14, > + .width = 2, > + .fixed_predivs = hosc_32k_predivs, > + .n_predivs = ARRAY_SIZE(hosc_32k_predivs), > + }, > + .common = { > + .reg = DCXO_CTRL_REG, > + .features = CCU_FEATURE_FIXED_PREDIV, > + .hw.init = CLK_HW_INIT_PARENTS_DATA("hosc-32k-mux", > + hosc_parents, > + &ccu_mux_ro_ops, Again, this is just not the way to do it. > + 0), > + }, > +}; I would test that it actually does switch dividers, Or at the very least, it has a larger divider for 26M. Maybe Andre can help? At least on this SoC the fanout pins are much more accessible. > + > +static SUNXI_CCU_GATE_HW(hosc_32k_clk, "hosc-32k", &hosc_32k_mux_clk.common.hw, > + LOSC_OUT_GATING_REG, BIT(16), 0); > + > +static const struct clk_hw *rtc_32k_parents[] = { > + &osc32k_clk.common.hw, > + &hosc_32k_clk.common.hw, > +}; > + > +static struct ccu_mux rtc_32k_clk = { > + .mux = _SUNXI_CCU_MUX(1, 1), > + .common = { > + .reg = LOSC_CTRL_REG, > + .features = CCU_FEATURE_KEY_FIELD, > + .hw.init = CLK_HW_INIT_PARENTS_HW("rtc-32k", > + rtc_32k_parents, > + &ccu_mux_ops, > + 0), > + }, > +}; > + > +static const struct clk_parent_data osc32k_fanout_parents[] = { > + { .hw = &osc32k_clk.common.hw }, > + { .hw = &ext_osc32k_gate_clk.common.hw }, > + { .hw = &hosc_32k_clk.common.hw }, > +}; > + > +static SUNXI_CCU_MUX_DATA_WITH_GATE(osc32k_fanout_clk, "osc32k-fanout", osc32k_fanout_parents, > + LOSC_OUT_GATING_REG, > + 1, 2, /* mux */ > + BIT(0), /* gate */ > + 0); > + > +static SUNXI_CCU_GATE_HW(hosc_serdes1_clk, "hosc-serdes1", &hosc_clk.common.hw, > + DCXO_GATING_REG, DCXO_SERDES1_GATING, 0); ^ Just use the BIT() expression here. Adding these macros doesn't really help. > +static SUNXI_CCU_GATE_HW(hosc_serdes0_clk, "hosc-serdes0", &hosc_clk.common.hw, > + DCXO_GATING_REG, DCXO_SERDES0_GATING, 0); > +static SUNXI_CCU_GATE_HW(hosc_hdmi_clk, "hosc-hdmi", &hosc_clk.common.hw, > + DCXO_GATING_REG, DCXO_HDMI_GATING, 0); > +static SUNXI_CCU_GATE_HW(hosc_ufs_clk, "hosc-ufs", &hosc_clk.common.hw, > + DCXO_GATING_REG, DCXO_UFS_GATING, 0); > + > +static struct ccu_common *sun60i_rtc_ccu_clks[] = { > + &iosc_clk, > + &iosc_32k_clk, > + &ext_osc32k_gate_clk.common, > + &osc32k_clk.common, > + &hosc_clk.common, > + &hosc_32k_mux_clk.common, > + &hosc_32k_clk.common, > + &rtc_32k_clk.common, > + &osc32k_fanout_clk.common, > + &hosc_serdes1_clk.common, > + &hosc_serdes0_clk.common, > + &hosc_hdmi_clk.common, > + &hosc_ufs_clk.common, > +}; > + > +static struct clk_hw_onecell_data sun60i_rtc_ccu_hw_clks = { > + .num = CLK_NUMBER, > + .hws = { > + [CLK_IOSC] = &iosc_clk.hw, > + [CLK_OSC32K] = &osc32k_clk.common.hw, > + [CLK_HOSC] = &hosc_clk.common.hw, > + [CLK_RTC_32K] = &rtc_32k_clk.common.hw, > + [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw, > + [CLK_HOSC_SERDES1] = &hosc_serdes1_clk.common.hw, > + [CLK_HOSC_SERDES0] = &hosc_serdes0_clk.common.hw, > + [CLK_HOSC_HDMI] = &hosc_hdmi_clk.common.hw, > + [CLK_HOSC_UFS] = &hosc_ufs_clk.common.hw, > + [CLK_IOSC_32K] = &iosc_32k_clk.hw, > + [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw, > + [CLK_HOSC_32K_MUX] = &hosc_32k_mux_clk.common.hw, > + [CLK_HOSC_32K] = &hosc_32k_clk.common.hw, > + }, > +}; > + > +static const struct sunxi_ccu_desc sun60i_rtc_ccu_desc = { > + .ccu_clks = sun60i_rtc_ccu_clks, > + .num_ccu_clks = ARRAY_SIZE(sun60i_rtc_ccu_clks), > + > + .hw_clks = &sun60i_rtc_ccu_hw_clks, > +}; > + > +static int sun60i_rtc_ccu_probe(struct auxiliary_device *adev, > + const struct auxiliary_device_id *id) > +{ > + struct device *dev = &adev->dev; > + void __iomem *reg = dev->platform_data; > + > + return devm_sunxi_ccu_probe(dev, reg, &sun60i_rtc_ccu_desc); > +} > + > +static const struct auxiliary_device_id sun60i_ccu_rtc_ids[] = { > + { .name = SUN6I_RTC_AUX_ID(sun60i) }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(auxiliary, sun60i_ccu_rtc_ids); > + > +static struct auxiliary_driver sun60i_ccu_rtc_driver = { > + .probe = sun60i_rtc_ccu_probe, > + .id_table = sun60i_ccu_rtc_ids, > +}; > +module_auxiliary_driver(sun60i_ccu_rtc_driver); > + > +MODULE_IMPORT_NS("SUNXI_CCU"); > +MODULE_DESCRIPTION("Support for the Allwinner A733 RTC CCU"); > +MODULE_LICENSE("GPL"); > diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h > new file mode 100644 > index 000000000000..41ec6195b5e7 > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h > @@ -0,0 +1,18 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech> > + */ > + > +#ifndef _CCU_SUN60I_A733_RTC_H_ > +#define _CCU_SUN60I_A733_RTC_H_ > + > +#include <dt-bindings/clock/sun60i-a733-rtc.h> > + > +#define CLK_IOSC_32K 9 > +#define CLK_EXT_OSC32K_GATE 10 > +#define CLK_HOSC_32K_MUX 11 > +#define CLK_HOSC_32K 12 > + > +#define CLK_NUMBER (CLK_HOSC_32K + 1) > + > +#endif /* _CCU_SUN60I_A733_RTC_H_ */ > diff --git a/drivers/clk/sunxi-ng/ccu_rtc.h b/drivers/clk/sunxi-ng/ccu_rtc.h > index 1c44c2206a25..665162723796 100644 > --- a/drivers/clk/sunxi-ng/ccu_rtc.h > +++ b/drivers/clk/sunxi-ng/ccu_rtc.h > @@ -27,8 +27,15 @@ > #define LOSC_OUT_GATING_REG 0x60 > > #define DCXO_CTRL_REG 0x160 > +#define DCXO_CTRL_DCXO_EN BIT(1) > #define DCXO_CTRL_CLK16M_RC_EN BIT(0) > > +#define DCXO_GATING_REG 0x16c > +#define DCXO_SERDES1_GATING BIT(5) > +#define DCXO_SERDES0_GATING BIT(4) > +#define DCXO_HDMI_GATING BIT(1) > +#define DCXO_UFS_GATING BIT(0) Adding them to the header is probably even less useful, as the output could change in future chips. ChenYu ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support 2026-03-28 14:41 ` Chen-Yu Tsai @ 2026-04-10 9:49 ` Junhui Liu 2026-06-15 17:56 ` Jerome Brunet 1 sibling, 0 replies; 6+ messages in thread From: Junhui Liu @ 2026-04-10 9:49 UTC (permalink / raw) To: wens, Junhui Liu Cc: Michael Turquette, Stephen Boyd, Jernej Skrabec, Samuel Holland, Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Ripard, linux-clk, linux-arm-kernel, linux-sunxi, linux-kernel, linux-rtc, devicetree, André Przywara On Sat Mar 28, 2026 at 10:41 PM CST, Chen-Yu Tsai wrote: > On Wed, Jan 21, 2026 at 7:04 PM Junhui Liu <junhui.liu@pigmoral.tech> wrote: >> >> Add support for the internal CCU found in the RTC module of the Allwinner >> A733 SoC. While the basic 16MHz (IOSC) and 32kHz logic remains compatible >> with older SoCs like the sun6i, the A733 introduces several new features. >> >> The A733 RTC CCU supports choosing one of three external crystal >> frequencies: 19.2MHz, 24MHz, and 26MHz. It features hardware detection >> logic to automatically identify the frequency used on the board and >> exports this DCXO signal as the "hosc" clock. >> >> Furthermore, the driver implements logic to derive a 32kHz reference >> from the HOSC. This is achieved through a muxed clock path using fixed >> pre-dividers to normalize the different crystal frequencies to ~32kHz. > > Have you tested whether the actually normalizes the frequency, i.e. > selects a different divider based on the DCXO frequency? Otherwise > we're just lying about the frequency. I only have A733 boards with 26MHz crystals, so I couldn't test all crystal configurations. However, I exported the "hosc_32k" clock (referred to as dcxo24M_div32k_clk in the vendor driver) to a physical pin via the fanout path and measured it with the oscilloscope. Observations: - Normal conditions: The frequency remains stable within the 32.744 kHz to 32.791 kHz range. - Forced condition: I grounded the R24 resistor on radxa A7A board to trick the SoC into detecting a 24MHz crystal while the actual input remained 26MHz. In this case, the frequency became unstable but still stayed around the 32.2 kHz to 33.3 kHz range. Based on these results, it appears the hardware does attempt to normalize the frequency towards 32.768 kHz via some internal logic. > >> This path reuses the same hardware mux registers as the HOSC clock. >> >> Additionally, this CCU provides several gate clocks for specific >> peripherals, including SerDes, HDMI, and UFS. The driver is implemented >> as an auxiliary driver to be bound to the sun6i-rtc driver. >> >> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> >> --- >> drivers/clk/sunxi-ng/Kconfig | 5 + >> drivers/clk/sunxi-ng/Makefile | 2 + >> drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c | 204 +++++++++++++++++++++++++++++ >> drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h | 18 +++ >> drivers/clk/sunxi-ng/ccu_rtc.h | 7 + >> 5 files changed, 236 insertions(+) >> [...] >> + >> +static const struct clk_parent_data hosc_parents[] = { >> + { .fw_name = "osc24M" }, >> + { .fw_name = "osc19M" }, >> + { .fw_name = "osc26M" }, >> + { .fw_name = "osc24M" }, >> +}; > > As mentioned in my reply to the binding, this is wrong. There is only > one input. > > The most you can do is check the rate of the parent clock against the > detected one, and _scream_ that the DT is wrong. And maybe override > the reported frequency. I will add a warning message if the frequency detected by the driver does not match the one in the DT. > > If you want to do the latter, you could add a new fixed rate gated > clock type to our library. You would fill in the rate before the > clocks get registered. I probably wouldn't go that far. We want people > to have correct hardware descriptions. > > Funnily enough Allwinner's BSP actually implements a fixed rate gate > for the next 24M-to-32k divider clock. Yes, I noticed that as well. I agree, and I will model this path as a simple fixed-rate clock (32768Hz) in v2. > >> + >> +struct ccu_mux hosc_clk = { >> + .enable = DCXO_CTRL_DCXO_EN, >> + .mux = _SUNXI_CCU_MUX(14, 2), >> + .common = { >> + .reg = DCXO_CTRL_REG, >> + .hw.init = CLK_HW_INIT_PARENTS_DATA("hosc", >> + hosc_parents, >> + &ccu_mux_ro_ops, >> + 0), >> + }, >> +}; > > So this is wrong. > >> + >> +static const struct ccu_mux_fixed_prediv hosc_32k_predivs[] = { >> + { .index = 0, .div = 732 }, > > Why is it 732 instead of 750? As mentioned above, the target frequency is 32.768kHz rather than 32.0kHz. However, since I will drop this prediv array and use a fixed-rate clock instead, I think this will no longer be an issue. -- Best regards, Junhui Liu ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support 2026-03-28 14:41 ` Chen-Yu Tsai 2026-04-10 9:49 ` Junhui Liu @ 2026-06-15 17:56 ` Jerome Brunet 2026-06-23 15:23 ` Chen-Yu Tsai 1 sibling, 1 reply; 6+ messages in thread From: Jerome Brunet @ 2026-06-15 17:56 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Junhui Liu, Michael Turquette, Stephen Boyd, Jernej Skrabec, Samuel Holland, Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Ripard, linux-clk, linux-arm-kernel, linux-sunxi, linux-kernel, linux-rtc, devicetree, André Przywara On sam. 28 mars 2026 at 22:41, Chen-Yu Tsai <wens@kernel.org> wrote: > On Wed, Jan 21, 2026 at 7:04 PM Junhui Liu <junhui.liu@pigmoral.tech> wrote: >> >> Add support for the internal CCU found in the RTC module of the Allwinner >> A733 SoC. While the basic 16MHz (IOSC) and 32kHz logic remains compatible >> with older SoCs like the sun6i, the A733 introduces several new features. >> >> The A733 RTC CCU supports choosing one of three external crystal >> frequencies: 19.2MHz, 24MHz, and 26MHz. It features hardware detection >> logic to automatically identify the frequency used on the board and >> exports this DCXO signal as the "hosc" clock. >> >> Furthermore, the driver implements logic to derive a 32kHz reference >> from the HOSC. This is achieved through a muxed clock path using fixed >> pre-dividers to normalize the different crystal frequencies to ~32kHz. > > Have you tested whether the actually normalizes the frequency, i.e. > selects a different divider based on the DCXO frequency? Otherwise > we're just lying about the frequency. > >> This path reuses the same hardware mux registers as the HOSC clock. >> >> Additionally, this CCU provides several gate clocks for specific >> peripherals, including SerDes, HDMI, and UFS. The driver is implemented >> as an auxiliary driver to be bound to the sun6i-rtc driver. >> >> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> >> --- [...] >> +}; >> + >> +static const struct clk_parent_data hosc_parents[] = { >> + { .fw_name = "osc24M" }, >> + { .fw_name = "osc19M" }, >> + { .fw_name = "osc26M" }, >> + { .fw_name = "osc24M" }, >> +}; > > As mentioned in my reply to the binding, this is wrong. There is only > one input. > > The most you can do is check the rate of the parent clock against the > detected one, and _scream_ that the DT is wrong. And maybe override > the reported frequency. > > If you want to do the latter, you could add a new fixed rate gated > clock type to our library. You would fill in the rate before the > clocks get registered. I probably wouldn't go that far. We want people > to have correct hardware descriptions. > > Funnily enough Allwinner's BSP actually implements a fixed rate gate > for the next 24M-to-32k divider clock. What about implementing the register bellow as a read-only (and non-cached) divider using the factors provided by Junhui ? That would be an accurate description of the HW I think. The oscillator gets set in DT and if the output reported past the divider is not 32728Hz, you know you've got a problem (bad DT or HW gone bad) With a fixed-rate gate, you may actually end up lying about what actually happen, if the HW does not behave as expected. Do you prefer a fixed-rate gate still or should I try the RO divider approach ? > >> + >> +struct ccu_mux hosc_clk = { >> + .enable = DCXO_CTRL_DCXO_EN, >> + .mux = _SUNXI_CCU_MUX(14, 2), >> + .common = { >> + .reg = DCXO_CTRL_REG, >> + .hw.init = CLK_HW_INIT_PARENTS_DATA("hosc", >> + hosc_parents, >> + &ccu_mux_ro_ops, >> + 0), >> + }, >> +}; > > So this is wrong. > >> + >> +static const struct ccu_mux_fixed_prediv hosc_32k_predivs[] = { >> + { .index = 0, .div = 732 }, > > Why is it 732 instead of 750? > >> + { .index = 1, .div = 586 }, >> + { .index = 2, .div = 793 }, >> + { .index = 3, .div = 732 }, >> +}; >> + >> +static struct ccu_mux hosc_32k_mux_clk = { >> + .enable = DCXO_CTRL_DCXO_EN, > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support 2026-06-15 17:56 ` Jerome Brunet @ 2026-06-23 15:23 ` Chen-Yu Tsai 0 siblings, 0 replies; 6+ messages in thread From: Chen-Yu Tsai @ 2026-06-23 15:23 UTC (permalink / raw) To: Jerome Brunet Cc: Junhui Liu, Michael Turquette, Stephen Boyd, Jernej Skrabec, Samuel Holland, Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Ripard, linux-clk, linux-arm-kernel, linux-sunxi, linux-kernel, linux-rtc, devicetree, André Przywara On Tue, Jun 16, 2026 at 1:56 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > On sam. 28 mars 2026 at 22:41, Chen-Yu Tsai <wens@kernel.org> wrote: > > > On Wed, Jan 21, 2026 at 7:04 PM Junhui Liu <junhui.liu@pigmoral.tech> wrote: > >> > >> Add support for the internal CCU found in the RTC module of the Allwinner > >> A733 SoC. While the basic 16MHz (IOSC) and 32kHz logic remains compatible > >> with older SoCs like the sun6i, the A733 introduces several new features. > >> > >> The A733 RTC CCU supports choosing one of three external crystal > >> frequencies: 19.2MHz, 24MHz, and 26MHz. It features hardware detection > >> logic to automatically identify the frequency used on the board and > >> exports this DCXO signal as the "hosc" clock. > >> > >> Furthermore, the driver implements logic to derive a 32kHz reference > >> from the HOSC. This is achieved through a muxed clock path using fixed > >> pre-dividers to normalize the different crystal frequencies to ~32kHz. > > > > Have you tested whether the actually normalizes the frequency, i.e. > > selects a different divider based on the DCXO frequency? Otherwise > > we're just lying about the frequency. > > > >> This path reuses the same hardware mux registers as the HOSC clock. > >> > >> Additionally, this CCU provides several gate clocks for specific > >> peripherals, including SerDes, HDMI, and UFS. The driver is implemented > >> as an auxiliary driver to be bound to the sun6i-rtc driver. > >> > >> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> > >> --- > > [...] > > >> +}; > >> + > >> +static const struct clk_parent_data hosc_parents[] = { > >> + { .fw_name = "osc24M" }, > >> + { .fw_name = "osc19M" }, > >> + { .fw_name = "osc26M" }, > >> + { .fw_name = "osc24M" }, > >> +}; > > > > As mentioned in my reply to the binding, this is wrong. There is only > > one input. > > > > The most you can do is check the rate of the parent clock against the > > detected one, and _scream_ that the DT is wrong. And maybe override > > the reported frequency. > > > > If you want to do the latter, you could add a new fixed rate gated > > clock type to our library. You would fill in the rate before the > > clocks get registered. I probably wouldn't go that far. We want people > > to have correct hardware descriptions. > > > > Funnily enough Allwinner's BSP actually implements a fixed rate gate > > for the next 24M-to-32k divider clock. > > What about implementing the register bellow as a read-only (and > non-cached) divider using the factors provided by Junhui ? That would be > an accurate description of the HW I think. > > The oscillator gets set in DT and if the output reported past the > divider is not 32728Hz, you know you've got a problem (bad DT or HW gone > bad) > > With a fixed-rate gate, you may actually end up lying about what > actually happen, if the HW does not behave as expected. > > Do you prefer a fixed-rate gate still or should I try the RO divider > approach ? I think either one would work. The RO divider is probably more accurate. Sorry for the late reply. ChenYu ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-06-23 15:23 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-01-22 4:41 [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support kernel test robot -- strict thread matches above, loose matches on Subject: below -- 2026-01-21 10:59 [PATCH 0/7] rtc: sun6i: Add support for Allwinner A733 SoC Junhui Liu 2026-01-21 10:59 ` [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support Junhui Liu 2026-03-28 14:41 ` Chen-Yu Tsai 2026-04-10 9:49 ` Junhui Liu 2026-06-15 17:56 ` Jerome Brunet 2026-06-23 15:23 ` Chen-Yu Tsai
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.