* [PATCH v2 1/3] ppc/pnv: Support for SECURITY_SWITCH XSCOM register access
2026-01-26 13:55 [PATCH v2 0/3] Power10 PowerVM bringup fixes Caleb Schlossin
@ 2026-01-26 13:55 ` Caleb Schlossin
2026-01-26 13:55 ` [PATCH v2 2/3] ppc/pnv: Add unimplemented quad and core regs Caleb Schlossin
2026-01-26 13:55 ` [PATCH v2 3/3] ppc/pnv: Add OCC FLAG registers Caleb Schlossin
2 siblings, 0 replies; 8+ messages in thread
From: Caleb Schlossin @ 2026-01-26 13:55 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, npiggin, adityag, milesg, chalapathi.v, harshpb, calebs
Power Hypervisor code requires access to the SECURITY_SWITCH
XSCOM register at MMIO address 0x80028 (scom address 0x10005).
Adding basic read support for now so that is doesn't cause
error messages to be posted.
Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Aditya Gupta <adityag@linux.ibm.com>
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
hw/ppc/pnv_xscom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index 8557b560ae..dc1ffc6c01 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -61,6 +61,8 @@ static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
{
switch (pcba) {
+ case 0x10005: /* SECURITY SWITCH */
+ return 0;
case 0xf000f:
return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
case 0x18002: /* ECID2 */
--
2.47.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 2/3] ppc/pnv: Add unimplemented quad and core regs
2026-01-26 13:55 [PATCH v2 0/3] Power10 PowerVM bringup fixes Caleb Schlossin
2026-01-26 13:55 ` [PATCH v2 1/3] ppc/pnv: Support for SECURITY_SWITCH XSCOM register access Caleb Schlossin
@ 2026-01-26 13:55 ` Caleb Schlossin
2026-02-10 7:04 ` Aditya Gupta
2026-01-26 13:55 ` [PATCH v2 3/3] ppc/pnv: Add OCC FLAG registers Caleb Schlossin
2 siblings, 1 reply; 8+ messages in thread
From: Caleb Schlossin @ 2026-01-26 13:55 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, npiggin, adityag, milesg, chalapathi.v, harshpb, calebs
This commit adds the read/write functionality for few core and
quad registers.
Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Aditya Gupta <adityag@linux.ibm.com>
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
hw/ppc/pnv_core.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 8939515c2c..56675f5506 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -185,10 +185,18 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
* POWER10 core controls
*/
+#define PNV10_XSCOM_EC_IMA_EVENT_MASK 0x400
#define PNV10_XSCOM_EC_CORE_THREAD_STATE 0x412
#define PNV10_XSCOM_EC_CORE_THREAD_INFO 0x413
+#define PNV10_XSCOM_EC_CORE_FIRMASK 0x443
+#define PNV10_XSCOM_EC_CORE_FIRMASK_AND 0x444
+#define PNV10_XSCOM_EC_CORE_FIRMASK_OR 0x445
#define PNV10_XSCOM_EC_CORE_DIRECT_CONTROLS 0x449
#define PNV10_XSCOM_EC_CORE_RAS_STATUS 0x454
+#define PNV10_XSCOM_EC_SPATTN_OR 0x497
+#define PNV10_XSCOM_EC_SPATTN_AND 0x498
+#define PNV10_XSCOM_EC_SPATTN 0x499
+#define PNV10_XSCOM_EC_SPATTN_MASK 0x49A
static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
unsigned int width)
@@ -224,6 +232,19 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
}
}
break;
+ case PNV10_XSCOM_EC_IMA_EVENT_MASK:
+ case PNV10_XSCOM_EC_CORE_FIRMASK:
+ return 0;
+ case PNV10_XSCOM_EC_CORE_FIRMASK_OR:
+ case PNV10_XSCOM_EC_CORE_FIRMASK_AND:
+ case PNV10_XSCOM_EC_SPATTN_OR:
+ case PNV10_XSCOM_EC_SPATTN_AND:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
+ "xscom read at 0x%08x\n", __func__, offset);
+ break;
+ case PNV10_XSCOM_EC_SPATTN:
+ case PNV10_XSCOM_EC_SPATTN_MASK:
+ return 0;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
offset);
@@ -284,6 +305,15 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
}
break;
+ case PNV10_XSCOM_EC_IMA_EVENT_MASK:
+ case PNV10_XSCOM_EC_CORE_FIRMASK:
+ case PNV10_XSCOM_EC_CORE_FIRMASK_OR:
+ case PNV10_XSCOM_EC_CORE_FIRMASK_AND:
+ case PNV10_XSCOM_EC_SPATTN_OR:
+ case PNV10_XSCOM_EC_SPATTN_AND:
+ case PNV10_XSCOM_EC_SPATTN:
+ case PNV10_XSCOM_EC_SPATTN_MASK:
+ break;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
offset);
@@ -579,6 +609,23 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
* POWER10 Quads
*/
+#define P10_XSCOM_EQ3_MODE_REG1 0x1160a
+#define P10_XSCOM_EQ3_NCU_SPEC_BAR_REG 0x11650
+#define P10_XSCOM_EQ3_HTM_MODE 0x11680
+#define P10_XSCOM_EQ3_HTM_IMA_PDBAR 0x1168b
+#define P10_XSCOM_EQ2_MODE_REG1 0x1260a
+#define P10_XSCOM_EQ2_NCU_SPEC_BAR_REG 0x12650
+#define P10_XSCOM_EQ2_HTM_MODE 0x12680
+#define P10_XSCOM_EQ2_HTM_IMA_PDBAR 0x1268b
+#define P10_XSCOM_EQ1_MODE_REG1 0x1460a
+#define P10_XSCOM_EQ1_NCU_SPEC_BAR_REG 0x14650
+#define P10_XSCOM_EQ1_HTM_MODE 0x14680
+#define P10_XSCOM_EQ1_HTM_IMA_PDBAR 0x1468b
+#define P10_XSCOM_EQ0_MODE_REG1 0x1860a
+#define P10_XSCOM_EQ0_NCU_SPEC_BAR_REG 0x18650
+#define P10_XSCOM_EQ0_HTM_MODE 0x18680
+#define P10_XSCOM_EQ0_HTM_IMA_PDBAR 0x1868b
+
static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
unsigned int width)
{
@@ -586,6 +633,23 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
uint64_t val = -1;
switch (offset) {
+ case P10_XSCOM_EQ0_MODE_REG1:
+ case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:
+ case P10_XSCOM_EQ0_HTM_MODE:
+ case P10_XSCOM_EQ0_HTM_IMA_PDBAR:
+ case P10_XSCOM_EQ1_MODE_REG1:
+ case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:
+ case P10_XSCOM_EQ1_HTM_MODE:
+ case P10_XSCOM_EQ1_HTM_IMA_PDBAR:
+ case P10_XSCOM_EQ2_MODE_REG1:
+ case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:
+ case P10_XSCOM_EQ2_HTM_MODE:
+ case P10_XSCOM_EQ2_HTM_IMA_PDBAR:
+ case P10_XSCOM_EQ3_MODE_REG1:
+ case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:
+ case P10_XSCOM_EQ3_HTM_MODE:
+ case P10_XSCOM_EQ3_HTM_IMA_PDBAR:
+ return 0;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
offset);
@@ -600,6 +664,23 @@ static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,
uint32_t offset = addr >> 3;
switch (offset) {
+ case P10_XSCOM_EQ0_MODE_REG1:
+ case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:
+ case P10_XSCOM_EQ0_HTM_MODE:
+ case P10_XSCOM_EQ0_HTM_IMA_PDBAR:
+ case P10_XSCOM_EQ1_MODE_REG1:
+ case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:
+ case P10_XSCOM_EQ1_HTM_MODE:
+ case P10_XSCOM_EQ1_HTM_IMA_PDBAR:
+ case P10_XSCOM_EQ2_MODE_REG1:
+ case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:
+ case P10_XSCOM_EQ2_HTM_MODE:
+ case P10_XSCOM_EQ2_HTM_IMA_PDBAR:
+ case P10_XSCOM_EQ3_MODE_REG1:
+ case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:
+ case P10_XSCOM_EQ3_HTM_MODE:
+ case P10_XSCOM_EQ3_HTM_IMA_PDBAR:
+ break;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
offset);
--
2.47.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/3] ppc/pnv: Add unimplemented quad and core regs
2026-01-26 13:55 ` [PATCH v2 2/3] ppc/pnv: Add unimplemented quad and core regs Caleb Schlossin
@ 2026-02-10 7:04 ` Aditya Gupta
2026-02-10 13:10 ` Caleb Schlossin
0 siblings, 1 reply; 8+ messages in thread
From: Aditya Gupta @ 2026-02-10 7:04 UTC (permalink / raw)
To: Caleb Schlossin
Cc: qemu-devel, qemu-ppc, npiggin, milesg, chalapathi.v, harshpb
Hello Caleb,
Was going through the patch again. Can we add a comment doc, about the
scoms for which the unimplemented warning is getting hidden ?
On 26/01/26 07:55AM, Caleb Schlossin wrote:
> <...snip...>
>
> @@ -284,6 +305,15 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
> }
> break;
>
> + case PNV10_XSCOM_EC_IMA_EVENT_MASK:
> + case PNV10_XSCOM_EC_CORE_FIRMASK:
> + case PNV10_XSCOM_EC_CORE_FIRMASK_OR:
> + case PNV10_XSCOM_EC_CORE_FIRMASK_AND:
> + case PNV10_XSCOM_EC_SPATTN_OR:
> + case PNV10_XSCOM_EC_SPATTN_AND:
> + case PNV10_XSCOM_EC_SPATTN:
> + case PNV10_XSCOM_EC_SPATTN_MASK:
> + break;
> default:
> qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
Here, the unimp warning is getting skipped, by ignoring writes to those
scoms.
Similarly in other places, you return 0 as default value for few scom
reads.
A comment about the special treatment will help future developers to
read the code.
Thanks,
- Aditya G
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/3] ppc/pnv: Add unimplemented quad and core regs
2026-02-10 7:04 ` Aditya Gupta
@ 2026-02-10 13:10 ` Caleb Schlossin
0 siblings, 0 replies; 8+ messages in thread
From: Caleb Schlossin @ 2026-02-10 13:10 UTC (permalink / raw)
To: Aditya Gupta; +Cc: qemu-devel, qemu-ppc, npiggin, milesg, chalapathi.v, harshpb
On 2/10/26 1:04 AM, Aditya Gupta wrote:
> Hello Caleb,
>
> Was going through the patch again. Can we add a comment doc, about the
> scoms for which the unimplemented warning is getting hidden ?
>
> On 26/01/26 07:55AM, Caleb Schlossin wrote:
>> <...snip...>
>>
>> @@ -284,6 +305,15 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
>> }
>> break;
>>
>> + case PNV10_XSCOM_EC_IMA_EVENT_MASK:
>> + case PNV10_XSCOM_EC_CORE_FIRMASK:
>> + case PNV10_XSCOM_EC_CORE_FIRMASK_OR:
>> + case PNV10_XSCOM_EC_CORE_FIRMASK_AND:
>> + case PNV10_XSCOM_EC_SPATTN_OR:
>> + case PNV10_XSCOM_EC_SPATTN_AND:
>> + case PNV10_XSCOM_EC_SPATTN:
>> + case PNV10_XSCOM_EC_SPATTN_MASK:
>> + break;
>> default:
>> qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
>
> Here, the unimp warning is getting skipped, by ignoring writes to those
> scoms.
> Similarly in other places, you return 0 as default value for few scom
> reads.
>
> A comment about the special treatment will help future developers to
> read the code.
Sure. I'll add that in my next patch set.
Thanks,
Caleb
>
> Thanks,
> - Aditya G
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] ppc/pnv: Add OCC FLAG registers
2026-01-26 13:55 [PATCH v2 0/3] Power10 PowerVM bringup fixes Caleb Schlossin
2026-01-26 13:55 ` [PATCH v2 1/3] ppc/pnv: Support for SECURITY_SWITCH XSCOM register access Caleb Schlossin
2026-01-26 13:55 ` [PATCH v2 2/3] ppc/pnv: Add unimplemented quad and core regs Caleb Schlossin
@ 2026-01-26 13:55 ` Caleb Schlossin
2 siblings, 0 replies; 8+ messages in thread
From: Caleb Schlossin @ 2026-01-26 13:55 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, npiggin, adityag, milesg, chalapathi.v, harshpb, calebs
OCCFLG are scratch registers that can be shared with OCC firmware.
Log reads and writes to the registers as a reminder when we run
into more OCC code.
Add RW, WO_CLEAR and WO_OR SCOM Type enums in pnv_occ.c
Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Aditya Gupta <adityag@linux.ibm.com>
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
hw/ppc/pnv_occ.c | 55 +++++++++++++++++++++++++++++++++++++---
include/hw/ppc/pnv_occ.h | 4 +++
2 files changed, 56 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 64cab3e9dc..81dd5cfd1b 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -195,6 +195,49 @@ static const TypeInfo pnv_occ_power8_type_info = {
#define P9_OCB_OCI_OCCMISC_CLEAR 0x6081
#define P9_OCB_OCI_OCCMISC_OR 0x6082
+/* OCC scratch registers for flag setting */
+#define P9_OCCFLG0 0x60ac
+#define P9_OCCFLG7_OR 0x60c3
+
+enum ScomType {
+ SCOM_TYPE_RW = 0,
+ SCOM_TYPE_WO_CLEAR = 1,
+ SCOM_TYPE_WO_OR = 2,
+};
+
+static void rw_occ_flag_regs(PnvOCC *occ, uint32_t offset, bool read,
+ uint64_t *val)
+{
+ int flag_num;
+ int flag_type;
+
+ /*
+ * Each OCCFLG register has SCOM0 - RW, SCOM1 - WO_CLEAR, SCOM2 - WO_OR
+ * hence divide by 3 to get flag index and mod 3 to get SCOM type.
+ */
+ flag_num = (offset - P9_OCCFLG0) / 3;
+ flag_type = (offset - P9_OCCFLG0) % 3;
+
+ if (read) {
+ if (flag_type) {
+ qemu_log_mask(LOG_GUEST_ERROR, "OCC: Write only register: Ox%"
+ PRIx32 "\n", offset);
+ return;
+ }
+ *val = occ->occflags[flag_num];
+ } else {
+ switch (flag_type) {
+ case SCOM_TYPE_RW:
+ occ->occflags[flag_num] = *val;
+ break;
+ case SCOM_TYPE_WO_CLEAR:
+ occ->occflags[flag_num] &= ~(*val);
+ break;
+ case SCOM_TYPE_WO_OR:
+ occ->occflags[flag_num] |= *val;
+ }
+ }
+}
static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
unsigned size)
@@ -207,8 +250,11 @@ static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
case P9_OCB_OCI_OCCMISC:
val = occ->occmisc;
break;
+ case P9_OCCFLG0 ... P9_OCCFLG7_OR:
+ rw_occ_flag_regs(occ, offset, 1, &val);
+ break;
default:
- qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
+ qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register read: Ox%"
HWADDR_PRIx "\n", addr >> 3);
}
return val;
@@ -229,9 +275,12 @@ static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,
break;
case P9_OCB_OCI_OCCMISC:
pnv_occ_set_misc(occ, val);
- break;
+ break;
+ case P9_OCCFLG0 ... P9_OCCFLG7_OR:
+ rw_occ_flag_regs(occ, offset, 0, &val);
+ break;
default:
- qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
+ qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register write: Ox%"
HWADDR_PRIx "\n", addr >> 3);
}
}
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index 84bdf5004d..92a4dbf1a0 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -47,6 +47,10 @@ struct PnvOCC {
/* OCC Misc interrupt */
uint64_t occmisc;
+ /* OCC Flags */
+#define NR_FLAG_REGS 8
+ uint32_t occflags[NR_FLAG_REGS];
+
qemu_irq psi_irq;
/* OCCs operate on regions of HOMER memory */
--
2.47.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] ppc/pnv: Add OCC FLAG registers
2026-02-10 13:46 [PATCH v2 0/3] Power10 PowerVM bringup fixes Caleb Schlossin
@ 2026-02-10 13:46 ` Caleb Schlossin
2026-03-02 6:12 ` Harsh Prateek Bora
0 siblings, 1 reply; 8+ messages in thread
From: Caleb Schlossin @ 2026-02-10 13:46 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, npiggin, adityag, milesg, chalapathi.v, harshpb, calebs
OCCFLG are scratch registers that can be shared with OCC firmware.
Log reads and writes to the registers as a reminder when we run
into more OCC code.
Add RW, WO_CLEAR and WO_OR SCOM Type enums in pnv_occ.c
Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Aditya Gupta <adityag@linux.ibm.com>
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
hw/ppc/pnv_occ.c | 55 +++++++++++++++++++++++++++++++++++++---
include/hw/ppc/pnv_occ.h | 4 +++
2 files changed, 56 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 64cab3e9dc..b9f69daffc 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -195,6 +195,49 @@ static const TypeInfo pnv_occ_power8_type_info = {
#define P9_OCB_OCI_OCCMISC_CLEAR 0x6081
#define P9_OCB_OCI_OCCMISC_OR 0x6082
+/* OCC scratch registers for flag setting */
+#define P9_OCCFLG0 0x60ac
+#define P9_OCCFLG7_OR 0x60c3
+
+enum ScomType {
+ SCOM_TYPE_RW = 0,
+ SCOM_TYPE_WO_CLEAR = 1,
+ SCOM_TYPE_WO_OR = 2,
+};
+
+static void rw_occ_flag_regs(PnvOCC *occ, uint32_t offset, bool read,
+ uint64_t *val)
+{
+ int flag_num;
+ int flag_type;
+
+ /*
+ * Each OCCFLG register has SCOM0 - RW, SCOM1 - WO_CLEAR, SCOM2 - WO_OR
+ * hence divide by 3 to get flag index and mod 3 to get SCOM type.
+ */
+ flag_num = (offset - P9_OCCFLG0) / 3;
+ flag_type = (offset - P9_OCCFLG0) % 3;
+
+ if (read) {
+ if (flag_type) {
+ qemu_log_mask(LOG_GUEST_ERROR, "OCC: Write only register: Ox%"
+ PRIx32 "\n", offset);
+ return;
+ }
+ *val = occ->occflags[flag_num];
+ } else {
+ switch (flag_type) {
+ case SCOM_TYPE_RW:
+ occ->occflags[flag_num] = *val;
+ break;
+ case SCOM_TYPE_WO_CLEAR:
+ occ->occflags[flag_num] &= ~(*val);
+ break;
+ case SCOM_TYPE_WO_OR:
+ occ->occflags[flag_num] |= *val;
+ }
+ }
+}
static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
unsigned size)
@@ -207,8 +250,11 @@ static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
case P9_OCB_OCI_OCCMISC:
val = occ->occmisc;
break;
+ case P9_OCCFLG0 ... P9_OCCFLG7_OR:
+ rw_occ_flag_regs(occ, offset, 1, &val);
+ break;
default:
- qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
+ qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register read: Ox%"
HWADDR_PRIx "\n", addr >> 3);
}
return val;
@@ -229,9 +275,12 @@ static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,
break;
case P9_OCB_OCI_OCCMISC:
pnv_occ_set_misc(occ, val);
- break;
+ break;
+ case P9_OCCFLG0 ... P9_OCCFLG7_OR:
+ rw_occ_flag_regs(occ, offset, 0, &val);
+ break;
default:
- qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
+ qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register write: Ox%"
HWADDR_PRIx "\n", addr >> 3);
}
}
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index 84bdf5004d..92a4dbf1a0 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -47,6 +47,10 @@ struct PnvOCC {
/* OCC Misc interrupt */
uint64_t occmisc;
+ /* OCC Flags */
+#define NR_FLAG_REGS 8
+ uint32_t occflags[NR_FLAG_REGS];
+
qemu_irq psi_irq;
/* OCCs operate on regions of HOMER memory */
--
2.47.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/3] ppc/pnv: Add OCC FLAG registers
2026-02-10 13:46 ` [PATCH v2 3/3] ppc/pnv: Add OCC FLAG registers Caleb Schlossin
@ 2026-03-02 6:12 ` Harsh Prateek Bora
0 siblings, 0 replies; 8+ messages in thread
From: Harsh Prateek Bora @ 2026-03-02 6:12 UTC (permalink / raw)
To: Caleb Schlossin, qemu-devel
Cc: qemu-ppc, npiggin, adityag, milesg, chalapathi.v
On 10/02/26 7:16 pm, Caleb Schlossin wrote:
> OCCFLG are scratch registers that can be shared with OCC firmware.
> Log reads and writes to the registers as a reminder when we run
> into more OCC code.
>
> Add RW, WO_CLEAR and WO_OR SCOM Type enums in pnv_occ.c
>
> Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com
> Reviewed-by: Glenn Miles<milesg@linux.ibm.com>
> Reviewed-by: Aditya Gupta<adityag@linux.ibm.com>
> Signed-off-by: Chalapathi V<chalapathi.v@linux.ibm.com>
> Signed-off-by: Caleb Schlossin<calebs@linux.ibm.com>
> ---
> hw/ppc/pnv_occ.c | 55 +++++++++++++++++++++++++++++++++++++---
> include/hw/ppc/pnv_occ.h | 4 +++
> 2 files changed, 56 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
> index 64cab3e9dc..b9f69daffc 100644
> --- a/hw/ppc/pnv_occ.c
> +++ b/hw/ppc/pnv_occ.c
> @@ -195,6 +195,49 @@ static const TypeInfo pnv_occ_power8_type_info = {
> #define P9_OCB_OCI_OCCMISC_CLEAR 0x6081
> #define P9_OCB_OCI_OCCMISC_OR 0x6082
>
> +/* OCC scratch registers for flag setting */
> +#define P9_OCCFLG0 0x60ac
> +#define P9_OCCFLG7_OR 0x60c3
> +
> +enum ScomType {
> + SCOM_TYPE_RW = 0,
> + SCOM_TYPE_WO_CLEAR = 1,
> + SCOM_TYPE_WO_OR = 2,
> +};
> +
Would be more suitable to place above macros, enum in pnv_occ.h,
but that's trivial and can be taken care as a separate patch later.
Queued patch 1,3.
^ permalink raw reply [flat|nested] 8+ messages in thread