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From: Jamin Lin via <qemu-arm@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
	<kane_chen@aspeedtech.com>
Subject: [PATCH v1 4/7] hw/arm/aspeed_ast2600: Expand RC_H PCIe MMIO window to 0x60000000 - 0x80000000
Date: Tue, 27 Jan 2026 11:23:40 +0800	[thread overview]
Message-ID: <20260127032348.2238527-5-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20260127032348.2238527-1-jamin_lin@aspeedtech.com>

Historically, the ASPEED PCIe driver supported both RC_L and RC_H, with RC_L
using MMIO window 0x60000000 - 0x70000000 and RC_H using 0x70000000 - 0x80000000.

Mainline Linux has dropped RC_L support and now supports RC_H only, updating
RC_H to use a single combined MMIO window 0x60000000 - 0x80000000.

Update the AST2600 QEMU model accordingly by moving PCIE_MMIO1 base to
0x60000000 and increasing the aliased MMIO size to 0x20000000.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast2600.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 4c5a42ea17..efb1d8c063 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -81,7 +81,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
     [ASPEED_DEV_FSI1]      = 0x1E79B000,
     [ASPEED_DEV_FSI2]      = 0x1E79B100,
     [ASPEED_DEV_I3C]       = 0x1E7A0000,
-    [ASPEED_DEV_PCIE_MMIO1] = 0x70000000,
+    [ASPEED_DEV_PCIE_MMIO1] = 0x60000000,
     [ASPEED_DEV_SDRAM]     = 0x80000000,
 };
 
@@ -303,14 +303,14 @@ static uint64_t aspeed_calc_affinity(int cpu)
  *
  * Model scope / limitations:
  *   - Firmware supports RC_H only; this QEMU model does not support RC_L.
- *   - RC_H uses PHY1 and the MMIO window [0x70000000, 0x80000000]
+ *   - RC_H uses PHY1 and the MMIO window [0x60000000, 0x80000000]
  *     (aka MMIO1).
  *
  * Indexing convention (this model):
  *   - Expose a single logical instance at index 0.
  *   - pcie[0] -> hardware RC_H (PCIe1)
  *   - phy[0]  -> hardware PHY1
- *   - mmio.0 -> guest address range MMIO1: 0x70000000-0x80000000
+ *   - mmio.0 -> guest address range MMIO1: 0x60000000-0x80000000
  *   - RC_L / PCIe0 is not created and mapped.
  */
 static bool aspeed_soc_ast2600_pcie_realize(DeviceState *dev, Error **errp)
@@ -346,7 +346,7 @@ static bool aspeed_soc_ast2600_pcie_realize(DeviceState *dev, Error **errp)
     memory_region_init_alias(&s->pcie_mmio_alias[0], OBJECT(&s->pcie[0].rc),
                              "aspeed.pcie-mmio", mmio_mr,
                              sc->memmap[ASPEED_DEV_PCIE_MMIO1],
-                             0x10000000);
+                             0x20000000);
     memory_region_add_subregion(s->memory,
                                 sc->memmap[ASPEED_DEV_PCIE_MMIO1],
                                 &s->pcie_mmio_alias[0]);
-- 
2.43.0



WARNING: multiple messages have this Message-ID (diff)
From: Jamin Lin via qemu development <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
	<kane_chen@aspeedtech.com>
Subject: [PATCH v1 4/7] hw/arm/aspeed_ast2600: Expand RC_H PCIe MMIO window to 0x60000000 - 0x80000000
Date: Tue, 27 Jan 2026 11:23:40 +0800	[thread overview]
Message-ID: <20260127032348.2238527-5-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20260127032348.2238527-1-jamin_lin@aspeedtech.com>

Historically, the ASPEED PCIe driver supported both RC_L and RC_H, with RC_L
using MMIO window 0x60000000 - 0x70000000 and RC_H using 0x70000000 - 0x80000000.

Mainline Linux has dropped RC_L support and now supports RC_H only, updating
RC_H to use a single combined MMIO window 0x60000000 - 0x80000000.

Update the AST2600 QEMU model accordingly by moving PCIE_MMIO1 base to
0x60000000 and increasing the aliased MMIO size to 0x20000000.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast2600.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 4c5a42ea17..efb1d8c063 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -81,7 +81,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
     [ASPEED_DEV_FSI1]      = 0x1E79B000,
     [ASPEED_DEV_FSI2]      = 0x1E79B100,
     [ASPEED_DEV_I3C]       = 0x1E7A0000,
-    [ASPEED_DEV_PCIE_MMIO1] = 0x70000000,
+    [ASPEED_DEV_PCIE_MMIO1] = 0x60000000,
     [ASPEED_DEV_SDRAM]     = 0x80000000,
 };
 
@@ -303,14 +303,14 @@ static uint64_t aspeed_calc_affinity(int cpu)
  *
  * Model scope / limitations:
  *   - Firmware supports RC_H only; this QEMU model does not support RC_L.
- *   - RC_H uses PHY1 and the MMIO window [0x70000000, 0x80000000]
+ *   - RC_H uses PHY1 and the MMIO window [0x60000000, 0x80000000]
  *     (aka MMIO1).
  *
  * Indexing convention (this model):
  *   - Expose a single logical instance at index 0.
  *   - pcie[0] -> hardware RC_H (PCIe1)
  *   - phy[0]  -> hardware PHY1
- *   - mmio.0 -> guest address range MMIO1: 0x70000000-0x80000000
+ *   - mmio.0 -> guest address range MMIO1: 0x60000000-0x80000000
  *   - RC_L / PCIe0 is not created and mapped.
  */
 static bool aspeed_soc_ast2600_pcie_realize(DeviceState *dev, Error **errp)
@@ -346,7 +346,7 @@ static bool aspeed_soc_ast2600_pcie_realize(DeviceState *dev, Error **errp)
     memory_region_init_alias(&s->pcie_mmio_alias[0], OBJECT(&s->pcie[0].rc),
                              "aspeed.pcie-mmio", mmio_mr,
                              sc->memmap[ASPEED_DEV_PCIE_MMIO1],
-                             0x10000000);
+                             0x20000000);
     memory_region_add_subregion(s->memory,
                                 sc->memmap[ASPEED_DEV_PCIE_MMIO1],
                                 &s->pcie_mmio_alias[0]);
-- 
2.43.0



  parent reply	other threads:[~2026-01-27  3:24 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-27  3:23 [PATCH v1 0/7] Update functional tests for AST2500/AST2600/AST103/AST1060 Jamin Lin via
2026-01-27  3:23 ` Jamin Lin via qemu development
2026-01-27  3:23 ` [PATCH v1 1/7] tests/functional/arm/test_aspeed_ast2500: Update test ASPEED SDK v10.00 Jamin Lin via
2026-01-27  3:23   ` Jamin Lin via qemu development
2026-01-27  3:23 ` [PATCH v1 2/7] hw/pci-host/aspeed_pcie: Drop AST2600 PCIe root device Jamin Lin via
2026-01-27  3:23   ` Jamin Lin via qemu development
2026-01-27  3:23 ` [PATCH v1 3/7] hw/pci-host/aspeed_pcie: Drop AST2600 RC_H root-bus remap and bus-nr property Jamin Lin via
2026-01-27  3:23   ` Jamin Lin via qemu development
2026-01-28 10:43   ` Cédric Le Goater
2026-01-29  2:10     ` Jamin Lin
2026-01-29  7:06       ` Cédric Le Goater
2026-01-27  3:23 ` Jamin Lin via [this message]
2026-01-27  3:23   ` [PATCH v1 4/7] hw/arm/aspeed_ast2600: Expand RC_H PCIe MMIO window to 0x60000000 - 0x80000000 Jamin Lin via qemu development
2026-01-27  3:23 ` [PATCH v1 5/7] tests/functional/arm/test_aspeed_ast2600_sdk: Update test ASPEED SDK v11.00 Jamin Lin via
2026-01-27  3:23   ` Jamin Lin via qemu development
2026-01-27  3:23 ` [PATCH v1 6/7] tests/functional/arm/test_aspeed_ast1060: Update test aspeed-zephyr-project v03.04 Jamin Lin via
2026-01-27  3:23   ` Jamin Lin via qemu development
2026-01-27  3:23 ` [PATCH v1 7/7] tests/functional/arm/test_aspeed_ast1030: Update test ASPEED Zephyr SDK v03.05 Jamin Lin via
2026-01-27  3:23   ` Jamin Lin via qemu development
2026-01-29  7:07 ` [PATCH v1 0/7] Update functional tests for AST2500/AST2600/AST103/AST1060 Cédric Le Goater

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