All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jason Gunthorpe <jgg@nvidia.com>
To: Andrew Jones <andrew.jones@oss.qualcomm.com>
Cc: Alexandre Ghiti <alex@ghiti.fr>,
	Albert Ou <aou@eecs.berkeley.edu>,
	iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
	linux-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <pjw@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Tomasz Jeznach <tjeznach@rivosinc.com>,
	Will Deacon <will@kernel.org>,
	lihangjing@bytedance.com, Xu Lu <luxu.kernel@bytedance.com>,
	patches@lists.linux.dev, xieyongji@bytedance.com
Subject: Re: [PATCH v2 5/5] iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST
Date: Fri, 30 Jan 2026 19:44:34 -0400	[thread overview]
Message-ID: <20260130234434.GK2223369@nvidia.com> (raw)
In-Reply-To: <dn7bsft2qvjod3sm6omneq37pwr2jtdzgobapy6obpgccg7soc@ctvs3c2w4vob>

On Fri, Jan 30, 2026 at 01:58:51PM -0600, Andrew Jones wrote:
> >  config RISCV_IOMMU
> >  	bool "RISC-V IOMMU Support"
> > -	depends on RISCV && 64BIT
> > -	default y
> > +	default RISCV
> > +	depends on (RISCV || COMPILE_TEST) && 64BIT
> > +	depends on GENERIC_MSI_IRQ
> 
> This new depends isn't called out in the commit message. Maybe it should
> even be its own patch with a fixes d5f88acdd6ff ("iommu/riscv: Add support
> for platform msi") tag, but, either way, thanks for the fix.

I think if riscv has a 32 bit configuration with iommu HW available
then you'd want a different fix to make it work.. Probably include one
of the high/low headers to get emulated writeq

This is just intended to make it work with COMPILE_TEST on eg ARM32.

> > @@ -436,7 +436,9 @@ static unsigned int riscv_iommu_queue_send(struct riscv_iommu_queue *queue,
> >  	 * 6. Make sure the doorbell write to the device has finished before updating
> >  	 *    the shadow tail index in normal memory. 'fence o, w'
> >  	 */
> > +#ifdef CONFIG_MMIOWB
> >  	mmiowb();
> > +#endif
> 
> Taking inspiration from powerpc we'd put the #ifdef CONFIG_MMIOWB in
> arch/riscv/include/asm/mmiowb.h

That won't help compile on x86 for example.

Thanks,
Jason

WARNING: multiple messages have this Message-ID (diff)
From: Jason Gunthorpe <jgg@nvidia.com>
To: Andrew Jones <andrew.jones@oss.qualcomm.com>
Cc: Alexandre Ghiti <alex@ghiti.fr>,
	Albert Ou <aou@eecs.berkeley.edu>,
	iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
	linux-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <pjw@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Tomasz Jeznach <tjeznach@rivosinc.com>,
	Will Deacon <will@kernel.org>,
	lihangjing@bytedance.com, Xu Lu <luxu.kernel@bytedance.com>,
	patches@lists.linux.dev, xieyongji@bytedance.com
Subject: Re: [PATCH v2 5/5] iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST
Date: Fri, 30 Jan 2026 19:44:34 -0400	[thread overview]
Message-ID: <20260130234434.GK2223369@nvidia.com> (raw)
In-Reply-To: <dn7bsft2qvjod3sm6omneq37pwr2jtdzgobapy6obpgccg7soc@ctvs3c2w4vob>

On Fri, Jan 30, 2026 at 01:58:51PM -0600, Andrew Jones wrote:
> >  config RISCV_IOMMU
> >  	bool "RISC-V IOMMU Support"
> > -	depends on RISCV && 64BIT
> > -	default y
> > +	default RISCV
> > +	depends on (RISCV || COMPILE_TEST) && 64BIT
> > +	depends on GENERIC_MSI_IRQ
> 
> This new depends isn't called out in the commit message. Maybe it should
> even be its own patch with a fixes d5f88acdd6ff ("iommu/riscv: Add support
> for platform msi") tag, but, either way, thanks for the fix.

I think if riscv has a 32 bit configuration with iommu HW available
then you'd want a different fix to make it work.. Probably include one
of the high/low headers to get emulated writeq

This is just intended to make it work with COMPILE_TEST on eg ARM32.

> > @@ -436,7 +436,9 @@ static unsigned int riscv_iommu_queue_send(struct riscv_iommu_queue *queue,
> >  	 * 6. Make sure the doorbell write to the device has finished before updating
> >  	 *    the shadow tail index in normal memory. 'fence o, w'
> >  	 */
> > +#ifdef CONFIG_MMIOWB
> >  	mmiowb();
> > +#endif
> 
> Taking inspiration from powerpc we'd put the #ifdef CONFIG_MMIOWB in
> arch/riscv/include/asm/mmiowb.h

That won't help compile on x86 for example.

Thanks,
Jason

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-01-30 23:44 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-06 15:06 [PATCH v2 0/5] Convert riscv to use the generic iommu page table Jason Gunthorpe
2026-01-06 15:06 ` Jason Gunthorpe
2026-01-06 15:06 ` [PATCH v2 1/5] iommupt: Add the RISC-V page table format Jason Gunthorpe
2026-01-06 15:06   ` Jason Gunthorpe
2026-01-30 19:21   ` Andrew Jones
2026-01-30 19:21     ` Andrew Jones
2026-01-30 23:47     ` Jason Gunthorpe
2026-01-30 23:47       ` Jason Gunthorpe
2026-01-06 15:06 ` [PATCH v2 2/5] iommu/riscv: Disable SADE Jason Gunthorpe
2026-01-06 15:06   ` Jason Gunthorpe
2026-01-06 15:06 ` [PATCH v2 3/5] iommu/riscv: Use the generic iommu page table Jason Gunthorpe
2026-01-06 15:06   ` Jason Gunthorpe
2026-01-06 15:06 ` [PATCH v2 4/5] iommu/riscv: Enable SVNAPOT support for contiguous ptes Jason Gunthorpe
2026-01-06 15:06   ` Jason Gunthorpe
2026-01-06 15:06 ` [PATCH v2 5/5] iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST Jason Gunthorpe
2026-01-06 15:06   ` Jason Gunthorpe
2026-01-30 19:58   ` Andrew Jones
2026-01-30 19:58     ` Andrew Jones
2026-01-30 23:44     ` Jason Gunthorpe [this message]
2026-01-30 23:44       ` Jason Gunthorpe
2026-02-04 16:09       ` Andrew Jones
2026-02-04 16:09         ` Andrew Jones
2026-01-22  1:46 ` [PATCH v2 0/5] Convert riscv to use the generic iommu page table Vincent Chen
2026-01-22  1:46   ` Vincent Chen
2026-01-22 15:31   ` Jason Gunthorpe
2026-01-22 15:31     ` Jason Gunthorpe
2026-01-23  3:05     ` Vincent Chen
2026-01-23  3:05       ` Vincent Chen
2026-01-23 12:29       ` Vincent Chen
2026-01-23 12:29         ` Vincent Chen
2026-01-23 13:52         ` Jason Gunthorpe
2026-01-23 13:52           ` Jason Gunthorpe
2026-01-29 11:21           ` Robin Murphy
2026-01-29 11:21             ` Robin Murphy
2026-01-31  0:27             ` Jason Gunthorpe
2026-01-31  0:27               ` Jason Gunthorpe
2026-02-02 14:00               ` Robin Murphy
2026-02-02 14:00                 ` Robin Murphy
2026-02-02 14:37                 ` Jason Gunthorpe
2026-02-02 14:37                   ` Jason Gunthorpe
2026-02-02 16:43                   ` Robin Murphy
2026-02-02 16:43                     ` Robin Murphy
2026-01-22  7:56 ` Joerg Roedel
2026-01-22  7:56   ` Joerg Roedel
2026-01-29  0:46   ` Jason Gunthorpe
2026-01-29  0:46     ` Jason Gunthorpe
2026-01-30 23:14     ` Paul Walmsley
2026-01-30 23:14       ` Paul Walmsley
2026-01-31  1:28       ` Tomasz Jeznach
2026-01-31  1:28         ` Tomasz Jeznach

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260130234434.GK2223369@nvidia.com \
    --to=jgg@nvidia.com \
    --cc=alex@ghiti.fr \
    --cc=andrew.jones@oss.qualcomm.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=iommu@lists.linux.dev \
    --cc=joro@8bytes.org \
    --cc=lihangjing@bytedance.com \
    --cc=linux-riscv@lists.infradead.org \
    --cc=luxu.kernel@bytedance.com \
    --cc=palmer@dabbelt.com \
    --cc=patches@lists.linux.dev \
    --cc=pjw@kernel.org \
    --cc=robin.murphy@arm.com \
    --cc=tjeznach@rivosinc.com \
    --cc=will@kernel.org \
    --cc=xieyongji@bytedance.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.