From: Boris Brezillon <boris.brezillon@collabora.com>
To: Alice Ryhl <aliceryhl@google.com>
Cc: "Maxime Ripard" <mripard@kernel.org>,
"Daniel Almeida" <daniel.almeida@collabora.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
"Viresh Kumar" <viresh.kumar@linaro.org>,
"Danilo Krummrich" <dakr@kernel.org>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Drew Fustini" <fustini@kernel.org>,
"Guo Ren" <guoren@kernel.org>, "Fu Wei" <wefu@redhat.com>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Miguel Ojeda" <ojeda@kernel.org>,
"Boqun Feng" <boqun.feng@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Benno Lossin" <lossin@kernel.org>,
"Andreas Hindborg" <a.hindborg@kernel.org>,
"Trevor Gross" <tmgross@umich.edu>,
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org,
linux-pwm@vger.kernel.org, linux-clk@vger.kernel.org,
rust-for-linux@vger.kernel.org
Subject: Re: [PATCH v3 1/3] rust: clk: use the type-state pattern
Date: Tue, 3 Feb 2026 12:26:31 +0100 [thread overview]
Message-ID: <20260203122631.3a94a935@fedora> (raw)
In-Reply-To: <20260203113902.501e5803@fedora>
On Tue, 3 Feb 2026 11:39:02 +0100
Boris Brezillon <boris.brezillon@collabora.com> wrote:
> On Mon, 19 Jan 2026 12:35:21 +0000
> Alice Ryhl <aliceryhl@google.com> wrote:
>
> > On Mon, Jan 19, 2026 at 11:45:57AM +0100, Maxime Ripard wrote:
> > > On Thu, Jan 08, 2026 at 11:14:37AM -0300, Daniel Almeida wrote:
> > > > > For example, it's quite typical to have (at least) one clock for the bus
> > > > > interface that drives the register, and one that drives the main
> > > > > component logic. The former needs to be enabled only when you're
> > > > > accessing the registers (and can be abstracted with
> > > > > regmap_mmio_attach_clk for example), and the latter needs to be enabled
> > > > > only when the device actually starts operating.
> > > > >
> > > > > You have a similar thing for the prepare vs enable thing. The difference
> > > > > between the two is that enable can be called into atomic context but
> > > > > prepare can't.
> > > > >
> > > > > So for drivers that would care about this, you would create your device
> > > > > with an unprepared clock, and then at various times during the driver
> > > > > lifetime, you would mutate that state.
> >
> > The case where you're doing it only while accessing registers is
> > interesting, because that means the Enable bit may be owned by a local
> > variable. We may imagine an:
> >
> > let enabled = self.prepared_clk.enable_scoped();
> > ... use registers
> > drop(enabled);
> >
> > Now ... this doesn't quite work with the current API - the current
> > Enabled stated owns both a prepare and enable count, but the above keeps
> > the prepare count in `self` and the enabled count in a local variable.
> > But it could be done with a fourth state, or by a closure method:
> >
> > self.prepared_clk.with_enabled(|| {
> > ... use registers
> > });
> >
> > All of this would work with an immutable variable of type Clk<Prepared>.
>
> Hm, maybe it'd make sense to implement Clone so we can have a temporary
> clk variable that has its own prepare/enable refs and releases them
> as it goes out of scope. This implies wrapping *mut bindings::clk in an
> Arc<> because bindings::clk is not ARef, but should be relatively easy
> to do. Posting the quick experiment I did with this approach, in case
> you're interested [1]
This time with a proper RawClk(*mut bindings::clk) wrapper, so we can
clk_put() called in RawClk::drop() instead of in Clk::drop().
[1]https://gitlab.freedesktop.org/bbrezillon/linux/-/commit/6fa6cb72f14373b276c61d038bc2b16f49c78f74
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com>
To: Alice Ryhl <aliceryhl@google.com>
Cc: "Maxime Ripard" <mripard@kernel.org>,
"Daniel Almeida" <daniel.almeida@collabora.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
"Viresh Kumar" <viresh.kumar@linaro.org>,
"Danilo Krummrich" <dakr@kernel.org>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Drew Fustini" <fustini@kernel.org>,
"Guo Ren" <guoren@kernel.org>, "Fu Wei" <wefu@redhat.com>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Miguel Ojeda" <ojeda@kernel.org>,
"Boqun Feng" <boqun.feng@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Benno Lossin" <lossin@kernel.org>,
"Andreas Hindborg" <a.hindborg@kernel.org>,
"Trevor Gross" <tmgross@umich.edu>,
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org,
linux-pwm@vger.kernel.org, linux-clk@vger.kernel.org,
rust-for-linux@vger.kernel.org
Subject: Re: [PATCH v3 1/3] rust: clk: use the type-state pattern
Date: Tue, 3 Feb 2026 12:26:31 +0100 [thread overview]
Message-ID: <20260203122631.3a94a935@fedora> (raw)
In-Reply-To: <20260203113902.501e5803@fedora>
On Tue, 3 Feb 2026 11:39:02 +0100
Boris Brezillon <boris.brezillon@collabora.com> wrote:
> On Mon, 19 Jan 2026 12:35:21 +0000
> Alice Ryhl <aliceryhl@google.com> wrote:
>
> > On Mon, Jan 19, 2026 at 11:45:57AM +0100, Maxime Ripard wrote:
> > > On Thu, Jan 08, 2026 at 11:14:37AM -0300, Daniel Almeida wrote:
> > > > > For example, it's quite typical to have (at least) one clock for the bus
> > > > > interface that drives the register, and one that drives the main
> > > > > component logic. The former needs to be enabled only when you're
> > > > > accessing the registers (and can be abstracted with
> > > > > regmap_mmio_attach_clk for example), and the latter needs to be enabled
> > > > > only when the device actually starts operating.
> > > > >
> > > > > You have a similar thing for the prepare vs enable thing. The difference
> > > > > between the two is that enable can be called into atomic context but
> > > > > prepare can't.
> > > > >
> > > > > So for drivers that would care about this, you would create your device
> > > > > with an unprepared clock, and then at various times during the driver
> > > > > lifetime, you would mutate that state.
> >
> > The case where you're doing it only while accessing registers is
> > interesting, because that means the Enable bit may be owned by a local
> > variable. We may imagine an:
> >
> > let enabled = self.prepared_clk.enable_scoped();
> > ... use registers
> > drop(enabled);
> >
> > Now ... this doesn't quite work with the current API - the current
> > Enabled stated owns both a prepare and enable count, but the above keeps
> > the prepare count in `self` and the enabled count in a local variable.
> > But it could be done with a fourth state, or by a closure method:
> >
> > self.prepared_clk.with_enabled(|| {
> > ... use registers
> > });
> >
> > All of this would work with an immutable variable of type Clk<Prepared>.
>
> Hm, maybe it'd make sense to implement Clone so we can have a temporary
> clk variable that has its own prepare/enable refs and releases them
> as it goes out of scope. This implies wrapping *mut bindings::clk in an
> Arc<> because bindings::clk is not ARef, but should be relatively easy
> to do. Posting the quick experiment I did with this approach, in case
> you're interested [1]
This time with a proper RawClk(*mut bindings::clk) wrapper, so we can
clk_put() called in RawClk::drop() instead of in Clk::drop().
[1]https://gitlab.freedesktop.org/bbrezillon/linux/-/commit/6fa6cb72f14373b276c61d038bc2b16f49c78f74
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next prev parent reply other threads:[~2026-02-03 11:26 UTC|newest]
Thread overview: 136+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-07 15:09 [PATCH v3 0/3] Clk improvements Daniel Almeida
2026-01-07 15:09 ` Daniel Almeida
2026-01-07 15:09 ` [PATCH v3 1/3] rust: clk: use the type-state pattern Daniel Almeida
2026-01-07 15:09 ` Daniel Almeida
2026-01-08 8:07 ` Maxime Ripard
2026-01-08 8:07 ` Maxime Ripard
2026-01-08 13:57 ` Miguel Ojeda
2026-01-08 13:57 ` Miguel Ojeda
2026-01-08 14:18 ` Daniel Almeida
2026-01-08 14:18 ` Daniel Almeida
2026-01-08 14:14 ` Daniel Almeida
2026-01-08 14:14 ` Daniel Almeida
2026-01-19 10:45 ` Maxime Ripard
2026-01-19 10:45 ` Maxime Ripard
2026-01-19 12:13 ` Daniel Almeida
2026-01-19 12:13 ` Daniel Almeida
2026-01-19 12:35 ` Alice Ryhl
2026-01-19 12:35 ` Alice Ryhl
2026-01-19 12:54 ` Daniel Almeida
2026-01-19 12:54 ` Daniel Almeida
2026-01-19 13:13 ` Danilo Krummrich
2026-01-19 13:13 ` Danilo Krummrich
2026-01-19 14:18 ` Maxime Ripard
2026-01-19 14:18 ` Maxime Ripard
2026-01-19 14:37 ` Danilo Krummrich
2026-01-19 14:37 ` Danilo Krummrich
2026-01-22 13:44 ` Maxime Ripard
2026-01-22 13:44 ` Maxime Ripard
2026-01-23 0:29 ` Daniel Almeida
2026-01-23 0:29 ` Daniel Almeida
2026-02-04 9:15 ` Maxime Ripard
2026-02-04 9:15 ` Maxime Ripard
2026-02-04 12:43 ` Daniel Almeida
2026-02-04 12:43 ` Daniel Almeida
2026-02-04 14:34 ` Maxime Ripard
2026-02-04 14:34 ` Maxime Ripard
2026-02-09 9:50 ` Boris Brezillon
2026-02-09 9:50 ` Boris Brezillon
2026-02-11 16:37 ` Maxime Ripard
2026-02-11 16:37 ` Maxime Ripard
2026-02-11 16:47 ` Danilo Krummrich
2026-02-11 16:47 ` Danilo Krummrich
2026-02-12 7:59 ` Maxime Ripard
2026-02-12 7:59 ` Maxime Ripard
2026-02-12 8:52 ` Alice Ryhl
2026-02-12 8:52 ` Alice Ryhl
2026-02-12 9:23 ` Danilo Krummrich
2026-02-12 9:23 ` Danilo Krummrich
2026-02-12 14:01 ` Danilo Krummrich
2026-02-12 14:01 ` Danilo Krummrich
2026-02-12 16:50 ` Maxime Ripard
2026-02-12 16:50 ` Maxime Ripard
2026-02-12 11:45 ` Miguel Ojeda
2026-02-12 11:45 ` Miguel Ojeda
2026-02-12 8:16 ` Alice Ryhl
2026-02-12 8:16 ` Alice Ryhl
2026-02-12 13:38 ` Maxime Ripard
2026-02-12 13:38 ` Maxime Ripard
2026-02-12 14:02 ` Alice Ryhl
2026-02-12 14:02 ` Alice Ryhl
2026-02-12 16:48 ` Maxime Ripard
2026-02-12 16:48 ` Maxime Ripard
2026-01-23 10:25 ` Danilo Krummrich
2026-01-23 10:25 ` Danilo Krummrich
2026-01-19 12:57 ` Gary Guo
2026-01-19 12:57 ` Gary Guo
2026-01-19 14:27 ` Maxime Ripard
2026-01-19 14:27 ` Maxime Ripard
2026-02-03 10:39 ` Boris Brezillon
2026-02-03 10:39 ` Boris Brezillon
2026-02-03 11:26 ` Boris Brezillon [this message]
2026-02-03 11:26 ` Boris Brezillon
2026-02-03 14:53 ` Boris Brezillon
2026-02-03 14:53 ` Boris Brezillon
2026-02-03 13:33 ` Daniel Almeida
2026-02-03 13:33 ` Daniel Almeida
2026-02-03 13:42 ` Gary Guo
2026-02-03 13:42 ` Gary Guo
2026-02-03 13:55 ` Daniel Almeida
2026-02-03 13:55 ` Daniel Almeida
2026-02-03 14:33 ` Boris Brezillon
2026-02-03 14:33 ` Boris Brezillon
2026-02-03 14:08 ` Boris Brezillon
2026-02-03 14:08 ` Boris Brezillon
2026-02-03 16:28 ` Daniel Almeida
2026-02-03 16:28 ` Daniel Almeida
2026-02-03 16:55 ` Boris Brezillon
2026-02-03 16:55 ` Boris Brezillon
2026-02-03 16:59 ` Gary Guo
2026-02-03 16:59 ` Gary Guo
2026-02-03 19:26 ` Daniel Almeida
2026-02-03 19:26 ` Daniel Almeida
2026-02-03 19:43 ` Boris Brezillon
2026-02-03 19:43 ` Boris Brezillon
2026-02-03 20:36 ` Gary Guo
2026-02-03 20:36 ` Gary Guo
2026-02-04 8:11 ` Boris Brezillon
2026-02-04 8:11 ` Boris Brezillon
2026-02-04 9:18 ` Maxime Ripard
2026-02-04 9:18 ` Maxime Ripard
2026-01-19 14:26 ` Gary Guo
2026-01-19 14:26 ` Gary Guo
2026-01-19 15:44 ` Daniel Almeida
2026-01-19 15:44 ` Daniel Almeida
2026-01-19 14:20 ` Gary Guo
2026-01-19 14:20 ` Gary Guo
2026-01-19 15:22 ` Miguel Ojeda
2026-01-19 15:22 ` Miguel Ojeda
2026-01-19 15:36 ` Gary Guo
2026-01-19 15:36 ` Gary Guo
2026-01-19 15:46 ` Miguel Ojeda
2026-01-19 15:46 ` Miguel Ojeda
2026-01-19 16:10 ` Gary Guo
2026-01-19 16:10 ` Gary Guo
2026-02-02 16:10 ` Boris Brezillon
2026-02-02 16:10 ` Boris Brezillon
2026-02-03 9:09 ` Boris Brezillon
2026-02-03 9:09 ` Boris Brezillon
2026-02-03 9:47 ` Boris Brezillon
2026-02-03 9:47 ` Boris Brezillon
2026-02-03 13:37 ` Daniel Almeida
2026-02-03 13:37 ` Daniel Almeida
2026-02-03 14:18 ` Boris Brezillon
2026-02-03 14:18 ` Boris Brezillon
2026-02-03 9:17 ` Boris Brezillon
2026-02-03 9:17 ` Boris Brezillon
2026-02-03 13:35 ` Daniel Almeida
2026-02-03 13:35 ` Daniel Almeida
2026-01-07 15:09 ` [PATCH v3 2/3] rust: clk: add devres-managed clks Daniel Almeida
2026-01-07 15:09 ` Daniel Almeida
2026-01-19 14:33 ` Gary Guo
2026-01-19 14:33 ` Gary Guo
2026-01-07 15:09 ` [PATCH v3 3/3] rust: clk: use 'kernel vertical style' for imports Daniel Almeida
2026-01-07 15:09 ` Daniel Almeida
2026-01-08 7:53 ` Maxime Ripard
2026-01-08 7:53 ` Maxime Ripard
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