Re: [PATCH] hw/pci: Use correct bus aperture for device container size

["Michael S. Tsirkin" <mst@redhat.com>]

On Mon, Nov 24, 2025 at 12:47:54PM +0100, Philippe Mathieu-Daudé wrote:
> Before commit 3716d5902d7 ("pci: introduce a bus master container")
> device view of the bus address space was correctly sized to the
> bus aperture, but then it always used a 64-bit aperture. Restore
> the previous behavior, so devices on 32-bit PCI only see 32-bit
> address space.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>


Wait I am confused. Is there a problem this is trying to fix?


> ---
>  hw/pci/pci.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index b1eba348e06..64f33b9de04 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -1375,7 +1375,8 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
>      pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
>  
>      memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
> -                       "bus master container", UINT64_MAX);
> +                       "bus master container",
> +                       memory_region_size(bus->address_space_mem));

as far as I can tell this does more than it says it does.


Look at raven.c:
                                                                                                                                         
  h->bus = pci_register_root_bus(d, NULL, raven_set_irq, raven_map_irq,                                                                  
                                 s, &s->pci_memory, &s->pci_io, 0, 4,                                                                    
                                 TYPE_PCI_BUS);                                                                                          
                                                                                                                                         
  The bus is created with &s->pci_memory (1G) as the address space.                                                  
                                                                                                                                         
  But the actual bus master space (&s->bm at line 285) is 4 G.                                                                         
                                                                                                                                         
  Your patch limits DMA to 1G. No?

failures here (definitely the ppc one)

https://gitlab.com/mstredhat/qemu/-/jobs/12984084992

reverting fixed it:

https://gitlab.com/mstredhat/qemu/-/jobs/12984187692



                                                                                                                                         
>      address_space_init(&pci_dev->bus_master_as,
>                         &pci_dev->bus_master_container_region, pci_dev->name);
>      pci_dev->bus_master_as.max_bounce_buffer_size =
> -- 
> 2.51.0