[PATCH v1 00/10] Support ASPEED AST2700 A2

[PATCH v1 00/10] Support ASPEED AST2700 A2

[Jamin Lin]

v1
  1. Add AST2700 A2 SoC support
  2. Add AST2700 A2 EVB machine
  3. Alias ast2700-evb to ast2700a2-evb
  4. Switch AST2700 FC machine to use the A2 SoC
  5. Update functional tests for both AST2700 A1 and A2
  6. Fix I2C Fix Out-of-Bounds access issue

Jamin Lin (10):
  hw/i2c/aspeed_i2c: Fix Out-of-Bounds access by using dynamic register
    array
  hw/i2c/aspeed_i2c: Increase I2C device register size to 0xA0
  hw/misc/aspeed_scu: Remove unused SoC silicon revision definitions
  hw/misc/aspeed_scu: Add AST2700 A2 silicon revisions
  hw/arm/aspeed_ast27x0: Add AST2700 A2 SoC support
  hw/arm/aspeed_ast27x0_evb: Add AST2700 A2 EVB machine
  tests/qtest/ast2700-hace-test: Use ast2700-evb alias for AST2700 HACE
    tests
  tests/functional/aarch64/test_aspeed_ast2700: Add AST2700 A2 EVB
    functional tests
  hw/arm/aspeed_ast27x0-fc: Switch AST2700 FC machine to A2 SoC
  tests/functional/aarch64/test_aspeed_ast2700fc: Use AST2700 A2 SDK
    image for FC tests

 include/hw/i2c/aspeed_i2c.h                   |  4 +-
 include/hw/misc/aspeed_scu.h                  | 11 +---
 hw/arm/aspeed_ast27x0-fc.c                    | 15 +++---
 hw/arm/aspeed_ast27x0.c                       | 36 +++++++++++++
 hw/arm/aspeed_ast27x0_evb.c                   | 29 +++++++++-
 hw/i2c/aspeed_i2c.c                           | 54 +++++++++++--------
 hw/misc/aspeed_scu.c                          | 11 +---
 tests/qtest/ast2700-hace-test.c               | 22 ++++----
 .../functional/aarch64/test_aspeed_ast2700.py | 44 +++++++++++++++
 .../aarch64/test_aspeed_ast2700fc.py          | 16 +++---
 10 files changed, 169 insertions(+), 73 deletions(-)

-- 
2.43.0

[PATCH v1 01/10] hw/i2c/aspeed_i2c: Fix Out-of-Bounds access by using dynamic register array

[Jamin Lin]

The ASPEED I2C controller emulation used a fixed-size register array
(28 dwords) for all SoC variants, while multiple ASPEED SoCs
(AST2600, AST1030, AST2700) expose a larger MMIO register window
(e.g. reg_size = 0x80).

This mismatch allows MMIO accesses beyond the allocated register
array, leading to out-of-bounds reads in the I2C controller model.

Fix this by converting the register storage to a dynamically allocated
array sized according to the controller class reg_size. The register
array is now allocated during bus realize and free on unrealize,
ensuring safe access across different ASPEED SoC implementations.

This change eliminates I2C register out-of-bounds access caused by
SoC-specific register size differences.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3290
---
 include/hw/i2c/aspeed_i2c.h |  4 +---
 hw/i2c/aspeed_i2c.c         | 18 ++++++++++++++----
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index 68bd138026..205f0a58d2 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -36,8 +36,6 @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
 #define ASPEED_I2C_NR_BUSSES 16
 #define ASPEED_I2C_SHARE_POOL_SIZE 0x800
 #define ASPEED_I2C_BUS_POOL_SIZE 0x20
-#define ASPEED_I2C_OLD_NUM_REG 11
-#define ASPEED_I2C_NEW_NUM_REG 28
 
 #define A_I2CD_M_STOP_CMD       BIT(5)
 #define A_I2CD_M_RX_CMD         BIT(3)
@@ -256,7 +254,7 @@ struct AspeedI2CBus {
     uint8_t id;
     qemu_irq irq;
 
-    uint32_t regs[ASPEED_I2C_NEW_NUM_REG];
+    uint32_t *regs;
     uint8_t pool[ASPEED_I2C_BUS_POOL_SIZE];
     uint64_t dma_dram_offset;
 };
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index fb3d6a5600..cf3a003978 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -1091,10 +1091,9 @@ static const MemoryRegionOps aspeed_i2c_bus_pool_ops = {
 
 static const VMStateDescription aspeed_i2c_bus_vmstate = {
     .name = TYPE_ASPEED_I2C,
-    .version_id = 6,
-    .minimum_version_id = 6,
+    .version_id = 7,
+    .minimum_version_id = 7,
     .fields = (const VMStateField[]) {
-        VMSTATE_UINT32_ARRAY(regs, AspeedI2CBus, ASPEED_I2C_NEW_NUM_REG),
         VMSTATE_UINT8_ARRAY(pool, AspeedI2CBus, ASPEED_I2C_BUS_POOL_SIZE),
         VMSTATE_UINT64(dma_dram_offset, AspeedI2CBus),
         VMSTATE_END_OF_LIST()
@@ -1465,8 +1464,9 @@ static const TypeInfo aspeed_i2c_bus_slave_info = {
 static void aspeed_i2c_bus_reset(DeviceState *dev)
 {
     AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
+    AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s->controller);
 
-    memset(s->regs, 0, sizeof(s->regs));
+    memset(s->regs, 0, aic->reg_size);
     i2c_end_transfer(s->bus);
 }
 
@@ -1492,6 +1492,7 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp)
     s->slave = i2c_slave_create_simple(s->bus, TYPE_ASPEED_I2C_BUS_SLAVE,
                                        0xff);
 
+    s->regs = g_new(uint32_t, aic->reg_size >> 2);
     memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i2c_bus_ops,
                           s, s->name, aic->reg_size);
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr);
@@ -1501,6 +1502,14 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp)
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr_pool);
 }
 
+static void aspeed_i2c_bus_unrealize(DeviceState *dev)
+{
+    AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
+
+    g_free(s->regs);
+    s->regs = NULL;
+}
+
 static const Property aspeed_i2c_bus_properties[] = {
     DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0),
     DEFINE_PROP_LINK("controller", AspeedI2CBus, controller, TYPE_ASPEED_I2C,
@@ -1514,6 +1523,7 @@ static void aspeed_i2c_bus_class_init(ObjectClass *klass, const void *data)
 
     dc->desc = "Aspeed I2C Bus";
     dc->realize = aspeed_i2c_bus_realize;
+    dc->unrealize = aspeed_i2c_bus_unrealize;
     device_class_set_legacy_reset(dc, aspeed_i2c_bus_reset);
     device_class_set_props(dc, aspeed_i2c_bus_properties);
 }
-- 
2.43.0

[PATCH v1 1/1] tests/functional/aarch64/test_aspeed_ast2700fc: Use AST2700 A2 SDK image for FC tests

[Jamin Lin]

Update AST2700 FC functional tests to use the AST2700 A2 SDK v11.00 image.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 .../functional/aarch64/test_aspeed_ast2700fc.py  | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index 47e56dcfc5..51ee8bc787 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -62,8 +62,8 @@ def load_ast2700fc_coprocessor(self, name):
                              f'loader,file={file},cpu-num={cpu_num}')
 
     ASSET_SDK_V1100_AST2700 = Asset(
-            'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-obmc.tar.gz',
-            'd5ceed511cd0dfefbb102fff2d731159e0472948a28066dc0d90bcd54be76525')
+            'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-default-obmc.tar.gz',
+            'e2b8f043fe8063dd3b6ded93422e38bd41914dc9c3202199507652df024de4dc')
 
     def do_ast2700_i2c_test(self):
         exec_command_and_wait_for_pattern(self,
@@ -98,7 +98,7 @@ def do_ast2700fc_ssp_test(self):
         exec_command_and_wait_for_pattern(self, 'version',
                                           'Zephyr version 3.7.1')
         exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
-                                          '[72c02000] 06010103')
+                                          '[72c02000] 06020103')
 
     def do_ast2700fc_tsp_test(self):
         self.vm.shutdown()
@@ -109,7 +109,7 @@ def do_ast2700fc_tsp_test(self):
         exec_command_and_wait_for_pattern(self, 'version',
                                           'Zephyr version 3.7.1')
         exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
-                                          '[72c02000] 06010103')
+                                          '[72c02000] 06020103')
 
     def start_ast2700fc_test(self, name):
         ca35_core = 4
@@ -153,8 +153,8 @@ def test_aarch64_ast2700fc_sdk_v11_00(self):
         self.require_netdev('user')
 
         self.archive_extract(self.ASSET_SDK_V1100_AST2700)
-        self.start_ast2700fc_test('ast2700-a1')
-        self.verify_openbmc_boot_and_login('ast2700-a1')
+        self.start_ast2700fc_test('ast2700-default')
+        self.verify_openbmc_boot_and_login('ast2700-default')
         self.do_ast2700_i2c_test()
         self.do_ast2700_pcie_test()
         self.do_ast2700fc_ssp_test()
@@ -164,8 +164,8 @@ def test_aarch64_ast2700fc_sdk_vbootrom_v11_00(self):
         self.set_machine('ast2700fc')
 
         self.archive_extract(self.ASSET_SDK_V1100_AST2700)
-        self.start_ast2700fc_test_vbootrom('ast2700-a1')
-        self.verify_openbmc_boot_and_login('ast2700-a1')
+        self.start_ast2700fc_test_vbootrom('ast2700-default')
+        self.verify_openbmc_boot_and_login('ast2700-default')
         self.do_ast2700fc_ssp_test()
         self.do_ast2700fc_tsp_test()
 
-- 
2.43.0

[PATCH v1 02/10] hw/i2c/aspeed_i2c: Increase I2C device register size to 0xA0

[Jamin Lin]

According to the AST2700 A1 datasheet, the register space for each I2C
device instance has been expanded from 0x80 bytes to 0xA0 bytes.

Update the AST2700 I2C controller configuration to reflect the new
register layout by increasing the per-device register size to 0xA0
and adjusting the register gap size accordingly.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/i2c/aspeed_i2c.c | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index cf3a003978..e1682c9bdd 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -1206,37 +1206,37 @@ static void aspeed_i2c_instance_init(Object *obj)
  *
  * Address Definitions (AST2700)
  *   0x000 ... 0x0FF: Global Register
- *   0x100 ... 0x17F: Device 0
+ *   0x100 ... 0x19F: Device 0
  *   0x1A0 ... 0x1BF: Device 0 buffer
- *   0x200 ... 0x27F: Device 1
+ *   0x200 ... 0x29F: Device 1
  *   0x2A0 ... 0x2BF: Device 1 buffer
- *   0x300 ... 0x37F: Device 2
+ *   0x300 ... 0x39F: Device 2
  *   0x3A0 ... 0x3BF: Device 2 buffer
- *   0x400 ... 0x47F: Device 3
+ *   0x400 ... 0x49F: Device 3
  *   0x4A0 ... 0x4BF: Device 3 buffer
- *   0x500 ... 0x57F: Device 4
+ *   0x500 ... 0x59F: Device 4
  *   0x5A0 ... 0x5BF: Device 4 buffer
- *   0x600 ... 0x67F: Device 5
+ *   0x600 ... 0x69F: Device 5
  *   0x6A0 ... 0x6BF: Device 5 buffer
- *   0x700 ... 0x77F: Device 6
+ *   0x700 ... 0x79F: Device 6
  *   0x7A0 ... 0x7BF: Device 6 buffer
- *   0x800 ... 0x87F: Device 7
+ *   0x800 ... 0x89F: Device 7
  *   0x8A0 ... 0x8BF: Device 7 buffer
- *   0x900 ... 0x97F: Device 8
+ *   0x900 ... 0x99F: Device 8
  *   0x9A0 ... 0x9BF: Device 8 buffer
- *   0xA00 ... 0xA7F: Device 9
+ *   0xA00 ... 0xA9F: Device 9
  *   0xAA0 ... 0xABF: Device 9 buffer
- *   0xB00 ... 0xB7F: Device 10
+ *   0xB00 ... 0xB9F: Device 10
  *   0xBA0 ... 0xBBF: Device 10 buffer
- *   0xC00 ... 0xC7F: Device 11
+ *   0xC00 ... 0xC9F: Device 11
  *   0xCA0 ... 0xCBF: Device 11 buffer
- *   0xD00 ... 0xD7F: Device 12
+ *   0xD00 ... 0xD9F: Device 12
  *   0xDA0 ... 0xDBF: Device 12 buffer
- *   0xE00 ... 0xE7F: Device 13
+ *   0xE00 ... 0xE9F: Device 13
  *   0xEA0 ... 0xEBF: Device 13 buffer
- *   0xF00 ... 0xF7F: Device 14
+ *   0xF00 ... 0xF9F: Device 14
  *   0xFA0 ... 0xFBF: Device 14 buffer
- *   0x1000 ... 0x107F: Device 15
+ *   0x1000 ... 0x109F: Device 15
  *   0x10A0 ... 0x10BF: Device 15 buffer
  */
 static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
@@ -1670,8 +1670,8 @@ static void aspeed_2700_i2c_class_init(ObjectClass *klass, const void *data)
     dc->desc = "ASPEED 2700 I2C Controller";
 
     aic->num_busses = 16;
-    aic->reg_size = 0x80;
-    aic->reg_gap_size = 0x80;
+    aic->reg_size = 0xa0;
+    aic->reg_gap_size = 0x60;
     aic->gap = -1; /* no gap */
     aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq;
     aic->pool_size = 0x20;
-- 
2.43.0

[PATCH v1 03/10] hw/misc/aspeed_scu: Remove unused SoC silicon revision definitions

[Jamin Lin]

Several legacy Aspeed SoC silicon revision definitions are no longer
used by any machine models or runtime logic.

Remove unused silicon revision macros and corresponding entries from
the silicon revision table to reduce dead code and improve
maintainability.

No functional change intended.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 include/hw/misc/aspeed_scu.h | 10 ----------
 hw/misc/aspeed_scu.c         | 10 ----------
 2 files changed, 20 deletions(-)

diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 9e28bd4d2e..313a79f2f7 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -41,22 +41,12 @@ struct AspeedSCUState {
     uint32_t hw_prot_key;
 };
 
-#define AST2400_A0_SILICON_REV   0x02000303U
 #define AST2400_A1_SILICON_REV   0x02010303U
-#define AST2500_A0_SILICON_REV   0x04000303U
 #define AST2500_A1_SILICON_REV   0x04010303U
-#define AST2600_A0_SILICON_REV   0x05000303U
-#define AST2600_A1_SILICON_REV   0x05010303U
-#define AST2600_A2_SILICON_REV   0x05020303U
 #define AST2600_A3_SILICON_REV   0x05030303U
-#define AST1030_A0_SILICON_REV   0x80000000U
 #define AST1030_A1_SILICON_REV   0x80010000U
 #define AST1060_A2_SILICON_REV   0xA0030000U
-#define AST2700_A0_SILICON_REV   0x06000103U
-#define AST2720_A0_SILICON_REV   0x06000203U
-#define AST2750_A0_SILICON_REV   0x06000003U
 #define AST2700_A1_SILICON_REV   0x06010103U
-#define AST2750_A1_SILICON_REV   0x06010003U
 
 #define ASPEED_IS_AST2500(si_rev)     ((((si_rev) >> 24) & 0xff) == 0x04)
 
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 6829efa2dc..0edf9c1b16 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -555,22 +555,12 @@ static void aspeed_scu_reset(DeviceState *dev)
 }
 
 static uint32_t aspeed_silicon_revs[] = {
-    AST2400_A0_SILICON_REV,
     AST2400_A1_SILICON_REV,
-    AST2500_A0_SILICON_REV,
     AST2500_A1_SILICON_REV,
-    AST2600_A0_SILICON_REV,
-    AST2600_A1_SILICON_REV,
-    AST2600_A2_SILICON_REV,
     AST2600_A3_SILICON_REV,
-    AST1030_A0_SILICON_REV,
     AST1030_A1_SILICON_REV,
     AST1060_A2_SILICON_REV,
-    AST2700_A0_SILICON_REV,
-    AST2720_A0_SILICON_REV,
-    AST2750_A0_SILICON_REV,
     AST2700_A1_SILICON_REV,
-    AST2750_A1_SILICON_REV,
 };
 
 bool is_supported_silicon_rev(uint32_t silicon_rev)
-- 
2.43.0

[PATCH v1 04/10] hw/misc/aspeed_scu: Add AST2700 A2 silicon revisions

[Jamin Lin]

Add silicon revision definitions for AST2700 A2, and include
them in the list of supported Aspeed silicon revisions.

This allows newer AST27x0 A2 silicon to be correctly identified via
the SCU silicon revision register.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 include/hw/misc/aspeed_scu.h | 1 +
 hw/misc/aspeed_scu.c         | 1 +
 2 files changed, 2 insertions(+)

diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 313a79f2f7..d003955428 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -47,6 +47,7 @@ struct AspeedSCUState {
 #define AST1030_A1_SILICON_REV   0x80010000U
 #define AST1060_A2_SILICON_REV   0xA0030000U
 #define AST2700_A1_SILICON_REV   0x06010103U
+#define AST2700_A2_SILICON_REV   0x06020103U
 
 #define ASPEED_IS_AST2500(si_rev)     ((((si_rev) >> 24) & 0xff) == 0x04)
 
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 0edf9c1b16..e4160356e4 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -561,6 +561,7 @@ static uint32_t aspeed_silicon_revs[] = {
     AST1030_A1_SILICON_REV,
     AST1060_A2_SILICON_REV,
     AST2700_A1_SILICON_REV,
+    AST2700_A2_SILICON_REV,
 };
 
 bool is_supported_silicon_rev(uint32_t silicon_rev)
-- 
2.43.0

[PATCH v1 05/10] hw/arm/aspeed_ast27x0: Add AST2700 A2 SoC support

[Jamin Lin]

Introduce a new AST2700 A2 SoC variant by adding a dedicated class
initialization function.

This commit sets the A2 silicon revision and defines its SoC
capabilities, including CPU type, SRAM size, peripheral counts, and
CPU topology, while reusing the existing IRQ and memory maps.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast27x0.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 61790ea1cc..87dcb82e1b 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -1166,6 +1166,36 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
     sc->memmap       = aspeed_soc_ast2700_memmap;
 }
 
+static void aspeed_soc_ast2700a2_class_init(ObjectClass *oc, const void *data)
+{
+    static const char * const valid_cpu_types[] = {
+        ARM_CPU_TYPE_NAME("cortex-a35"),
+        NULL
+    };
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+
+    /* Reason: The Aspeed SoC can only be instantiated from a board */
+    dc->user_creatable = false;
+    dc->realize      = aspeed_soc_ast2700_realize;
+
+    sc->valid_cpu_types = valid_cpu_types;
+    sc->silicon_rev  = AST2700_A2_SILICON_REV;
+    sc->sram_size    = 0x20000;
+    sc->pcie_num     = 3;
+    sc->spis_num     = 3;
+    sc->sgpio_num    = 2;
+    sc->ehcis_num    = 4;
+    sc->wdts_num     = 8;
+    sc->macs_num     = 3;
+    sc->uarts_num    = 13;
+    sc->num_cpus     = 4;
+    sc->ioexp_num    = 2;
+    sc->uarts_base   = ASPEED_DEV_UART0;
+    sc->irqmap       = aspeed_soc_ast2700a1_irqmap;
+    sc->memmap       = aspeed_soc_ast2700_memmap;
+}
+
 static const TypeInfo aspeed_soc_ast27x0_types[] = {
     {
         .name           = TYPE_ASPEED27X0_SOC,
@@ -1179,6 +1209,12 @@ static const TypeInfo aspeed_soc_ast27x0_types[] = {
         .instance_init  = aspeed_soc_ast2700_init,
         .class_init     = aspeed_soc_ast2700a1_class_init,
     },
+    {
+        .name           = "ast2700-a2",
+        .parent         = TYPE_ASPEED27X0_SOC,
+        .instance_init  = aspeed_soc_ast2700_init,
+        .class_init     = aspeed_soc_ast2700a2_class_init,
+    },
 };
 
 DEFINE_TYPES(aspeed_soc_ast27x0_types)
-- 
2.43.0

[PATCH v1 06/10] hw/arm/aspeed_ast27x0_evb: Add AST2700 A2 EVB machine

[Jamin Lin]

Add a new AST2700 A2 EVB machine to model the newer A2 silicon.

The "ast2700-evb" machine alias is moved to the AST2700 A2 EVB, making
it the default AST2700 evaluation board. The existing AST2700 A1 EVB
machine remains available as "ast2700a1-evb".

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast27x0_evb.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c
index 31f7d61117..0ff1bebeb0 100644
--- a/hw/arm/aspeed_ast27x0_evb.c
+++ b/hw/arm/aspeed_ast27x0_evb.c
@@ -34,7 +34,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
     MachineClass *mc = MACHINE_CLASS(oc);
     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
 
-    mc->alias = "ast2700-evb";
     mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)";
     amc->soc_name  = "ast2700-a1";
     amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
@@ -50,12 +49,40 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
     aspeed_machine_class_init_cpus_defaults(mc);
 }
 
+static void aspeed_machine_ast2700a2_evb_class_init(ObjectClass *oc,
+                                                    const void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+    mc->alias = "ast2700-evb";
+    mc->desc = "Aspeed AST2700 A2 EVB (Cortex-A35)";
+    amc->soc_name  = "ast2700-a2";
+    amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
+    amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
+    amc->fmc_model = "w25q01jvq";
+    amc->spi_model = "w25q512jv";
+    amc->num_cs    = 2;
+    amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
+    amc->uart_default = ASPEED_DEV_UART12;
+    amc->i2c_init  = ast2700_evb_i2c_init;
+    amc->vbootrom = true;
+    mc->default_ram_size = 2 * GiB;
+    aspeed_machine_class_init_cpus_defaults(mc);
+}
+
 static const TypeInfo aspeed_ast27x0_evb_types[] = {
     {
         .name          = MACHINE_TYPE_NAME("ast2700a1-evb"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_ast2700a1_evb_class_init,
         .interfaces    = aarch64_machine_interfaces,
+    },
+    {
+        .name          = MACHINE_TYPE_NAME("ast2700a2-evb"),
+        .parent        = TYPE_ASPEED_MACHINE,
+        .class_init    = aspeed_machine_ast2700a2_evb_class_init,
+        .interfaces    = aarch64_machine_interfaces,
     }
 };
 
-- 
2.43.0

[PATCH v1 07/10] tests/qtest/ast2700-hace-test: Use ast2700-evb alias for AST2700 HACE tests

[Jamin Lin]

Update AST2700 HACE qtests to use the "ast2700-evb" machine alias
instead of a specific silicon revision.

The AST2700 A1 and A2 revisions are compatible for the HACE model, so
the tests do not depend on a particular EVB revision. Using the
"ast2700-evb" alias ensures the tests always run the latest
supported AST2700 silicon revision.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 tests/qtest/ast2700-hace-test.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/tests/qtest/ast2700-hace-test.c b/tests/qtest/ast2700-hace-test.c
index a400e2962b..508a34dd6c 100644
--- a/tests/qtest/ast2700-hace-test.c
+++ b/tests/qtest/ast2700-hace-test.c
@@ -23,57 +23,57 @@ static const struct AspeedMasks as2700_masks = {
 /* ast2700 */
 static void test_md5_ast2700(void)
 {
-    aspeed_test_md5("-machine ast2700a1-evb", 0x12070000, 0x400000000);
+    aspeed_test_md5("-machine ast2700-evb", 0x12070000, 0x400000000);
 }
 
 static void test_sha256_ast2700(void)
 {
-    aspeed_test_sha256("-machine ast2700a1-evb", 0x12070000, 0x400000000);
+    aspeed_test_sha256("-machine ast2700-evb", 0x12070000, 0x400000000);
 }
 
 static void test_sha256_sg_ast2700(void)
 {
-    aspeed_test_sha256_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000);
+    aspeed_test_sha256_sg("-machine ast2700-evb", 0x12070000, 0x400000000);
 }
 
 static void test_sha384_ast2700(void)
 {
-    aspeed_test_sha384("-machine ast2700a1-evb", 0x12070000, 0x400000000);
+    aspeed_test_sha384("-machine ast2700-evb", 0x12070000, 0x400000000);
 }
 
 static void test_sha384_sg_ast2700(void)
 {
-    aspeed_test_sha384_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000);
+    aspeed_test_sha384_sg("-machine ast2700-evb", 0x12070000, 0x400000000);
 }
 
 static void test_sha512_ast2700(void)
 {
-    aspeed_test_sha512("-machine ast2700a1-evb", 0x12070000, 0x400000000);
+    aspeed_test_sha512("-machine ast2700-evb", 0x12070000, 0x400000000);
 }
 
 static void test_sha512_sg_ast2700(void)
 {
-    aspeed_test_sha512_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000);
+    aspeed_test_sha512_sg("-machine ast2700-evb", 0x12070000, 0x400000000);
 }
 
 static void test_sha256_accum_ast2700(void)
 {
-    aspeed_test_sha256_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000);
+    aspeed_test_sha256_accum("-machine ast2700-evb", 0x12070000, 0x400000000);
 }
 
 static void test_sha384_accum_ast2700(void)
 {
-    aspeed_test_sha384_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000);
+    aspeed_test_sha384_accum("-machine ast2700-evb", 0x12070000, 0x400000000);
 }
 
 static void test_sha512_accum_ast2700(void)
 {
-    aspeed_test_sha512_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000);
+    aspeed_test_sha512_accum("-machine ast2700-evb", 0x12070000, 0x400000000);
 }
 
 static void test_addresses_ast2700(void)
 {
-    aspeed_test_addresses("-machine ast2700a1-evb", 0x12070000, &as2700_masks);
+    aspeed_test_addresses("-machine ast2700-evb", 0x12070000, &as2700_masks);
 }
 
 int main(int argc, char **argv)
-- 
2.43.0

[PATCH v1 08/10] tests/functional/aarch64/test_aspeed_ast2700: Add AST2700 A2 EVB functional tests

[Jamin Lin]

Add functional coverage for the AST2700 A2 EVB machine by introducing
test cases that boot and validate an OpenBMC SDK v11.00 image on
"ast2700a2-evb".

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 .../functional/aarch64/test_aspeed_ast2700.py | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functional/aarch64/test_aspeed_ast2700.py
index 61373ffe5b..68e930ab72 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700.py
@@ -86,6 +86,14 @@ def verify_openbmc_boot_and_login(self, name, enable_pcie=True):
             'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-dcscm-obmc.tar.gz',
             '4f8778be176ece1b57d33c4aee13bb989be114c3e4703150eaeb6f996bd5587f')
 
+    ASSET_SDK_V1100_AST2700A2 = Asset(
+            'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-default-obmc.tar.gz',
+            'e2b8f043fe8063dd3b6ded93422e38bd41914dc9c3202199507652df024de4dc')
+
+    ASSET_SDK_V1100_AST2700A2_DCSCM = Asset(
+            'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-dcscm-obmc.tar.gz',
+            '0e93f7976139da71fab9df7952a58bdd80650e23e7abf5853b0eb6695deb02d0')
+
     def do_ast2700_i2c_test(self, bus_id):
         bus_str = str(bus_id)
         exec_command_and_wait_for_pattern(self,
@@ -159,6 +167,18 @@ def test_aarch64_ast2700a1_evb_sdk_v11_00(self):
         self.do_ast2700_i2c_test(1)
         self.do_ast2700_pcie_test()
 
+    def test_aarch64_ast2700a2_evb_sdk_v11_00(self):
+        self.set_machine('ast2700a2-evb')
+        self.require_netdev('user')
+
+        self.archive_extract(self.ASSET_SDK_V1100_AST2700A2)
+        self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
+        self.vm.add_args('-netdev', 'user,id=net1')
+        self.start_ast2700_test('ast2700-default', 1)
+        self.verify_openbmc_boot_and_login('ast2700-default')
+        self.do_ast2700_i2c_test(1)
+        self.do_ast2700_pcie_test()
+
     def test_aarch64_ast2700a1_evb_sdk_vbootrom_v11_00(self):
         self.set_machine('ast2700a1-evb')
         self.require_netdev('user')
@@ -170,6 +190,17 @@ def test_aarch64_ast2700a1_evb_sdk_vbootrom_v11_00(self):
         self.verify_vbootrom_firmware_flow()
         self.verify_openbmc_boot_start()
 
+    def test_aarch64_ast2700a2_evb_sdk_vbootrom_v11_00(self):
+        self.set_machine('ast2700a2-evb')
+        self.require_netdev('user')
+
+        self.archive_extract(self.ASSET_SDK_V1100_AST2700A2)
+        self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
+        self.vm.add_args('-netdev', 'user,id=net1')
+        self.start_ast2700_test_vbootrom('ast2700-default', 1)
+        self.verify_vbootrom_firmware_flow()
+        self.verify_openbmc_boot_start()
+
     def test_aarch64_ast2700a1_evb_ioexp_v11_00(self):
         self.set_machine('ast2700a1-evb')
         self.require_netdev('user')
@@ -183,5 +214,18 @@ def test_aarch64_ast2700a1_evb_ioexp_v11_00(self):
         self.do_ast2700_i2c_test(8)
         self.do_ast2700_i2c_test(16)
 
+    def test_aarch64_ast2700a2_evb_ioexp_v11_00(self):
+        self.set_machine('ast2700a2-evb')
+        self.require_netdev('user')
+
+        self.archive_extract(self.ASSET_SDK_V1100_AST2700A2_DCSCM)
+        self.vm.set_machine('ast2700a2-evb,fmc-model=w25q512jv')
+        self.vm.add_args('-device',
+                         'tmp105,bus=ioexp0.0,address=0x4d,id=tmp-test-16')
+        self.start_ast2700_test('ast2700-dcscm', 8)
+        self.verify_openbmc_boot_and_login('ast2700-dcscm', False)
+        self.do_ast2700_i2c_test(8)
+        self.do_ast2700_i2c_test(16)
+
 if __name__ == '__main__':
     QemuSystemTest.main()
-- 
2.43.0

[PATCH v1 09/10] hw/arm/aspeed_ast27x0-fc: Switch AST2700 FC machine to A2 SoC

[Jamin Lin]

Update the AST2700 FC machine to use the AST2700 A2 SoC model instead of
the A1-specific variant.

This change removes A1-specific naming and definitions from the FC
machine and aligns it with the newer AST2700 A2 silicon.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast27x0-fc.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 0502a137f3..5eb6680da9 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -24,8 +24,8 @@
 #include "hw/arm/aspeed_coprocessor.h"
 #include "hw/arm/machines-qom.h"
 
-#define TYPE_AST2700A1FC MACHINE_TYPE_NAME("ast2700fc")
-OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700A1FC);
+#define TYPE_AST2700FC MACHINE_TYPE_NAME("ast2700fc")
+OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700FC);
 
 static struct arm_boot_info ast2700fc_board_info = {
     .board_id = -1, /* device-tree-only board */
@@ -48,8 +48,7 @@ struct Ast2700FCState {
     Aspeed27x0CoprocessorState tsp;
 };
 
-#define AST2700FC_BMC_RAM_SIZE (1 * GiB)
-#define AST2700FC_CM4_DRAM_SIZE (32 * MiB)
+#define AST2700FC_BMC_RAM_SIZE (2 * GiB)
 
 #define AST2700FC_HW_STRAP1 0x000000C0
 #define AST2700FC_HW_STRAP2 0x00000003
@@ -58,7 +57,7 @@ struct Ast2700FCState {
 
 static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
 {
-    Ast2700FCState *s = AST2700A1FC(machine);
+    Ast2700FCState *s = AST2700FC(machine);
     AspeedSoCState *soc;
     AspeedSoCClass *sc;
     const char *bios_name = NULL;
@@ -66,7 +65,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
     DeviceState *dev = NULL;
     uint64_t rom_size;
 
-    object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1");
+    object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a2");
     soc = ASPEED_SOC(&s->ca35);
     sc = ASPEED_SOC_GET_CLASS(soc);
 
@@ -135,7 +134,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
 
 static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
 {
-    Ast2700FCState *s = AST2700A1FC(machine);
+    Ast2700FCState *s = AST2700FC(machine);
     AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
 
     s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
@@ -167,7 +166,7 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
 
 static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
 {
-    Ast2700FCState *s = AST2700A1FC(machine);
+    Ast2700FCState *s = AST2700FC(machine);
     AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
 
     s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
-- 
2.43.0

[PATCH v1 10/10] tests/functional/aarch64/test_aspeed_ast2700fc: Use AST2700 A2 SDK image for FC tests

[Jamin Lin]

Update AST2700 FC functional tests to use the AST2700 A2 SDK v11.00 image.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 .../functional/aarch64/test_aspeed_ast2700fc.py  | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index 47e56dcfc5..51ee8bc787 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -62,8 +62,8 @@ def load_ast2700fc_coprocessor(self, name):
                              f'loader,file={file},cpu-num={cpu_num}')
 
     ASSET_SDK_V1100_AST2700 = Asset(
-            'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-obmc.tar.gz',
-            'd5ceed511cd0dfefbb102fff2d731159e0472948a28066dc0d90bcd54be76525')
+            'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-default-obmc.tar.gz',
+            'e2b8f043fe8063dd3b6ded93422e38bd41914dc9c3202199507652df024de4dc')
 
     def do_ast2700_i2c_test(self):
         exec_command_and_wait_for_pattern(self,
@@ -98,7 +98,7 @@ def do_ast2700fc_ssp_test(self):
         exec_command_and_wait_for_pattern(self, 'version',
                                           'Zephyr version 3.7.1')
         exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
-                                          '[72c02000] 06010103')
+                                          '[72c02000] 06020103')
 
     def do_ast2700fc_tsp_test(self):
         self.vm.shutdown()
@@ -109,7 +109,7 @@ def do_ast2700fc_tsp_test(self):
         exec_command_and_wait_for_pattern(self, 'version',
                                           'Zephyr version 3.7.1')
         exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
-                                          '[72c02000] 06010103')
+                                          '[72c02000] 06020103')
 
     def start_ast2700fc_test(self, name):
         ca35_core = 4
@@ -153,8 +153,8 @@ def test_aarch64_ast2700fc_sdk_v11_00(self):
         self.require_netdev('user')
 
         self.archive_extract(self.ASSET_SDK_V1100_AST2700)
-        self.start_ast2700fc_test('ast2700-a1')
-        self.verify_openbmc_boot_and_login('ast2700-a1')
+        self.start_ast2700fc_test('ast2700-default')
+        self.verify_openbmc_boot_and_login('ast2700-default')
         self.do_ast2700_i2c_test()
         self.do_ast2700_pcie_test()
         self.do_ast2700fc_ssp_test()
@@ -164,8 +164,8 @@ def test_aarch64_ast2700fc_sdk_vbootrom_v11_00(self):
         self.set_machine('ast2700fc')
 
         self.archive_extract(self.ASSET_SDK_V1100_AST2700)
-        self.start_ast2700fc_test_vbootrom('ast2700-a1')
-        self.verify_openbmc_boot_and_login('ast2700-a1')
+        self.start_ast2700fc_test_vbootrom('ast2700-default')
+        self.verify_openbmc_boot_and_login('ast2700-default')
         self.do_ast2700fc_ssp_test()
         self.do_ast2700fc_tsp_test()
 
-- 
2.43.0

Re: [PATCH v1 1/1] tests/functional/aarch64/test_aspeed_ast2700fc: Use AST2700 A2 SDK image for FC tests

[Cédric Le Goater]

On 2/6/26 06:33, Jamin Lin wrote:
> Update AST2700 FC functional tests to use the AST2700 A2 SDK v11.00 image.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   .../functional/aarch64/test_aspeed_ast2700fc.py  | 16 ++++++++--------
>   1 file changed, 8 insertions(+), 8 deletions(-)
> 

This patch is redundant with patch 10. Probably you had an extra
patch file in the directory you used to send the series. I will
ignore it for now but this confuses b4.

C.

Re: [PATCH v1 00/10] Support ASPEED AST2700 A2

[Cédric Le Goater]

Jamin,

On 2/6/26 06:33, Jamin Lin wrote:
> v1
>    1. Add AST2700 A2 SoC support
>    2. Add AST2700 A2 EVB machine
>    3. Alias ast2700-evb to ast2700a2-evb
>    4. Switch AST2700 FC machine to use the A2 SoC
>    5. Update functional tests for both AST2700 A1 and A2
>    6. Fix I2C Fix Out-of-Bounds access issue
> 
> Jamin Lin (10):
>    hw/i2c/aspeed_i2c: Fix Out-of-Bounds access by using dynamic register
>      array
>    hw/i2c/aspeed_i2c: Increase I2C device register size to 0xA0
>    hw/misc/aspeed_scu: Remove unused SoC silicon revision definitions
>    hw/misc/aspeed_scu: Add AST2700 A2 silicon revisions
>    hw/arm/aspeed_ast27x0: Add AST2700 A2 SoC support
>    hw/arm/aspeed_ast27x0_evb: Add AST2700 A2 EVB machine
>    tests/qtest/ast2700-hace-test: Use ast2700-evb alias for AST2700 HACE
>      tests
>    tests/functional/aarch64/test_aspeed_ast2700: Add AST2700 A2 EVB
>      functional tests
>    hw/arm/aspeed_ast27x0-fc: Switch AST2700 FC machine to A2 SoC
>    tests/functional/aarch64/test_aspeed_ast2700fc: Use AST2700 A2 SDK
>      image for FC tests
> 
>   include/hw/i2c/aspeed_i2c.h                   |  4 +-
>   include/hw/misc/aspeed_scu.h                  | 11 +---
>   hw/arm/aspeed_ast27x0-fc.c                    | 15 +++---
>   hw/arm/aspeed_ast27x0.c                       | 36 +++++++++++++
>   hw/arm/aspeed_ast27x0_evb.c                   | 29 +++++++++-
>   hw/i2c/aspeed_i2c.c                           | 54 +++++++++++--------
>   hw/misc/aspeed_scu.c                          | 11 +---
>   tests/qtest/ast2700-hace-test.c               | 22 ++++----
>   .../functional/aarch64/test_aspeed_ast2700.py | 44 +++++++++++++++
>   .../aarch64/test_aspeed_ast2700fc.py          | 16 +++---
>   10 files changed, 169 insertions(+), 73 deletions(-)
> 


It would nice if you could provide a summary of the changes
introduced in the A2 revision compared to the A1. That in
the cover letter and in the commit log of the patch adding
support. We're curious !

Thanks,

C.

Re: [PATCH v1 02/10] hw/i2c/aspeed_i2c: Increase I2C device register size to 0xA0

[Cédric Le Goater]

On 2/6/26 06:33, Jamin Lin wrote:
> According to the AST2700 A1 datasheet, the register space for each I2C
> device instance has been expanded from 0x80 bytes to 0xA0 bytes.

Was that change introduced with the A1 ? or A0 ?

Thanks,

C.


> Update the AST2700 I2C controller configuration to reflect the new
> register layout by increasing the per-device register size to 0xA0
> and adjusting the register gap size accordingly.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   hw/i2c/aspeed_i2c.c | 36 ++++++++++++++++++------------------
>   1 file changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
> index cf3a003978..e1682c9bdd 100644
> --- a/hw/i2c/aspeed_i2c.c
> +++ b/hw/i2c/aspeed_i2c.c
> @@ -1206,37 +1206,37 @@ static void aspeed_i2c_instance_init(Object *obj)
>    *
>    * Address Definitions (AST2700)
>    *   0x000 ... 0x0FF: Global Register
> - *   0x100 ... 0x17F: Device 0
> + *   0x100 ... 0x19F: Device 0
>    *   0x1A0 ... 0x1BF: Device 0 buffer
> - *   0x200 ... 0x27F: Device 1
> + *   0x200 ... 0x29F: Device 1
>    *   0x2A0 ... 0x2BF: Device 1 buffer
> - *   0x300 ... 0x37F: Device 2
> + *   0x300 ... 0x39F: Device 2
>    *   0x3A0 ... 0x3BF: Device 2 buffer
> - *   0x400 ... 0x47F: Device 3
> + *   0x400 ... 0x49F: Device 3
>    *   0x4A0 ... 0x4BF: Device 3 buffer
> - *   0x500 ... 0x57F: Device 4
> + *   0x500 ... 0x59F: Device 4
>    *   0x5A0 ... 0x5BF: Device 4 buffer
> - *   0x600 ... 0x67F: Device 5
> + *   0x600 ... 0x69F: Device 5
>    *   0x6A0 ... 0x6BF: Device 5 buffer
> - *   0x700 ... 0x77F: Device 6
> + *   0x700 ... 0x79F: Device 6
>    *   0x7A0 ... 0x7BF: Device 6 buffer
> - *   0x800 ... 0x87F: Device 7
> + *   0x800 ... 0x89F: Device 7
>    *   0x8A0 ... 0x8BF: Device 7 buffer
> - *   0x900 ... 0x97F: Device 8
> + *   0x900 ... 0x99F: Device 8
>    *   0x9A0 ... 0x9BF: Device 8 buffer
> - *   0xA00 ... 0xA7F: Device 9
> + *   0xA00 ... 0xA9F: Device 9
>    *   0xAA0 ... 0xABF: Device 9 buffer
> - *   0xB00 ... 0xB7F: Device 10
> + *   0xB00 ... 0xB9F: Device 10
>    *   0xBA0 ... 0xBBF: Device 10 buffer
> - *   0xC00 ... 0xC7F: Device 11
> + *   0xC00 ... 0xC9F: Device 11
>    *   0xCA0 ... 0xCBF: Device 11 buffer
> - *   0xD00 ... 0xD7F: Device 12
> + *   0xD00 ... 0xD9F: Device 12
>    *   0xDA0 ... 0xDBF: Device 12 buffer
> - *   0xE00 ... 0xE7F: Device 13
> + *   0xE00 ... 0xE9F: Device 13
>    *   0xEA0 ... 0xEBF: Device 13 buffer
> - *   0xF00 ... 0xF7F: Device 14
> + *   0xF00 ... 0xF9F: Device 14
>    *   0xFA0 ... 0xFBF: Device 14 buffer
> - *   0x1000 ... 0x107F: Device 15
> + *   0x1000 ... 0x109F: Device 15
>    *   0x10A0 ... 0x10BF: Device 15 buffer
>    */
>   static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
> @@ -1670,8 +1670,8 @@ static void aspeed_2700_i2c_class_init(ObjectClass *klass, const void *data)
>       dc->desc = "ASPEED 2700 I2C Controller";
>   
>       aic->num_busses = 16;
> -    aic->reg_size = 0x80;
> -    aic->reg_gap_size = 0x80;
> +    aic->reg_size = 0xa0;
> +    aic->reg_gap_size = 0x60;
>       aic->gap = -1; /* no gap */
>       aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq;
>       aic->pool_size = 0x20;

Re: [PATCH v1 03/10] hw/misc/aspeed_scu: Remove unused SoC silicon revision definitions

[Cédric Le Goater]

On 2/6/26 06:33, Jamin Lin wrote:
> Several legacy Aspeed SoC silicon revision definitions are no longer
> used by any machine models or runtime logic.
> 
> Remove unused silicon revision macros and corresponding entries from
> the silicon revision table to reduce dead code and improve
> maintainability.
> 
> No functional change intended.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   include/hw/misc/aspeed_scu.h | 10 ----------
>   hw/misc/aspeed_scu.c         | 10 ----------
>   2 files changed, 20 deletions(-)
> 
> diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
> index 9e28bd4d2e..313a79f2f7 100644
> --- a/include/hw/misc/aspeed_scu.h
> +++ b/include/hw/misc/aspeed_scu.h
> @@ -41,22 +41,12 @@ struct AspeedSCUState {
>       uint32_t hw_prot_key;
>   };
>   
> -#define AST2400_A0_SILICON_REV   0x02000303U
>   #define AST2400_A1_SILICON_REV   0x02010303U
> -#define AST2500_A0_SILICON_REV   0x04000303U
>   #define AST2500_A1_SILICON_REV   0x04010303U
> -#define AST2600_A0_SILICON_REV   0x05000303U
> -#define AST2600_A1_SILICON_REV   0x05010303U
> -#define AST2600_A2_SILICON_REV   0x05020303U
>   #define AST2600_A3_SILICON_REV   0x05030303U
> -#define AST1030_A0_SILICON_REV   0x80000000U
>   #define AST1030_A1_SILICON_REV   0x80010000U
>   #define AST1060_A2_SILICON_REV   0xA0030000U
> -#define AST2700_A0_SILICON_REV   0x06000103U
> -#define AST2720_A0_SILICON_REV   0x06000203U
> -#define AST2750_A0_SILICON_REV   0x06000003U
>   #define AST2700_A1_SILICON_REV   0x06010103U
> -#define AST2750_A1_SILICON_REV   0x06010003U
>   
>   #define ASPEED_IS_AST2500(si_rev)     ((((si_rev) >> 24) & 0xff) == 0x04)
>   
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index 6829efa2dc..0edf9c1b16 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -555,22 +555,12 @@ static void aspeed_scu_reset(DeviceState *dev)
>   }
>   
>   static uint32_t aspeed_silicon_revs[] = {
> -    AST2400_A0_SILICON_REV,
>       AST2400_A1_SILICON_REV,
> -    AST2500_A0_SILICON_REV,
>       AST2500_A1_SILICON_REV,
> -    AST2600_A0_SILICON_REV,
> -    AST2600_A1_SILICON_REV,
> -    AST2600_A2_SILICON_REV,
>       AST2600_A3_SILICON_REV,
> -    AST1030_A0_SILICON_REV,
>       AST1030_A1_SILICON_REV,
>       AST1060_A2_SILICON_REV,
> -    AST2700_A0_SILICON_REV,
> -    AST2720_A0_SILICON_REV,
> -    AST2750_A0_SILICON_REV,
>       AST2700_A1_SILICON_REV,
> -    AST2750_A1_SILICON_REV,
>   };
>   
>   bool is_supported_silicon_rev(uint32_t silicon_rev)

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.

Re: [PATCH v1 04/10] hw/misc/aspeed_scu: Add AST2700 A2 silicon revisions

[Cédric Le Goater]

On 2/6/26 06:33, Jamin Lin wrote:
> Add silicon revision definitions for AST2700 A2, and include
> them in the list of supported Aspeed silicon revisions.
> 
> This allows newer AST27x0 A2 silicon to be correctly identified via
> the SCU silicon revision register.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   include/hw/misc/aspeed_scu.h | 1 +
>   hw/misc/aspeed_scu.c         | 1 +
>   2 files changed, 2 insertions(+)
> 
> diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
> index 313a79f2f7..d003955428 100644
> --- a/include/hw/misc/aspeed_scu.h
> +++ b/include/hw/misc/aspeed_scu.h
> @@ -47,6 +47,7 @@ struct AspeedSCUState {
>   #define AST1030_A1_SILICON_REV   0x80010000U
>   #define AST1060_A2_SILICON_REV   0xA0030000U
>   #define AST2700_A1_SILICON_REV   0x06010103U
> +#define AST2700_A2_SILICON_REV   0x06020103U
>   
>   #define ASPEED_IS_AST2500(si_rev)     ((((si_rev) >> 24) & 0xff) == 0x04)
>   
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index 0edf9c1b16..e4160356e4 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -561,6 +561,7 @@ static uint32_t aspeed_silicon_revs[] = {
>       AST1030_A1_SILICON_REV,
>       AST1060_A2_SILICON_REV,
>       AST2700_A1_SILICON_REV,
> +    AST2700_A2_SILICON_REV,
>   };
>   
>   bool is_supported_silicon_rev(uint32_t silicon_rev)

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.

RE: [PATCH v1 1/1] tests/functional/aarch64/test_aspeed_ast2700fc: Use AST2700 A2 SDK image for FC tests

[Jamin Lin]

Hi Cédric

> Subject: Re: [PATCH v1 1/1] tests/functional/aarch64/test_aspeed_ast2700fc:
> Use AST2700 A2 SDK image for FC tests
> 
> On 2/6/26 06:33, Jamin Lin wrote:
> > Update AST2700 FC functional tests to use the AST2700 A2 SDK v11.00
> image.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   .../functional/aarch64/test_aspeed_ast2700fc.py  | 16 ++++++++--------
> >   1 file changed, 8 insertions(+), 8 deletions(-)
> >
> 
> This patch is redundant with patch 10. Probably you had an extra patch file in
> the directory you used to send the series. I will ignore it for now but this
> confuses b4.
> 
Thanks for report it.
It is my patch folder issue.
Jamin

jamin_lin@aspeed-fw02:~/qemu-work/debug-qemu-a2/v1-patch$ ls -al
total 64
drwxrwxr-x 2 jamin_lin jamin_lin 4096 Feb  6 11:56 .
drwxrwxr-x 6 jamin_lin jamin_lin 4096 Feb  6 13:38 ..
-rw-rw-r-- 1 jamin_lin jamin_lin 1623 Feb  6 11:56 v1-0000-cover-letter.patch
-rw-rw-r-- 1 jamin_lin jamin_lin 4345 Feb  6 11:59 v1-0001-hw-i2c-aspeed_i2c-Fix-Out-of-Bounds-access-by-usi.patch
-rw-rw-r-- 1 jamin_lin jamin_lin 3315 Feb  6 11:59 v1-0001-tests-functional-aarch64-test_aspeed_ast2700fc-Us.patch
-rw-rw-r-- 1 jamin_lin jamin_lin 3183 Feb  6 11:58 v1-0002-hw-i2c-aspeed_i2c-Increase-I2C-device-register-si.patch
-rw-rw-r-- 1 jamin_lin jamin_lin 2592 Feb  6 11:58 v1-0003-hw-misc-aspeed_scu-Remove-unused-SoC-silicon-revi.patch
-rw-rw-r-- 1 jamin_lin jamin_lin 1496 Feb  6 11:58 v1-0004-hw-misc-aspeed_scu-Add-AST2700-A2-silicon-revisio.patch
-rw-rw-r-- 1 jamin_lin jamin_lin 2537 Feb  6 11:58 v1-0005-hw-arm-aspeed_ast27x0-Add-AST2700-A2-SoC-support.patch
-rw-rw-r-- 1 jamin_lin jamin_lin 2723 Feb  6 11:58 v1-0006-hw-arm-aspeed_ast27x0_evb-Add-AST2700-A2-EVB-mach.patch
-rw-rw-r-- 1 jamin_lin jamin_lin 3334 Feb  6 11:58 v1-0007-tests-qtest-ast2700-hace-test-Use-ast2700-evb-ali.patch
-rw-rw-r-- 1 jamin_lin jamin_lin 4100 Feb  6 11:58 v1-0008-tests-functional-aarch64-test_aspeed_ast2700-Add-.patch
-rw-rw-r-- 1 jamin_lin jamin_lin 2905 Feb  6 11:58 v1-0009-hw-arm-aspeed_ast27x0-fc-Switch-AST2700-FC-machin.patch
-rw-rw-r-- 1 jamin_lin jamin_lin 3317 Feb  6 11:58 v1-0010-tests-functional-aarch64-test_aspeed_ast2700fc-Us.patch
> C.

Re: [PATCH v1 05/10] hw/arm/aspeed_ast27x0: Add AST2700 A2 SoC support

[Cédric Le Goater]

On 2/6/26 06:33, Jamin Lin wrote:
> Introduce a new AST2700 A2 SoC variant by adding a dedicated class
> initialization function.
> 
> This commit sets the A2 silicon revision and defines its SoC
> capabilities, including CPU type, SRAM size, peripheral counts, and
> CPU topology, while reusing the existing IRQ and memory maps.


Could you please briefly document the differences with the A1 ?

Thanks,

C.

> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   hw/arm/aspeed_ast27x0.c | 36 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 36 insertions(+)
> 
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 61790ea1cc..87dcb82e1b 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -1166,6 +1166,36 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
>       sc->memmap       = aspeed_soc_ast2700_memmap;
>   }
>   
> +static void aspeed_soc_ast2700a2_class_init(ObjectClass *oc, const void *data)
> +{
> +    static const char * const valid_cpu_types[] = {
> +        ARM_CPU_TYPE_NAME("cortex-a35"),
> +        NULL
> +    };
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
> +
> +    /* Reason: The Aspeed SoC can only be instantiated from a board */
> +    dc->user_creatable = false;
> +    dc->realize      = aspeed_soc_ast2700_realize;
> +
> +    sc->valid_cpu_types = valid_cpu_types;
> +    sc->silicon_rev  = AST2700_A2_SILICON_REV;
> +    sc->sram_size    = 0x20000;
> +    sc->pcie_num     = 3;
> +    sc->spis_num     = 3;
> +    sc->sgpio_num    = 2;
> +    sc->ehcis_num    = 4;
> +    sc->wdts_num     = 8;
> +    sc->macs_num     = 3;
> +    sc->uarts_num    = 13;
> +    sc->num_cpus     = 4;
> +    sc->ioexp_num    = 2;
> +    sc->uarts_base   = ASPEED_DEV_UART0;
> +    sc->irqmap       = aspeed_soc_ast2700a1_irqmap;
> +    sc->memmap       = aspeed_soc_ast2700_memmap;
> +}
> +
>   static const TypeInfo aspeed_soc_ast27x0_types[] = {
>       {
>           .name           = TYPE_ASPEED27X0_SOC,
> @@ -1179,6 +1209,12 @@ static const TypeInfo aspeed_soc_ast27x0_types[] = {
>           .instance_init  = aspeed_soc_ast2700_init,
>           .class_init     = aspeed_soc_ast2700a1_class_init,
>       },
> +    {
> +        .name           = "ast2700-a2",
> +        .parent         = TYPE_ASPEED27X0_SOC,
> +        .instance_init  = aspeed_soc_ast2700_init,
> +        .class_init     = aspeed_soc_ast2700a2_class_init,
> +    },
>   };
>   
>   DEFINE_TYPES(aspeed_soc_ast27x0_types)

Re: [PATCH v1 06/10] hw/arm/aspeed_ast27x0_evb: Add AST2700 A2 EVB machine

[Cédric Le Goater]

On 2/6/26 06:33, Jamin Lin wrote:
> Add a new AST2700 A2 EVB machine to model the newer A2 silicon.
> 
> The "ast2700-evb" machine alias is moved to the AST2700 A2 EVB, making
> it the default AST2700 evaluation board. The existing AST2700 A1 EVB
> machine remains available as "ast2700a1-evb".
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   hw/arm/aspeed_ast27x0_evb.c | 29 ++++++++++++++++++++++++++++-
>   1 file changed, 28 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c
> index 31f7d61117..0ff1bebeb0 100644
> --- a/hw/arm/aspeed_ast27x0_evb.c
> +++ b/hw/arm/aspeed_ast27x0_evb.c
> @@ -34,7 +34,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
>       MachineClass *mc = MACHINE_CLASS(oc);
>       AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
>   
> -    mc->alias = "ast2700-evb";

Please change the machine alias in a separate patch.

Thanks,

C.


>       mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)";
>       amc->soc_name  = "ast2700-a1";
>       amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
> @@ -50,12 +49,40 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
>       aspeed_machine_class_init_cpus_defaults(mc);
>   }
>   
> +static void aspeed_machine_ast2700a2_evb_class_init(ObjectClass *oc,
> +                                                    const void *data)
> +{
> +    MachineClass *mc = MACHINE_CLASS(oc);
> +    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> +
> +    mc->alias = "ast2700-evb";
> +    mc->desc = "Aspeed AST2700 A2 EVB (Cortex-A35)";
> +    amc->soc_name  = "ast2700-a2";
> +    amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
> +    amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
> +    amc->fmc_model = "w25q01jvq";
> +    amc->spi_model = "w25q512jv";
> +    amc->num_cs    = 2;
> +    amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
> +    amc->uart_default = ASPEED_DEV_UART12;
> +    amc->i2c_init  = ast2700_evb_i2c_init;
> +    amc->vbootrom = true;
> +    mc->default_ram_size = 2 * GiB;
> +    aspeed_machine_class_init_cpus_defaults(mc);
> +}
> +
>   static const TypeInfo aspeed_ast27x0_evb_types[] = {
>       {
>           .name          = MACHINE_TYPE_NAME("ast2700a1-evb"),
>           .parent        = TYPE_ASPEED_MACHINE,
>           .class_init    = aspeed_machine_ast2700a1_evb_class_init,
>           .interfaces    = aarch64_machine_interfaces,
> +    },
> +    {
> +        .name          = MACHINE_TYPE_NAME("ast2700a2-evb"),
> +        .parent        = TYPE_ASPEED_MACHINE,
> +        .class_init    = aspeed_machine_ast2700a2_evb_class_init,
> +        .interfaces    = aarch64_machine_interfaces,
>       }
>   };
>   

Re: [PATCH v1 07/10] tests/qtest/ast2700-hace-test: Use ast2700-evb alias for AST2700 HACE tests

[Cédric Le Goater]

On 2/6/26 06:33, Jamin Lin wrote:
> Update AST2700 HACE qtests to use the "ast2700-evb" machine alias
> instead of a specific silicon revision.
> 
> The AST2700 A1 and A2 revisions are compatible for the HACE model, so
> the tests do not depend on a particular EVB revision. Using the
> "ast2700-evb" alias ensures the tests always run the latest
> supported AST2700 silicon revision.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.


> ---
>   tests/qtest/ast2700-hace-test.c | 22 +++++++++++-----------
>   1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/tests/qtest/ast2700-hace-test.c b/tests/qtest/ast2700-hace-test.c
> index a400e2962b..508a34dd6c 100644
> --- a/tests/qtest/ast2700-hace-test.c
> +++ b/tests/qtest/ast2700-hace-test.c
> @@ -23,57 +23,57 @@ static const struct AspeedMasks as2700_masks = {
>   /* ast2700 */
>   static void test_md5_ast2700(void)
>   {
> -    aspeed_test_md5("-machine ast2700a1-evb", 0x12070000, 0x400000000);
> +    aspeed_test_md5("-machine ast2700-evb", 0x12070000, 0x400000000);
>   }
>   
>   static void test_sha256_ast2700(void)
>   {
> -    aspeed_test_sha256("-machine ast2700a1-evb", 0x12070000, 0x400000000);
> +    aspeed_test_sha256("-machine ast2700-evb", 0x12070000, 0x400000000);
>   }
>   
>   static void test_sha256_sg_ast2700(void)
>   {
> -    aspeed_test_sha256_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000);
> +    aspeed_test_sha256_sg("-machine ast2700-evb", 0x12070000, 0x400000000);
>   }
>   
>   static void test_sha384_ast2700(void)
>   {
> -    aspeed_test_sha384("-machine ast2700a1-evb", 0x12070000, 0x400000000);
> +    aspeed_test_sha384("-machine ast2700-evb", 0x12070000, 0x400000000);
>   }
>   
>   static void test_sha384_sg_ast2700(void)
>   {
> -    aspeed_test_sha384_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000);
> +    aspeed_test_sha384_sg("-machine ast2700-evb", 0x12070000, 0x400000000);
>   }
>   
>   static void test_sha512_ast2700(void)
>   {
> -    aspeed_test_sha512("-machine ast2700a1-evb", 0x12070000, 0x400000000);
> +    aspeed_test_sha512("-machine ast2700-evb", 0x12070000, 0x400000000);
>   }
>   
>   static void test_sha512_sg_ast2700(void)
>   {
> -    aspeed_test_sha512_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000);
> +    aspeed_test_sha512_sg("-machine ast2700-evb", 0x12070000, 0x400000000);
>   }
>   
>   static void test_sha256_accum_ast2700(void)
>   {
> -    aspeed_test_sha256_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000);
> +    aspeed_test_sha256_accum("-machine ast2700-evb", 0x12070000, 0x400000000);
>   }
>   
>   static void test_sha384_accum_ast2700(void)
>   {
> -    aspeed_test_sha384_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000);
> +    aspeed_test_sha384_accum("-machine ast2700-evb", 0x12070000, 0x400000000);
>   }
>   
>   static void test_sha512_accum_ast2700(void)
>   {
> -    aspeed_test_sha512_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000);
> +    aspeed_test_sha512_accum("-machine ast2700-evb", 0x12070000, 0x400000000);
>   }
>   
>   static void test_addresses_ast2700(void)
>   {
> -    aspeed_test_addresses("-machine ast2700a1-evb", 0x12070000, &as2700_masks);
> +    aspeed_test_addresses("-machine ast2700-evb", 0x12070000, &as2700_masks);
>   }
>   
>   int main(int argc, char **argv)

Re: [PATCH v1 09/10] hw/arm/aspeed_ast27x0-fc: Switch AST2700 FC machine to A2 SoC

[Cédric Le Goater]

On 2/6/26 06:33, Jamin Lin wrote:
> Update the AST2700 FC machine to use the AST2700 A2 SoC model instead of
> the A1-specific variant.
> 
> This change removes A1-specific naming and definitions from the FC
> machine and aligns it with the newer AST2700 A2 silicon.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   hw/arm/aspeed_ast27x0-fc.c | 15 +++++++--------
>   1 file changed, 7 insertions(+), 8 deletions(-)
> 
> diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
> index 0502a137f3..5eb6680da9 100644
> --- a/hw/arm/aspeed_ast27x0-fc.c
> +++ b/hw/arm/aspeed_ast27x0-fc.c
> @@ -24,8 +24,8 @@
>   #include "hw/arm/aspeed_coprocessor.h"
>   #include "hw/arm/machines-qom.h"
>   
> -#define TYPE_AST2700A1FC MACHINE_TYPE_NAME("ast2700fc")
> -OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700A1FC);
> +#define TYPE_AST2700FC MACHINE_TYPE_NAME("ast2700fc")
> +OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700FC);
>   
>   static struct arm_boot_info ast2700fc_board_info = {
>       .board_id = -1, /* device-tree-only board */
> @@ -48,8 +48,7 @@ struct Ast2700FCState {
>       Aspeed27x0CoprocessorState tsp;
>   };
>   
> -#define AST2700FC_BMC_RAM_SIZE (1 * GiB)
> -#define AST2700FC_CM4_DRAM_SIZE (32 * MiB)
> +#define AST2700FC_BMC_RAM_SIZE (2 * GiB)


This is an unrelated change.

Thanks,

C.

>   #define AST2700FC_HW_STRAP1 0x000000C0
>   #define AST2700FC_HW_STRAP2 0x00000003
> @@ -58,7 +57,7 @@ struct Ast2700FCState {
>   
>   static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
>   {
> -    Ast2700FCState *s = AST2700A1FC(machine);
> +    Ast2700FCState *s = AST2700FC(machine);
>       AspeedSoCState *soc;
>       AspeedSoCClass *sc;
>       const char *bios_name = NULL;
> @@ -66,7 +65,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
>       DeviceState *dev = NULL;
>       uint64_t rom_size;
>   
> -    object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1");
> +    object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a2");
>       soc = ASPEED_SOC(&s->ca35);
>       sc = ASPEED_SOC_GET_CLASS(soc);
>   
> @@ -135,7 +134,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
>   
>   static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
>   {
> -    Ast2700FCState *s = AST2700A1FC(machine);
> +    Ast2700FCState *s = AST2700FC(machine);
>       AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
>   
>       s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
> @@ -167,7 +166,7 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
>   
>   static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
>   {
> -    Ast2700FCState *s = AST2700A1FC(machine);
> +    Ast2700FCState *s = AST2700FC(machine);
>       AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
>   
>       s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");

Re: [PATCH v1 10/10] tests/functional/aarch64/test_aspeed_ast2700fc: Use AST2700 A2 SDK image for FC tests

[Cédric Le Goater]

On 2/6/26 06:33, Jamin Lin wrote:
> Update AST2700 FC functional tests to use the AST2700 A2 SDK v11.00 image.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   .../functional/aarch64/test_aspeed_ast2700fc.py  | 16 ++++++++--------
>   1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
> index 47e56dcfc5..51ee8bc787 100755
> --- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
> +++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
> @@ -62,8 +62,8 @@ def load_ast2700fc_coprocessor(self, name):
>                                f'loader,file={file},cpu-num={cpu_num}')
>   
>       ASSET_SDK_V1100_AST2700 = Asset(
> -            'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-obmc.tar.gz',
> -            'd5ceed511cd0dfefbb102fff2d731159e0472948a28066dc0d90bcd54be76525')
> +            'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-default-obmc.tar.gz',
> +            'e2b8f043fe8063dd3b6ded93422e38bd41914dc9c3202199507652df024de4dc')
>   
>       def do_ast2700_i2c_test(self):
>           exec_command_and_wait_for_pattern(self,
> @@ -98,7 +98,7 @@ def do_ast2700fc_ssp_test(self):
>           exec_command_and_wait_for_pattern(self, 'version',
>                                             'Zephyr version 3.7.1')
>           exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
> -                                          '[72c02000] 06010103')
> +                                          '[72c02000] 06020103')
>   
>       def do_ast2700fc_tsp_test(self):
>           self.vm.shutdown()
> @@ -109,7 +109,7 @@ def do_ast2700fc_tsp_test(self):
>           exec_command_and_wait_for_pattern(self, 'version',
>                                             'Zephyr version 3.7.1')
>           exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
> -                                          '[72c02000] 06010103')
> +                                          '[72c02000] 06020103')
>   
>       def start_ast2700fc_test(self, name):
>           ca35_core = 4
> @@ -153,8 +153,8 @@ def test_aarch64_ast2700fc_sdk_v11_00(self):
>           self.require_netdev('user')
>   
>           self.archive_extract(self.ASSET_SDK_V1100_AST2700)
> -        self.start_ast2700fc_test('ast2700-a1')
> -        self.verify_openbmc_boot_and_login('ast2700-a1')
> +        self.start_ast2700fc_test('ast2700-default')
> +        self.verify_openbmc_boot_and_login('ast2700-default')
>           self.do_ast2700_i2c_test()
>           self.do_ast2700_pcie_test()
>           self.do_ast2700fc_ssp_test()
> @@ -164,8 +164,8 @@ def test_aarch64_ast2700fc_sdk_vbootrom_v11_00(self):
>           self.set_machine('ast2700fc')
>   
>           self.archive_extract(self.ASSET_SDK_V1100_AST2700)
> -        self.start_ast2700fc_test_vbootrom('ast2700-a1')
> -        self.verify_openbmc_boot_and_login('ast2700-a1')
> +        self.start_ast2700fc_test_vbootrom('ast2700-default')
> +        self.verify_openbmc_boot_and_login('ast2700-default')
>           self.do_ast2700fc_ssp_test()
>           self.do_ast2700fc_tsp_test()
>   

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.

Re: [PATCH v1 08/10] tests/functional/aarch64/test_aspeed_ast2700: Add AST2700 A2 EVB functional tests

[Cédric Le Goater]

+ Thomas

On 2/6/26 06:33, Jamin Lin wrote:
> Add functional coverage for the AST2700 A2 EVB machine by introducing
> test cases that boot and validate an OpenBMC SDK v11.00 image on
> "ast2700a2-evb".

I wonder if we need to test both machines. The test is already quite long.

On my test system :

   qemu:func-aarch64-aspeed_ast2700             OK              119.68s   3 subtests passed

With both machines :

   qemu:func-aarch64-aspeed_ast2700             OK              219.79s   6 subtests passed

Thanks,

C.


> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   .../functional/aarch64/test_aspeed_ast2700.py | 44 +++++++++++++++++++
>   1 file changed, 44 insertions(+)
> 
> diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functional/aarch64/test_aspeed_ast2700.py
> index 61373ffe5b..68e930ab72 100755
> --- a/tests/functional/aarch64/test_aspeed_ast2700.py
> +++ b/tests/functional/aarch64/test_aspeed_ast2700.py
> @@ -86,6 +86,14 @@ def verify_openbmc_boot_and_login(self, name, enable_pcie=True):
>               'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-dcscm-obmc.tar.gz',
>               '4f8778be176ece1b57d33c4aee13bb989be114c3e4703150eaeb6f996bd5587f')
>   
> +    ASSET_SDK_V1100_AST2700A2 = Asset(
> +            'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-default-obmc.tar.gz',
> +            'e2b8f043fe8063dd3b6ded93422e38bd41914dc9c3202199507652df024de4dc')
> +
> +    ASSET_SDK_V1100_AST2700A2_DCSCM = Asset(
> +            'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-dcscm-obmc.tar.gz',
> +            '0e93f7976139da71fab9df7952a58bdd80650e23e7abf5853b0eb6695deb02d0')
> +
>       def do_ast2700_i2c_test(self, bus_id):
>           bus_str = str(bus_id)
>           exec_command_and_wait_for_pattern(self,
> @@ -159,6 +167,18 @@ def test_aarch64_ast2700a1_evb_sdk_v11_00(self):
>           self.do_ast2700_i2c_test(1)
>           self.do_ast2700_pcie_test()
>   
> +    def test_aarch64_ast2700a2_evb_sdk_v11_00(self):
> +        self.set_machine('ast2700a2-evb')
> +        self.require_netdev('user')
> +
> +        self.archive_extract(self.ASSET_SDK_V1100_AST2700A2)
> +        self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
> +        self.vm.add_args('-netdev', 'user,id=net1')
> +        self.start_ast2700_test('ast2700-default', 1)
> +        self.verify_openbmc_boot_and_login('ast2700-default')
> +        self.do_ast2700_i2c_test(1)
> +        self.do_ast2700_pcie_test()
> +
>       def test_aarch64_ast2700a1_evb_sdk_vbootrom_v11_00(self):
>           self.set_machine('ast2700a1-evb')
>           self.require_netdev('user')
> @@ -170,6 +190,17 @@ def test_aarch64_ast2700a1_evb_sdk_vbootrom_v11_00(self):
>           self.verify_vbootrom_firmware_flow()
>           self.verify_openbmc_boot_start()
>   
> +    def test_aarch64_ast2700a2_evb_sdk_vbootrom_v11_00(self):
> +        self.set_machine('ast2700a2-evb')
> +        self.require_netdev('user')
> +
> +        self.archive_extract(self.ASSET_SDK_V1100_AST2700A2)
> +        self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
> +        self.vm.add_args('-netdev', 'user,id=net1')
> +        self.start_ast2700_test_vbootrom('ast2700-default', 1)
> +        self.verify_vbootrom_firmware_flow()
> +        self.verify_openbmc_boot_start()
> +
>       def test_aarch64_ast2700a1_evb_ioexp_v11_00(self):
>           self.set_machine('ast2700a1-evb')
>           self.require_netdev('user')
> @@ -183,5 +214,18 @@ def test_aarch64_ast2700a1_evb_ioexp_v11_00(self):
>           self.do_ast2700_i2c_test(8)
>           self.do_ast2700_i2c_test(16)
>   
> +    def test_aarch64_ast2700a2_evb_ioexp_v11_00(self):
> +        self.set_machine('ast2700a2-evb')
> +        self.require_netdev('user')
> +
> +        self.archive_extract(self.ASSET_SDK_V1100_AST2700A2_DCSCM)
> +        self.vm.set_machine('ast2700a2-evb,fmc-model=w25q512jv')
> +        self.vm.add_args('-device',
> +                         'tmp105,bus=ioexp0.0,address=0x4d,id=tmp-test-16')
> +        self.start_ast2700_test('ast2700-dcscm', 8)
> +        self.verify_openbmc_boot_and_login('ast2700-dcscm', False)
> +        self.do_ast2700_i2c_test(8)
> +        self.do_ast2700_i2c_test(16)
> +
>   if __name__ == '__main__':
>       QemuSystemTest.main()

Re: [PATCH v1 01/10] hw/i2c/aspeed_i2c: Fix Out-of-Bounds access by using dynamic register array

[Cédric Le Goater]

On 2/6/26 06:33, Jamin Lin wrote:
> The ASPEED I2C controller emulation used a fixed-size register array
> (28 dwords) for all SoC variants, while multiple ASPEED SoCs
> (AST2600, AST1030, AST2700) expose a larger MMIO register window
> (e.g. reg_size = 0x80).
> 
> This mismatch allows MMIO accesses beyond the allocated register
> array, leading to out-of-bounds reads in the I2C controller model.
> 
> Fix this by converting the register storage to a dynamically allocated
> array sized according to the controller class reg_size. The register
> array is now allocated during bus realize and free on unrealize,
> ensuring safe access across different ASPEED SoC implementations.
> 
> This change eliminates I2C register out-of-bounds access caused by
> SoC-specific register size differences.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3290

Please keep this patch separate from the A2 series.

> ---
>   include/hw/i2c/aspeed_i2c.h |  4 +---
>   hw/i2c/aspeed_i2c.c         | 18 ++++++++++++++----
>   2 files changed, 15 insertions(+), 7 deletions(-)
> 
> diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
> index 68bd138026..205f0a58d2 100644
> --- a/include/hw/i2c/aspeed_i2c.h
> +++ b/include/hw/i2c/aspeed_i2c.h
> @@ -36,8 +36,6 @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
>   #define ASPEED_I2C_NR_BUSSES 16
>   #define ASPEED_I2C_SHARE_POOL_SIZE 0x800
>   #define ASPEED_I2C_BUS_POOL_SIZE 0x20
> -#define ASPEED_I2C_OLD_NUM_REG 11
> -#define ASPEED_I2C_NEW_NUM_REG 28
>   
>   #define A_I2CD_M_STOP_CMD       BIT(5)
>   #define A_I2CD_M_RX_CMD         BIT(3)
> @@ -256,7 +254,7 @@ struct AspeedI2CBus {
>       uint8_t id;
>       qemu_irq irq;
>   
> -    uint32_t regs[ASPEED_I2C_NEW_NUM_REG];
> +    uint32_t *regs;
>       uint8_t pool[ASPEED_I2C_BUS_POOL_SIZE];
>       uint64_t dma_dram_offset;
>   };
> diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
> index fb3d6a5600..cf3a003978 100644
> --- a/hw/i2c/aspeed_i2c.c
> +++ b/hw/i2c/aspeed_i2c.c
> @@ -1091,10 +1091,9 @@ static const MemoryRegionOps aspeed_i2c_bus_pool_ops = {
>   
>   static const VMStateDescription aspeed_i2c_bus_vmstate = {
>       .name = TYPE_ASPEED_I2C,
> -    .version_id = 6,
> -    .minimum_version_id = 6,
> +    .version_id = 7,
> +    .minimum_version_id = 7,
>       .fields = (const VMStateField[]) {
> -        VMSTATE_UINT32_ARRAY(regs, AspeedI2CBus, ASPEED_I2C_NEW_NUM_REG),

hmm, why not use VMSTATE_VARRAY_UINT32 ?

>           VMSTATE_UINT8_ARRAY(pool, AspeedI2CBus, ASPEED_I2C_BUS_POOL_SIZE),
>           VMSTATE_UINT64(dma_dram_offset, AspeedI2CBus),
>           VMSTATE_END_OF_LIST()
> @@ -1465,8 +1464,9 @@ static const TypeInfo aspeed_i2c_bus_slave_info = {
>   static void aspeed_i2c_bus_reset(DeviceState *dev)
>   {
>       AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
> +    AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s->controller);
>   
> -    memset(s->regs, 0, sizeof(s->regs));
> +    memset(s->regs, 0, aic->reg_size);
>       i2c_end_transfer(s->bus);
>   }
>   
> @@ -1492,6 +1492,7 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp)
>       s->slave = i2c_slave_create_simple(s->bus, TYPE_ASPEED_I2C_BUS_SLAVE,
>                                          0xff);
>   
> +    s->regs = g_new(uint32_t, aic->reg_size >> 2);

g_new0 ? even if the memset in reset will set regs[] contents to 0.

>       memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i2c_bus_ops,
>                             s, s->name, aic->reg_size);
>       sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr);
> @@ -1501,6 +1502,14 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp)
>       sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr_pool);
>   }
>   
> +static void aspeed_i2c_bus_unrealize(DeviceState *dev)
> +{
> +    AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
> +
> +    g_free(s->regs);
> +    s->regs = NULL;
> +}
> +
>   static const Property aspeed_i2c_bus_properties[] = {
>       DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0),
>       DEFINE_PROP_LINK("controller", AspeedI2CBus, controller, TYPE_ASPEED_I2C,
> @@ -1514,6 +1523,7 @@ static void aspeed_i2c_bus_class_init(ObjectClass *klass, const void *data)
>   
>       dc->desc = "Aspeed I2C Bus";
>       dc->realize = aspeed_i2c_bus_realize;
> +    dc->unrealize = aspeed_i2c_bus_unrealize;
>       device_class_set_legacy_reset(dc, aspeed_i2c_bus_reset);
>       device_class_set_props(dc, aspeed_i2c_bus_properties);
>   }

Re: [PATCH v1 08/10] tests/functional/aarch64/test_aspeed_ast2700: Add AST2700 A2 EVB functional tests

[Thomas Huth]

On 06/02/2026 11.11, Cédric Le Goater wrote:
> + Thomas
> 
> On 2/6/26 06:33, Jamin Lin wrote:
>> Add functional coverage for the AST2700 A2 EVB machine by introducing
>> test cases that boot and validate an OpenBMC SDK v11.00 image on
>> "ast2700a2-evb".
> 
> I wonder if we need to test both machines. The test is already quite long.
> 
> On my test system :
> 
>    qemu:func-aarch64-aspeed_ast2700             OK              119.68s   3 
> subtests passed
> 
> With both machines :
> 
>    qemu:func-aarch64-aspeed_ast2700             OK              219.79s   6 
> subtests passed

If the machines are very similar, it's maybe better to mark one of the tests 
with a decorator (skipSlowTest maybe), so we don't have to execute it by 
default, but we still have the test around if we need it.

  Thomas

Re: [PATCH v1 08/10] tests/functional/aarch64/test_aspeed_ast2700: Add AST2700 A2 EVB functional tests

[Peter Maydell]

On Fri, 6 Feb 2026 at 10:40, Thomas Huth <thuth@redhat.com> wrote:
>
> On 06/02/2026 11.11, Cédric Le Goater wrote:
> > + Thomas
> >
> > On 2/6/26 06:33, Jamin Lin wrote:
> >> Add functional coverage for the AST2700 A2 EVB machine by introducing
> >> test cases that boot and validate an OpenBMC SDK v11.00 image on
> >> "ast2700a2-evb".
> >
> > I wonder if we need to test both machines. The test is already quite long.
> >
> > On my test system :
> >
> >    qemu:func-aarch64-aspeed_ast2700             OK              119.68s   3
> > subtests passed
> >
> > With both machines :
> >
> >    qemu:func-aarch64-aspeed_ast2700             OK              219.79s   6
> > subtests passed
>
> If the machines are very similar, it's maybe better to mark one of the tests
> with a decorator (skipSlowTest maybe), so we don't have to execute it by
> default, but we still have the test around if we need it.


It might also be nice to have them be a separate top level test,
so that the tests can be run in parallel. AIUI having 1 test
with 6 subtests forces all 6 to run in sequence, whereas with
2 tests and 3 subtests each you can at least use 2 host CPUs.
Or does the qtest subtest handling include parallelism?

-- PMM

Re: [PATCH v1 08/10] tests/functional/aarch64/test_aspeed_ast2700: Add AST2700 A2 EVB functional tests

[Thomas Huth]

On 06/02/2026 12.33, Peter Maydell wrote:
> On Fri, 6 Feb 2026 at 10:40, Thomas Huth <thuth@redhat.com> wrote:
>>
>> On 06/02/2026 11.11, Cédric Le Goater wrote:
>>> + Thomas
>>>
>>> On 2/6/26 06:33, Jamin Lin wrote:
>>>> Add functional coverage for the AST2700 A2 EVB machine by introducing
>>>> test cases that boot and validate an OpenBMC SDK v11.00 image on
>>>> "ast2700a2-evb".
>>>
>>> I wonder if we need to test both machines. The test is already quite long.
>>>
>>> On my test system :
>>>
>>>     qemu:func-aarch64-aspeed_ast2700             OK              119.68s   3
>>> subtests passed
>>>
>>> With both machines :
>>>
>>>     qemu:func-aarch64-aspeed_ast2700             OK              219.79s   6
>>> subtests passed
>>
>> If the machines are very similar, it's maybe better to mark one of the tests
>> with a decorator (skipSlowTest maybe), so we don't have to execute it by
>> default, but we still have the test around if we need it.
> 
> 
> It might also be nice to have them be a separate top level test,
> so that the tests can be run in parallel. AIUI having 1 test
> with 6 subtests forces all 6 to run in sequence, whereas with
> 2 tests and 3 subtests each you can at least use 2 host CPUs.
> Or does the qtest subtest handling include parallelism?

No, there is no parallel execution for subtests, in neither the qtest nor 
the functional testing framework. So yes, if you want to execute this in 
parallel, put it into separate files.

  Thomas

RE: [PATCH v1 01/10] hw/i2c/aspeed_i2c: Fix Out-of-Bounds access by using dynamic register array

[Jamin Lin]

Hi Cédric

> Subject: Re: [PATCH v1 01/10] hw/i2c/aspeed_i2c: Fix Out-of-Bounds access by
> using dynamic register array
> 
> On 2/6/26 06:33, Jamin Lin wrote:
> > The ASPEED I2C controller emulation used a fixed-size register array
> > (28 dwords) for all SoC variants, while multiple ASPEED SoCs (AST2600,
> > AST1030, AST2700) expose a larger MMIO register window (e.g. reg_size
> > = 0x80).
> >
> > This mismatch allows MMIO accesses beyond the allocated register
> > array, leading to out-of-bounds reads in the I2C controller model.
> >
> > Fix this by converting the register storage to a dynamically allocated
> > array sized according to the controller class reg_size. The register
> > array is now allocated during bus realize and free on unrealize,
> > ensuring safe access across different ASPEED SoC implementations.
> >
> > This change eliminates I2C register out-of-bounds access caused by
> > SoC-specific register size differences.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3290
> 
> Please keep this patch separate from the A2 series.
Thanks for the review.
Will resend

Thanks-Jamin

> 
> > ---
> >   include/hw/i2c/aspeed_i2c.h |  4 +---
> >   hw/i2c/aspeed_i2c.c         | 18 ++++++++++++++----
> >   2 files changed, 15 insertions(+), 7 deletions(-)
> >
> > diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
> > index 68bd138026..205f0a58d2 100644
> > --- a/include/hw/i2c/aspeed_i2c.h
> > +++ b/include/hw/i2c/aspeed_i2c.h
> > @@ -36,8 +36,6 @@ OBJECT_DECLARE_TYPE(AspeedI2CState,
> AspeedI2CClass, ASPEED_I2C)
> >   #define ASPEED_I2C_NR_BUSSES 16
> >   #define ASPEED_I2C_SHARE_POOL_SIZE 0x800
> >   #define ASPEED_I2C_BUS_POOL_SIZE 0x20 -#define
> > ASPEED_I2C_OLD_NUM_REG 11 -#define ASPEED_I2C_NEW_NUM_REG 28
> >
> >   #define A_I2CD_M_STOP_CMD       BIT(5)
> >   #define A_I2CD_M_RX_CMD         BIT(3)
> > @@ -256,7 +254,7 @@ struct AspeedI2CBus {
> >       uint8_t id;
> >       qemu_irq irq;
> >
> > -    uint32_t regs[ASPEED_I2C_NEW_NUM_REG];
> > +    uint32_t *regs;
> >       uint8_t pool[ASPEED_I2C_BUS_POOL_SIZE];
> >       uint64_t dma_dram_offset;
> >   };
> > diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index
> > fb3d6a5600..cf3a003978 100644
> > --- a/hw/i2c/aspeed_i2c.c
> > +++ b/hw/i2c/aspeed_i2c.c
> > @@ -1091,10 +1091,9 @@ static const MemoryRegionOps
> > aspeed_i2c_bus_pool_ops = {
> >
> >   static const VMStateDescription aspeed_i2c_bus_vmstate = {
> >       .name = TYPE_ASPEED_I2C,
> > -    .version_id = 6,
> > -    .minimum_version_id = 6,
> > +    .version_id = 7,
> > +    .minimum_version_id = 7,
> >       .fields = (const VMStateField[]) {
> > -        VMSTATE_UINT32_ARRAY(regs, AspeedI2CBus,
> ASPEED_I2C_NEW_NUM_REG),
> 
> hmm, why not use VMSTATE_VARRAY_UINT32 ?
> 
> >           VMSTATE_UINT8_ARRAY(pool, AspeedI2CBus,
> ASPEED_I2C_BUS_POOL_SIZE),
> >           VMSTATE_UINT64(dma_dram_offset, AspeedI2CBus),
> >           VMSTATE_END_OF_LIST()
> > @@ -1465,8 +1464,9 @@ static const TypeInfo aspeed_i2c_bus_slave_info =
> {
> >   static void aspeed_i2c_bus_reset(DeviceState *dev)
> >   {
> >       AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
> > +    AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s->controller);
> >
> > -    memset(s->regs, 0, sizeof(s->regs));
> > +    memset(s->regs, 0, aic->reg_size);
> >       i2c_end_transfer(s->bus);
> >   }
> >
> > @@ -1492,6 +1492,7 @@ static void aspeed_i2c_bus_realize(DeviceState
> *dev, Error **errp)
> >       s->slave = i2c_slave_create_simple(s->bus,
> TYPE_ASPEED_I2C_BUS_SLAVE,
> >                                          0xff);
> >
> > +    s->regs = g_new(uint32_t, aic->reg_size >> 2);
> 
> g_new0 ? even if the memset in reset will set regs[] contents to 0.
> 
> >       memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i2c_bus_ops,
> >                             s, s->name, aic->reg_size);
> >       sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); @@ -1501,6
> > +1502,14 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error
> **errp)
> >       sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr_pool);
> >   }
> >
> > +static void aspeed_i2c_bus_unrealize(DeviceState *dev) {
> > +    AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
> > +
> > +    g_free(s->regs);
> > +    s->regs = NULL;
> > +}
> > +
> >   static const Property aspeed_i2c_bus_properties[] = {
> >       DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0),
> >       DEFINE_PROP_LINK("controller", AspeedI2CBus, controller,
> > TYPE_ASPEED_I2C, @@ -1514,6 +1523,7 @@ static void
> > aspeed_i2c_bus_class_init(ObjectClass *klass, const void *data)
> >
> >       dc->desc = "Aspeed I2C Bus";
> >       dc->realize = aspeed_i2c_bus_realize;
> > +    dc->unrealize = aspeed_i2c_bus_unrealize;
> >       device_class_set_legacy_reset(dc, aspeed_i2c_bus_reset);
> >       device_class_set_props(dc, aspeed_i2c_bus_properties);
> >   }

RE: [PATCH v1 02/10] hw/i2c/aspeed_i2c: Increase I2C device register size to 0xA0

[Jamin Lin]

Hi Cédric

> Subject: Re: [PATCH v1 02/10] hw/i2c/aspeed_i2c: Increase I2C device register
> size to 0xA0
> 
> On 2/6/26 06:33, Jamin Lin wrote:
> > According to the AST2700 A1 datasheet, the register space for each I2C
> > device instance has been expanded from 0x80 bytes to 0xA0 bytes.
> 
> Was that change introduced with the A1 ? or A0 ?
> 

The change was introduced in A1.
Both A1 and A2 use the same device register size of 0xA0.

Thanks,
Jamin

> Thanks,
> 
> C.
> 
> 
> > Update the AST2700 I2C controller configuration to reflect the new
> > register layout by increasing the per-device register size to 0xA0 and
> > adjusting the register gap size accordingly.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   hw/i2c/aspeed_i2c.c | 36 ++++++++++++++++++------------------
> >   1 file changed, 18 insertions(+), 18 deletions(-)
> >
> > diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index
> > cf3a003978..e1682c9bdd 100644
> > --- a/hw/i2c/aspeed_i2c.c
> > +++ b/hw/i2c/aspeed_i2c.c
> > @@ -1206,37 +1206,37 @@ static void aspeed_i2c_instance_init(Object
> *obj)
> >    *
> >    * Address Definitions (AST2700)
> >    *   0x000 ... 0x0FF: Global Register
> > - *   0x100 ... 0x17F: Device 0
> > + *   0x100 ... 0x19F: Device 0
> >    *   0x1A0 ... 0x1BF: Device 0 buffer
> > - *   0x200 ... 0x27F: Device 1
> > + *   0x200 ... 0x29F: Device 1
> >    *   0x2A0 ... 0x2BF: Device 1 buffer
> > - *   0x300 ... 0x37F: Device 2
> > + *   0x300 ... 0x39F: Device 2
> >    *   0x3A0 ... 0x3BF: Device 2 buffer
> > - *   0x400 ... 0x47F: Device 3
> > + *   0x400 ... 0x49F: Device 3
> >    *   0x4A0 ... 0x4BF: Device 3 buffer
> > - *   0x500 ... 0x57F: Device 4
> > + *   0x500 ... 0x59F: Device 4
> >    *   0x5A0 ... 0x5BF: Device 4 buffer
> > - *   0x600 ... 0x67F: Device 5
> > + *   0x600 ... 0x69F: Device 5
> >    *   0x6A0 ... 0x6BF: Device 5 buffer
> > - *   0x700 ... 0x77F: Device 6
> > + *   0x700 ... 0x79F: Device 6
> >    *   0x7A0 ... 0x7BF: Device 6 buffer
> > - *   0x800 ... 0x87F: Device 7
> > + *   0x800 ... 0x89F: Device 7
> >    *   0x8A0 ... 0x8BF: Device 7 buffer
> > - *   0x900 ... 0x97F: Device 8
> > + *   0x900 ... 0x99F: Device 8
> >    *   0x9A0 ... 0x9BF: Device 8 buffer
> > - *   0xA00 ... 0xA7F: Device 9
> > + *   0xA00 ... 0xA9F: Device 9
> >    *   0xAA0 ... 0xABF: Device 9 buffer
> > - *   0xB00 ... 0xB7F: Device 10
> > + *   0xB00 ... 0xB9F: Device 10
> >    *   0xBA0 ... 0xBBF: Device 10 buffer
> > - *   0xC00 ... 0xC7F: Device 11
> > + *   0xC00 ... 0xC9F: Device 11
> >    *   0xCA0 ... 0xCBF: Device 11 buffer
> > - *   0xD00 ... 0xD7F: Device 12
> > + *   0xD00 ... 0xD9F: Device 12
> >    *   0xDA0 ... 0xDBF: Device 12 buffer
> > - *   0xE00 ... 0xE7F: Device 13
> > + *   0xE00 ... 0xE9F: Device 13
> >    *   0xEA0 ... 0xEBF: Device 13 buffer
> > - *   0xF00 ... 0xF7F: Device 14
> > + *   0xF00 ... 0xF9F: Device 14
> >    *   0xFA0 ... 0xFBF: Device 14 buffer
> > - *   0x1000 ... 0x107F: Device 15
> > + *   0x1000 ... 0x109F: Device 15
> >    *   0x10A0 ... 0x10BF: Device 15 buffer
> >    */
> >   static void aspeed_i2c_realize(DeviceState *dev, Error **errp) @@
> > -1670,8 +1670,8 @@ static void aspeed_2700_i2c_class_init(ObjectClass
> *klass, const void *data)
> >       dc->desc = "ASPEED 2700 I2C Controller";
> >
> >       aic->num_busses = 16;
> > -    aic->reg_size = 0x80;
> > -    aic->reg_gap_size = 0x80;
> > +    aic->reg_size = 0xa0;
> > +    aic->reg_gap_size = 0x60;
> >       aic->gap = -1; /* no gap */
> >       aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq;
> >       aic->pool_size = 0x20;

RE: [PATCH v1 05/10] hw/arm/aspeed_ast27x0: Add AST2700 A2 SoC support

[Jamin Lin]

Hi Cédric,

> Subject: Re: [PATCH v1 05/10] hw/arm/aspeed_ast27x0: Add AST2700 A2 SoC
> support
> 
> On 2/6/26 06:33, Jamin Lin wrote:
> > Introduce a new AST2700 A2 SoC variant by adding a dedicated class
> > initialization function.
> >
> > This commit sets the A2 silicon revision and defines its SoC
> > capabilities, including CPU type, SRAM size, peripheral counts, and
> > CPU topology, while reusing the existing IRQ and memory maps.
> 
> 
> Could you please briefly document the differences with the A1 ?
> 
> Thanks,

I have updated the commit log as follows:

AST2700 A2 is functionally identical to AST2700 A1.
There are no changes to the IRQ layout, memory map, or peripheral
configuration. The only difference is the silicon revision.

This commit introduces a dedicated AST2700 A2 SoC type by reusing
the existing AST2700 A1 implementation and setting the A2 silicon
revision accordingly.

Thanks,
Jamin
> 
> C.
> 
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   hw/arm/aspeed_ast27x0.c | 36
> ++++++++++++++++++++++++++++++++++++
> >   1 file changed, 36 insertions(+)
> >
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> > 61790ea1cc..87dcb82e1b 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -1166,6 +1166,36 @@ static void
> aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
> >       sc->memmap       = aspeed_soc_ast2700_memmap;
> >   }
> >
> > +static void aspeed_soc_ast2700a2_class_init(ObjectClass *oc, const
> > +void *data) {
> > +    static const char * const valid_cpu_types[] = {
> > +        ARM_CPU_TYPE_NAME("cortex-a35"),
> > +        NULL
> > +    };
> > +    DeviceClass *dc = DEVICE_CLASS(oc);
> > +    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
> > +
> > +    /* Reason: The Aspeed SoC can only be instantiated from a board */
> > +    dc->user_creatable = false;
> > +    dc->realize      = aspeed_soc_ast2700_realize;
> > +
> > +    sc->valid_cpu_types = valid_cpu_types;
> > +    sc->silicon_rev  = AST2700_A2_SILICON_REV;
> > +    sc->sram_size    = 0x20000;
> > +    sc->pcie_num     = 3;
> > +    sc->spis_num     = 3;
> > +    sc->sgpio_num    = 2;
> > +    sc->ehcis_num    = 4;
> > +    sc->wdts_num     = 8;
> > +    sc->macs_num     = 3;
> > +    sc->uarts_num    = 13;
> > +    sc->num_cpus     = 4;
> > +    sc->ioexp_num    = 2;
> > +    sc->uarts_base   = ASPEED_DEV_UART0;
> > +    sc->irqmap       = aspeed_soc_ast2700a1_irqmap;
> > +    sc->memmap       = aspeed_soc_ast2700_memmap;
> > +}
> > +
> >   static const TypeInfo aspeed_soc_ast27x0_types[] = {
> >       {
> >           .name           = TYPE_ASPEED27X0_SOC,
> > @@ -1179,6 +1209,12 @@ static const TypeInfo aspeed_soc_ast27x0_types[]
> = {
> >           .instance_init  = aspeed_soc_ast2700_init,
> >           .class_init     = aspeed_soc_ast2700a1_class_init,
> >       },
> > +    {
> > +        .name           = "ast2700-a2",
> > +        .parent         = TYPE_ASPEED27X0_SOC,
> > +        .instance_init  = aspeed_soc_ast2700_init,
> > +        .class_init     = aspeed_soc_ast2700a2_class_init,
> > +    },
> >   };
> >
> >   DEFINE_TYPES(aspeed_soc_ast27x0_types)

RE: [PATCH v1 06/10] hw/arm/aspeed_ast27x0_evb: Add AST2700 A2 EVB machine

[Jamin Lin]

Hi Cédric

> Subject: Re: [PATCH v1 06/10] hw/arm/aspeed_ast27x0_evb: Add AST2700 A2
> EVB machine
> 
> On 2/6/26 06:33, Jamin Lin wrote:
> > Add a new AST2700 A2 EVB machine to model the newer A2 silicon.
> >
> > The "ast2700-evb" machine alias is moved to the AST2700 A2 EVB, making
> > it the default AST2700 evaluation board. The existing AST2700 A1 EVB
> > machine remains available as "ast2700a1-evb".
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   hw/arm/aspeed_ast27x0_evb.c | 29 ++++++++++++++++++++++++++++-
> >   1 file changed, 28 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c
> > index 31f7d61117..0ff1bebeb0 100644
> > --- a/hw/arm/aspeed_ast27x0_evb.c
> > +++ b/hw/arm/aspeed_ast27x0_evb.c
> > @@ -34,7 +34,6 @@ static void
> aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
> >       MachineClass *mc = MACHINE_CLASS(oc);
> >       AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> >
> > -    mc->alias = "ast2700-evb";
> 
> Please change the machine alias in a separate patch.
Thanks for the review and suggestion.
Will do.

Thanks,
Jamin
> 
> Thanks,
> 
> C.
> 
> 
> >       mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)";
> >       amc->soc_name  = "ast2700-a1";
> >       amc->hw_strap1 = AST2700_EVB_HW_STRAP1; @@ -50,12 +49,40
> @@
> > static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
> >       aspeed_machine_class_init_cpus_defaults(mc);
> >   }
> >
> > +static void aspeed_machine_ast2700a2_evb_class_init(ObjectClass *oc,
> > +                                                    const void
> *data)
> > +{
> > +    MachineClass *mc = MACHINE_CLASS(oc);
> > +    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> > +
> > +    mc->alias = "ast2700-evb";
> > +    mc->desc = "Aspeed AST2700 A2 EVB (Cortex-A35)";
> > +    amc->soc_name  = "ast2700-a2";
> > +    amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
> > +    amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
> > +    amc->fmc_model = "w25q01jvq";
> > +    amc->spi_model = "w25q512jv";
> > +    amc->num_cs    = 2;
> > +    amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON |
> ASPEED_MAC2_ON;
> > +    amc->uart_default = ASPEED_DEV_UART12;
> > +    amc->i2c_init  = ast2700_evb_i2c_init;
> > +    amc->vbootrom = true;
> > +    mc->default_ram_size = 2 * GiB;
> > +    aspeed_machine_class_init_cpus_defaults(mc);
> > +}
> > +
> >   static const TypeInfo aspeed_ast27x0_evb_types[] = {
> >       {
> >           .name          = MACHINE_TYPE_NAME("ast2700a1-evb"),
> >           .parent        = TYPE_ASPEED_MACHINE,
> >           .class_init    = aspeed_machine_ast2700a1_evb_class_init,
> >           .interfaces    = aarch64_machine_interfaces,
> > +    },
> > +    {
> > +        .name          = MACHINE_TYPE_NAME("ast2700a2-evb"),
> > +        .parent        = TYPE_ASPEED_MACHINE,
> > +        .class_init    = aspeed_machine_ast2700a2_evb_class_init,
> > +        .interfaces    = aarch64_machine_interfaces,
> >       }
> >   };
> >

RE: [PATCH v1 09/10] hw/arm/aspeed_ast27x0-fc: Switch AST2700 FC machine to A2 SoC

[Jamin Lin]

Hi Cédric

> Subject: Re: [PATCH v1 09/10] hw/arm/aspeed_ast27x0-fc: Switch AST2700 FC
> machine to A2 SoC
> 
> On 2/6/26 06:33, Jamin Lin wrote:
> > Update the AST2700 FC machine to use the AST2700 A2 SoC model instead
> > of the A1-specific variant.
> >
> > This change removes A1-specific naming and definitions from the FC
> > machine and aligns it with the newer AST2700 A2 silicon.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   hw/arm/aspeed_ast27x0-fc.c | 15 +++++++--------
> >   1 file changed, 7 insertions(+), 8 deletions(-)
> >
> > diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
> > index 0502a137f3..5eb6680da9 100644
> > --- a/hw/arm/aspeed_ast27x0-fc.c
> > +++ b/hw/arm/aspeed_ast27x0-fc.c
> > @@ -24,8 +24,8 @@
> >   #include "hw/arm/aspeed_coprocessor.h"
> >   #include "hw/arm/machines-qom.h"
> >
> > -#define TYPE_AST2700A1FC MACHINE_TYPE_NAME("ast2700fc")
> > -OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700A1FC);
> > +#define TYPE_AST2700FC MACHINE_TYPE_NAME("ast2700fc")
> > +OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700FC);
> >
> >   static struct arm_boot_info ast2700fc_board_info = {
> >       .board_id = -1, /* device-tree-only board */ @@ -48,8 +48,7 @@
> > struct Ast2700FCState {
> >       Aspeed27x0CoprocessorState tsp;
> >   };
> >
> > -#define AST2700FC_BMC_RAM_SIZE (1 * GiB) -#define
> > AST2700FC_CM4_DRAM_SIZE (32 * MiB)
> > +#define AST2700FC_BMC_RAM_SIZE (2 * GiB)
> 
The ast2700a2-evb machine is largely identical to ast2700a1-evb.
The only difference is the default DRAM size, which is increased
to 2 GB. So, I updated the DRAM size to 2GiB.
Should I separate the patch to update the DRAM size?

Thanks,
Jamin
> 
> This is an unrelated change.
> 
> Thanks,
> 
> C.
> 
> >   #define AST2700FC_HW_STRAP1 0x000000C0
> >   #define AST2700FC_HW_STRAP2 0x00000003 @@ -58,7 +57,7 @@ struct
> > Ast2700FCState {
> >
> >   static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
> >   {
> > -    Ast2700FCState *s = AST2700A1FC(machine);
> > +    Ast2700FCState *s = AST2700FC(machine);
> >       AspeedSoCState *soc;
> >       AspeedSoCClass *sc;
> >       const char *bios_name = NULL;
> > @@ -66,7 +65,7 @@ static bool ast2700fc_ca35_init(MachineState
> *machine, Error **errp)
> >       DeviceState *dev = NULL;
> >       uint64_t rom_size;
> >
> > -    object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1");
> > +    object_initialize_child(OBJECT(s), "ca35", &s->ca35,
> > + "ast2700-a2");
> >       soc = ASPEED_SOC(&s->ca35);
> >       sc = ASPEED_SOC_GET_CLASS(soc);
> >
> > @@ -135,7 +134,7 @@ static bool ast2700fc_ca35_init(MachineState
> > *machine, Error **errp)
> >
> >   static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
> >   {
> > -    Ast2700FCState *s = AST2700A1FC(machine);
> > +    Ast2700FCState *s = AST2700FC(machine);
> >       AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
> >
> >       s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK"); @@ -167,7
> > +166,7 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error
> > **errp)
> >
> >   static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
> >   {
> > -    Ast2700FCState *s = AST2700A1FC(machine);
> > +    Ast2700FCState *s = AST2700FC(machine);
> >       AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
> >
> >       s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");

RE: [PATCH v1 08/10] tests/functional/aarch64/test_aspeed_ast2700: Add AST2700 A2 EVB functional tests

[Jamin Lin]

Hi Thomas, Peter, Cédric

> Subject: Re: [PATCH v1 08/10] tests/functional/aarch64/test_aspeed_ast2700:
> Add AST2700 A2 EVB functional tests
> 
> On 06/02/2026 12.33, Peter Maydell wrote:
> > On Fri, 6 Feb 2026 at 10:40, Thomas Huth <thuth@redhat.com> wrote:
> >>
> >> On 06/02/2026 11.11, Cédric Le Goater wrote:
> >>> + Thomas
> >>>
> >>> On 2/6/26 06:33, Jamin Lin wrote:
> >>>> Add functional coverage for the AST2700 A2 EVB machine by
> >>>> introducing test cases that boot and validate an OpenBMC SDK v11.00
> >>>> image on "ast2700a2-evb".
> >>>
> >>> I wonder if we need to test both machines. The test is already quite long.
> >>>
> >>> On my test system :
> >>>
> >>>     qemu:func-aarch64-aspeed_ast2700             OK
> 119.68s   3
> >>> subtests passed
> >>>
> >>> With both machines :
> >>>
> >>>     qemu:func-aarch64-aspeed_ast2700             OK
> 219.79s   6
> >>> subtests passed
> >>
> >> If the machines are very similar, it's maybe better to mark one of
> >> the tests with a decorator (skipSlowTest maybe), so we don't have to
> >> execute it by default, but we still have the test around if we need it.
> >
> >
> > It might also be nice to have them be a separate top level test, so
> > that the tests can be run in parallel. AIUI having 1 test with 6
> > subtests forces all 6 to run in sequence, whereas with
> > 2 tests and 3 subtests each you can at least use 2 host CPUs.
> > Or does the qtest subtest handling include parallelism?
> 
> No, there is no parallel execution for subtests, in neither the qtest nor the
> functional testing framework. So yes, if you want to execute this in parallel, put
> it into separate files.
> 
>   Thomas

Thanks for the review and the suggestions.

I plan to rename test_aspeed_ast2700.py to test_aspeed_ast2700a1.py for AST2700 A1 testing.
Then, I will add a new test_aspeed_ast2700.py for AST2700 A2 testing.
This test will cover the latest EVB machine and SoC.

Please let me know if you have any suggestions.

Thanks-Jamin

RE: [PATCH v1 00/10] Support ASPEED AST2700 A2

[Jamin Lin]

Hi Cédric,

> Subject: Re: [PATCH v1 00/10] Support ASPEED AST2700 A2
> 
> Jamin,
> 
> On 2/6/26 06:33, Jamin Lin wrote:
> > v1
> >    1. Add AST2700 A2 SoC support
> >    2. Add AST2700 A2 EVB machine
> >    3. Alias ast2700-evb to ast2700a2-evb
> >    4. Switch AST2700 FC machine to use the A2 SoC
> >    5. Update functional tests for both AST2700 A1 and A2
> >    6. Fix I2C Fix Out-of-Bounds access issue
> >
> > Jamin Lin (10):
> >    hw/i2c/aspeed_i2c: Fix Out-of-Bounds access by using dynamic register
> >      array
> >    hw/i2c/aspeed_i2c: Increase I2C device register size to 0xA0
> >    hw/misc/aspeed_scu: Remove unused SoC silicon revision definitions
> >    hw/misc/aspeed_scu: Add AST2700 A2 silicon revisions
> >    hw/arm/aspeed_ast27x0: Add AST2700 A2 SoC support
> >    hw/arm/aspeed_ast27x0_evb: Add AST2700 A2 EVB machine
> >    tests/qtest/ast2700-hace-test: Use ast2700-evb alias for AST2700 HACE
> >      tests
> >    tests/functional/aarch64/test_aspeed_ast2700: Add AST2700 A2 EVB
> >      functional tests
> >    hw/arm/aspeed_ast27x0-fc: Switch AST2700 FC machine to A2 SoC
> >    tests/functional/aarch64/test_aspeed_ast2700fc: Use AST2700 A2 SDK
> >      image for FC tests
> >
> >   include/hw/i2c/aspeed_i2c.h                   |  4 +-
> >   include/hw/misc/aspeed_scu.h                  | 11 +---
> >   hw/arm/aspeed_ast27x0-fc.c                    | 15 +++---
> >   hw/arm/aspeed_ast27x0.c                       | 36
> +++++++++++++
> >   hw/arm/aspeed_ast27x0_evb.c                   | 29 +++++++++-
> >   hw/i2c/aspeed_i2c.c                           | 54
> +++++++++++--------
> >   hw/misc/aspeed_scu.c                          | 11 +---
> >   tests/qtest/ast2700-hace-test.c               | 22 ++++----
> >   .../functional/aarch64/test_aspeed_ast2700.py | 44 +++++++++++++++
> >   .../aarch64/test_aspeed_ast2700fc.py          | 16 +++---
> >   10 files changed, 169 insertions(+), 73 deletions(-)
> >
> 
> 
> It would nice if you could provide a summary of the changes introduced in the
> A2 revision compared to the A1. That in the cover letter and in the commit log
> of the patch adding support. We're curious !
> 
Thanks for the review and the suggestion.

I have added a summary of the differences between AST2700 A1 and AST2700 A2 to the commit log of the patch that adds A2 support.
The same information has also been added to the cover letter.

For clarity, the differences are:
V2:
 1. AST2700 A2 is functionally identical to AST2700 A1. There are no changes to the IRQ layout, memory map, or peripheral configuration; the only difference is the silicon revision.
 2. The ast2700a2-evb machine is largely identical to ast2700a1-evb. The only difference is the default DRAM size, which is increased to 2 GB.
 3. The I2C out-of-bounds fix has been separated into a new patch series.

Thanks,
Jamin

> Thanks,
> 
> C.

Re: [PATCH v1 02/10] hw/i2c/aspeed_i2c: Increase I2C device register size to 0xA0

[Cédric Le Goater]

Hello Jamin,

On 2/9/26 03:02, Jamin Lin wrote:
> Hi Cédric
> 
>> Subject: Re: [PATCH v1 02/10] hw/i2c/aspeed_i2c: Increase I2C device register
>> size to 0xA0
>>
>> On 2/6/26 06:33, Jamin Lin wrote:
>>> According to the AST2700 A1 datasheet, the register space for each I2C
>>> device instance has been expanded from 0x80 bytes to 0xA0 bytes.
>>
>> Was that change introduced with the A1 ? or A0 ?
>>
> 
> The change was introduced in A1.
> Both A1 and A2 use the same device register size of 0xA0.


We should add a fixes tag.

Thanks,

C.


> Thanks,
> Jamin
> 
>> Thanks,
>>
>> C.
>>
>>
>>> Update the AST2700 I2C controller configuration to reflect the new
>>> register layout by increasing the per-device register size to 0xA0 and
>>> adjusting the register gap size accordingly.
>>>
>>> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
>>> ---
>>>    hw/i2c/aspeed_i2c.c | 36 ++++++++++++++++++------------------
>>>    1 file changed, 18 insertions(+), 18 deletions(-)
>>>
>>> diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index
>>> cf3a003978..e1682c9bdd 100644
>>> --- a/hw/i2c/aspeed_i2c.c
>>> +++ b/hw/i2c/aspeed_i2c.c
>>> @@ -1206,37 +1206,37 @@ static void aspeed_i2c_instance_init(Object
>> *obj)
>>>     *
>>>     * Address Definitions (AST2700)
>>>     *   0x000 ... 0x0FF: Global Register
>>> - *   0x100 ... 0x17F: Device 0
>>> + *   0x100 ... 0x19F: Device 0
>>>     *   0x1A0 ... 0x1BF: Device 0 buffer
>>> - *   0x200 ... 0x27F: Device 1
>>> + *   0x200 ... 0x29F: Device 1
>>>     *   0x2A0 ... 0x2BF: Device 1 buffer
>>> - *   0x300 ... 0x37F: Device 2
>>> + *   0x300 ... 0x39F: Device 2
>>>     *   0x3A0 ... 0x3BF: Device 2 buffer
>>> - *   0x400 ... 0x47F: Device 3
>>> + *   0x400 ... 0x49F: Device 3
>>>     *   0x4A0 ... 0x4BF: Device 3 buffer
>>> - *   0x500 ... 0x57F: Device 4
>>> + *   0x500 ... 0x59F: Device 4
>>>     *   0x5A0 ... 0x5BF: Device 4 buffer
>>> - *   0x600 ... 0x67F: Device 5
>>> + *   0x600 ... 0x69F: Device 5
>>>     *   0x6A0 ... 0x6BF: Device 5 buffer
>>> - *   0x700 ... 0x77F: Device 6
>>> + *   0x700 ... 0x79F: Device 6
>>>     *   0x7A0 ... 0x7BF: Device 6 buffer
>>> - *   0x800 ... 0x87F: Device 7
>>> + *   0x800 ... 0x89F: Device 7
>>>     *   0x8A0 ... 0x8BF: Device 7 buffer
>>> - *   0x900 ... 0x97F: Device 8
>>> + *   0x900 ... 0x99F: Device 8
>>>     *   0x9A0 ... 0x9BF: Device 8 buffer
>>> - *   0xA00 ... 0xA7F: Device 9
>>> + *   0xA00 ... 0xA9F: Device 9
>>>     *   0xAA0 ... 0xABF: Device 9 buffer
>>> - *   0xB00 ... 0xB7F: Device 10
>>> + *   0xB00 ... 0xB9F: Device 10
>>>     *   0xBA0 ... 0xBBF: Device 10 buffer
>>> - *   0xC00 ... 0xC7F: Device 11
>>> + *   0xC00 ... 0xC9F: Device 11
>>>     *   0xCA0 ... 0xCBF: Device 11 buffer
>>> - *   0xD00 ... 0xD7F: Device 12
>>> + *   0xD00 ... 0xD9F: Device 12
>>>     *   0xDA0 ... 0xDBF: Device 12 buffer
>>> - *   0xE00 ... 0xE7F: Device 13
>>> + *   0xE00 ... 0xE9F: Device 13
>>>     *   0xEA0 ... 0xEBF: Device 13 buffer
>>> - *   0xF00 ... 0xF7F: Device 14
>>> + *   0xF00 ... 0xF9F: Device 14
>>>     *   0xFA0 ... 0xFBF: Device 14 buffer
>>> - *   0x1000 ... 0x107F: Device 15
>>> + *   0x1000 ... 0x109F: Device 15
>>>     *   0x10A0 ... 0x10BF: Device 15 buffer
>>>     */
>>>    static void aspeed_i2c_realize(DeviceState *dev, Error **errp) @@
>>> -1670,8 +1670,8 @@ static void aspeed_2700_i2c_class_init(ObjectClass
>> *klass, const void *data)
>>>        dc->desc = "ASPEED 2700 I2C Controller";
>>>
>>>        aic->num_busses = 16;
>>> -    aic->reg_size = 0x80;
>>> -    aic->reg_gap_size = 0x80;
>>> +    aic->reg_size = 0xa0;
>>> +    aic->reg_gap_size = 0x60;
>>>        aic->gap = -1; /* no gap */
>>>        aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq;
>>>        aic->pool_size = 0x20;
> 

RE: [PATCH v1 02/10] hw/i2c/aspeed_i2c: Increase I2C device register size to 0xA0

[Jamin Lin]

Hi Cédric

> Subject: Re: [PATCH v1 02/10] hw/i2c/aspeed_i2c: Increase I2C device register
> size to 0xA0
> 
> Hello Jamin,
> 
> On 2/9/26 03:02, Jamin Lin wrote:
> > Hi Cédric
> >
> >> Subject: Re: [PATCH v1 02/10] hw/i2c/aspeed_i2c: Increase I2C device
> >> register size to 0xA0
> >>
> >> On 2/6/26 06:33, Jamin Lin wrote:
> >>> According to the AST2700 A1 datasheet, the register space for each
> >>> I2C device instance has been expanded from 0x80 bytes to 0xA0 bytes.
> >>
> >> Was that change introduced with the A1 ? or A0 ?
> >>
> >
> > The change was introduced in A1.
> > Both A1 and A2 use the same device register size of 0xA0.
> 
> 
> We should add a fixes tag.
> 
Will add.

Thanks,
Jamin
> Thanks,
> 
> C.
> 
> 
> > Thanks,
> > Jamin
> >
> >> Thanks,
> >>
> >> C.
> >>
> >>
> >>> Update the AST2700 I2C controller configuration to reflect the new
> >>> register layout by increasing the per-device register size to 0xA0
> >>> and adjusting the register gap size accordingly.
> >>>
> >>> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> >>> ---
> >>>    hw/i2c/aspeed_i2c.c | 36 ++++++++++++++++++------------------
> >>>    1 file changed, 18 insertions(+), 18 deletions(-)
> >>>
> >>> diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index
> >>> cf3a003978..e1682c9bdd 100644
> >>> --- a/hw/i2c/aspeed_i2c.c
> >>> +++ b/hw/i2c/aspeed_i2c.c
> >>> @@ -1206,37 +1206,37 @@ static void aspeed_i2c_instance_init(Object
> >> *obj)
> >>>     *
> >>>     * Address Definitions (AST2700)
> >>>     *   0x000 ... 0x0FF: Global Register
> >>> - *   0x100 ... 0x17F: Device 0
> >>> + *   0x100 ... 0x19F: Device 0
> >>>     *   0x1A0 ... 0x1BF: Device 0 buffer
> >>> - *   0x200 ... 0x27F: Device 1
> >>> + *   0x200 ... 0x29F: Device 1
> >>>     *   0x2A0 ... 0x2BF: Device 1 buffer
> >>> - *   0x300 ... 0x37F: Device 2
> >>> + *   0x300 ... 0x39F: Device 2
> >>>     *   0x3A0 ... 0x3BF: Device 2 buffer
> >>> - *   0x400 ... 0x47F: Device 3
> >>> + *   0x400 ... 0x49F: Device 3
> >>>     *   0x4A0 ... 0x4BF: Device 3 buffer
> >>> - *   0x500 ... 0x57F: Device 4
> >>> + *   0x500 ... 0x59F: Device 4
> >>>     *   0x5A0 ... 0x5BF: Device 4 buffer
> >>> - *   0x600 ... 0x67F: Device 5
> >>> + *   0x600 ... 0x69F: Device 5
> >>>     *   0x6A0 ... 0x6BF: Device 5 buffer
> >>> - *   0x700 ... 0x77F: Device 6
> >>> + *   0x700 ... 0x79F: Device 6
> >>>     *   0x7A0 ... 0x7BF: Device 6 buffer
> >>> - *   0x800 ... 0x87F: Device 7
> >>> + *   0x800 ... 0x89F: Device 7
> >>>     *   0x8A0 ... 0x8BF: Device 7 buffer
> >>> - *   0x900 ... 0x97F: Device 8
> >>> + *   0x900 ... 0x99F: Device 8
> >>>     *   0x9A0 ... 0x9BF: Device 8 buffer
> >>> - *   0xA00 ... 0xA7F: Device 9
> >>> + *   0xA00 ... 0xA9F: Device 9
> >>>     *   0xAA0 ... 0xABF: Device 9 buffer
> >>> - *   0xB00 ... 0xB7F: Device 10
> >>> + *   0xB00 ... 0xB9F: Device 10
> >>>     *   0xBA0 ... 0xBBF: Device 10 buffer
> >>> - *   0xC00 ... 0xC7F: Device 11
> >>> + *   0xC00 ... 0xC9F: Device 11
> >>>     *   0xCA0 ... 0xCBF: Device 11 buffer
> >>> - *   0xD00 ... 0xD7F: Device 12
> >>> + *   0xD00 ... 0xD9F: Device 12
> >>>     *   0xDA0 ... 0xDBF: Device 12 buffer
> >>> - *   0xE00 ... 0xE7F: Device 13
> >>> + *   0xE00 ... 0xE9F: Device 13
> >>>     *   0xEA0 ... 0xEBF: Device 13 buffer
> >>> - *   0xF00 ... 0xF7F: Device 14
> >>> + *   0xF00 ... 0xF9F: Device 14
> >>>     *   0xFA0 ... 0xFBF: Device 14 buffer
> >>> - *   0x1000 ... 0x107F: Device 15
> >>> + *   0x1000 ... 0x109F: Device 15
> >>>     *   0x10A0 ... 0x10BF: Device 15 buffer
> >>>     */
> >>>    static void aspeed_i2c_realize(DeviceState *dev, Error **errp) @@
> >>> -1670,8 +1670,8 @@ static void
> >>> aspeed_2700_i2c_class_init(ObjectClass
> >> *klass, const void *data)
> >>>        dc->desc = "ASPEED 2700 I2C Controller";
> >>>
> >>>        aic->num_busses = 16;
> >>> -    aic->reg_size = 0x80;
> >>> -    aic->reg_gap_size = 0x80;
> >>> +    aic->reg_size = 0xa0;
> >>> +    aic->reg_gap_size = 0x60;
> >>>        aic->gap = -1; /* no gap */
> >>>        aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq;
> >>>        aic->pool_size = 0x20;
> >

Re: [PATCH v1 09/10] hw/arm/aspeed_ast27x0-fc: Switch AST2700 FC machine to A2 SoC

[Cédric Le Goater]

On 2/9/26 03:31, Jamin Lin wrote:
> Hi Cédric
> 
>> Subject: Re: [PATCH v1 09/10] hw/arm/aspeed_ast27x0-fc: Switch AST2700 FC
>> machine to A2 SoC
>>
>> On 2/6/26 06:33, Jamin Lin wrote:
>>> Update the AST2700 FC machine to use the AST2700 A2 SoC model instead
>>> of the A1-specific variant.
>>>
>>> This change removes A1-specific naming and definitions from the FC
>>> machine and aligns it with the newer AST2700 A2 silicon.
>>>
>>> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
>>> ---
>>>    hw/arm/aspeed_ast27x0-fc.c | 15 +++++++--------
>>>    1 file changed, 7 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
>>> index 0502a137f3..5eb6680da9 100644
>>> --- a/hw/arm/aspeed_ast27x0-fc.c
>>> +++ b/hw/arm/aspeed_ast27x0-fc.c
>>> @@ -24,8 +24,8 @@
>>>    #include "hw/arm/aspeed_coprocessor.h"
>>>    #include "hw/arm/machines-qom.h"
>>>
>>> -#define TYPE_AST2700A1FC MACHINE_TYPE_NAME("ast2700fc")
>>> -OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700A1FC);
>>> +#define TYPE_AST2700FC MACHINE_TYPE_NAME("ast2700fc")
>>> +OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700FC);
>>>
>>>    static struct arm_boot_info ast2700fc_board_info = {
>>>        .board_id = -1, /* device-tree-only board */ @@ -48,8 +48,7 @@
>>> struct Ast2700FCState {
>>>        Aspeed27x0CoprocessorState tsp;
>>>    };
>>>
>>> -#define AST2700FC_BMC_RAM_SIZE (1 * GiB) -#define
>>> AST2700FC_CM4_DRAM_SIZE (32 * MiB)
>>> +#define AST2700FC_BMC_RAM_SIZE (2 * GiB)
>>
> The ast2700a2-evb machine is largely identical to ast2700a1-evb.
> The only difference is the default DRAM size, which is increased
> to 2 GB. So, I updated the DRAM size to 2GiB.
> Should I separate the patch to update the DRAM size?

That would be nice.


I let you decide if a Fixes tag is needed.

Thanks,

C.


> 
> Thanks,
> Jamin
>>
>> This is an unrelated change.
>>
>> Thanks,
>>
>> C.
>>
>>>    #define AST2700FC_HW_STRAP1 0x000000C0
>>>    #define AST2700FC_HW_STRAP2 0x00000003 @@ -58,7 +57,7 @@ struct
>>> Ast2700FCState {
>>>
>>>    static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
>>>    {
>>> -    Ast2700FCState *s = AST2700A1FC(machine);
>>> +    Ast2700FCState *s = AST2700FC(machine);
>>>        AspeedSoCState *soc;
>>>        AspeedSoCClass *sc;
>>>        const char *bios_name = NULL;
>>> @@ -66,7 +65,7 @@ static bool ast2700fc_ca35_init(MachineState
>> *machine, Error **errp)
>>>        DeviceState *dev = NULL;
>>>        uint64_t rom_size;
>>>
>>> -    object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1");
>>> +    object_initialize_child(OBJECT(s), "ca35", &s->ca35,
>>> + "ast2700-a2");
>>>        soc = ASPEED_SOC(&s->ca35);
>>>        sc = ASPEED_SOC_GET_CLASS(soc);
>>>
>>> @@ -135,7 +134,7 @@ static bool ast2700fc_ca35_init(MachineState
>>> *machine, Error **errp)
>>>
>>>    static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
>>>    {
>>> -    Ast2700FCState *s = AST2700A1FC(machine);
>>> +    Ast2700FCState *s = AST2700FC(machine);
>>>        AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
>>>
>>>        s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK"); @@ -167,7
>>> +166,7 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error
>>> **errp)
>>>
>>>    static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
>>>    {
>>> -    Ast2700FCState *s = AST2700A1FC(machine);
>>> +    Ast2700FCState *s = AST2700FC(machine);
>>>        AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
>>>
>>>        s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
>