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From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Alireza Sanaee <alireza.sanaee@huawei.com>
Cc: <qemu-devel@nongnu.org>, <linuxarm@huawei.com>,
	<eblake@redhat.com>, <armbru@redhat.com>, <berrange@redhat.com>,
	<pbonzini@redhat.com>, <mst@redhat.com>, <lizhijian@fujitsu.com>,
	<anisa.su@samsung.com>, <linux-cxl@vger.kernel.org>
Subject: Re: [RFC PATCH 5/7] hw/cxl: Add performant direct mapping for extents
Date: Fri, 6 Feb 2026 12:41:11 +0000	[thread overview]
Message-ID: <20260206124111.00000723@huawei.com> (raw)
In-Reply-To: <20251127225526.700-6-alireza.sanaee@huawei.com>

On Thu, 27 Nov 2025 22:55:23 +0000
Alireza Sanaee <alireza.sanaee@huawei.com> wrote:

> Add alias direct mapping into the fixed memory window.

Say more on why, plus provide sequence of commands to do this.

> 
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>

> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index b785553225..15114a5314 100644
> --- a/hw/cxl/cxl-mailbox-utils.c
> +++ b/hw/cxl/cxl-mailbox-utils.c

> @@ -3123,6 +3141,7 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,
>              }
>  
>              mr = host_memory_backend_get_memory(hmb_dc);
> +
>              if (!mr) {
>                  qemu_log("Could not get memory region from host memory "
>                           "backend\n");
> @@ -3132,11 +3151,32 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,
>              memory_region_set_nonvolatile(mr, false);
>              memory_region_set_enabled(mr, true);
>              host_memory_backend_set_mapped(hmb_dc, true);
> +
> +            if (ct3d->direct_mr_enabled) {
> +                g_autofree char *direct_mapping_name =
> +                    g_strdup_printf("cxl-direct-mapping-%d", mr_idx);
> +                int region_offset = dpa - ct3d->dc.regions[rid].base;
> +                MemoryRegion *dr_dc_mr = &ct3d->dc.dc_direct_mr[mr_idx];
> +                memory_region_init_alias(dr_dc_mr, OBJECT(ct3d),
> +                                         direct_mapping_name, mr, region_offset,
> +                                         ct3d->dc.dc_decoder_window.size);
> +                memory_region_add_subregion(&fw->mr,
> +                                            ct3d->dc.dc_decoder_window.base -
> +                                                fw->base + offset,
> +                                            dr_dc_mr);
> +                /*
> +                 * for now assuming 4 extents and 4 direct mapping memory
> +                 * regions.
> +                 */
> +                ct3d->dc.cur_direct_region_idx =
> +                    (ct3d->dc.cur_direct_region_idx + 1) % 4;

Don't do a modulo as that'll just overwrite someone else.  Just check if
we are out of space.  Ultimately they will come and go in random orders
so you'll need a different data structure to avoid running out too early.

> +            }

> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index fe0c44e8d7..1a521df881 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -524,6 +524,7 @@ typedef struct CXLDCExtent {
>      uint16_t shared_seq;
>      uint8_t rsvd[0x6];
>      int rid;
> +    uint64_t offset;
>  
>      QTAILQ_ENTRY(CXLDCExtent) node;
>  } CXLDCExtent;
> @@ -589,6 +590,7 @@ struct CXLType3Dev {
>  
>      /* State */
>      MemoryRegion direct_mr[CXL_HDM_DECODER_COUNT];
> +    bool direct_mr_enabled;
>      AddressSpace hostvmem_as;
>      AddressSpace hostpmem_as;
>      CXLComponentState cxl_cstate;
> @@ -633,6 +635,14 @@ struct CXLType3Dev {
>          HostMemoryBackend *host_dc;
>          AddressSpace host_dc_as;
>          struct CXLFixedWindow *fw;
> +        int cur_direct_region_idx;
> +        /*
> +         * dc_decoder_window represents the CXL Decoder Window

What decoder? Needs more info on why this exists.
There is no particular reason a decoder maps to a DCD region but
that's probably the largest granularity we'll get. Could well point
to just part of a dc region.  I don't mind rejecting fast path
in those corner cases but we need to make the slow path work then.

> +         */
> +        struct decoder_window {
> +            hwaddr base;
> +            hwaddr size;
> +        } dc_decoder_window;
>          /*
>           * total_capacity is equivalent to the dynamic capability
>           * memory region size.
> @@ -647,6 +657,11 @@ struct CXLType3Dev {
>  
>          uint8_t num_regions; /* 0-8 regions */
>          CXLDCRegion regions[DCD_MAX_NUM_REGION];
> +        /*
> +         * Assume 4 now but many possible, each region is one alias an extent
> +         * to allow performance translation in KVM.

The KVM bit doesn't matter.  It is better with this in TCG as well.
I think we'll ultimately want a list for these - but this is fine for now.

> +         */
> +        MemoryRegion dc_direct_mr[4];
>      } dc;


WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via qemu development <qemu-devel@nongnu.org>
To: Alireza Sanaee <alireza.sanaee@huawei.com>
Cc: <qemu-devel@nongnu.org>, <linuxarm@huawei.com>,
	<eblake@redhat.com>, <armbru@redhat.com>, <berrange@redhat.com>,
	<pbonzini@redhat.com>, <mst@redhat.com>, <lizhijian@fujitsu.com>,
	<anisa.su@samsung.com>, <linux-cxl@vger.kernel.org>
Subject: Re: [RFC PATCH 5/7] hw/cxl: Add performant direct mapping for extents
Date: Fri, 6 Feb 2026 12:41:11 +0000	[thread overview]
Message-ID: <20260206124111.00000723@huawei.com> (raw)
In-Reply-To: <20251127225526.700-6-alireza.sanaee@huawei.com>

On Thu, 27 Nov 2025 22:55:23 +0000
Alireza Sanaee <alireza.sanaee@huawei.com> wrote:

> Add alias direct mapping into the fixed memory window.

Say more on why, plus provide sequence of commands to do this.

> 
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>

> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index b785553225..15114a5314 100644
> --- a/hw/cxl/cxl-mailbox-utils.c
> +++ b/hw/cxl/cxl-mailbox-utils.c

> @@ -3123,6 +3141,7 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,
>              }
>  
>              mr = host_memory_backend_get_memory(hmb_dc);
> +
>              if (!mr) {
>                  qemu_log("Could not get memory region from host memory "
>                           "backend\n");
> @@ -3132,11 +3151,32 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,
>              memory_region_set_nonvolatile(mr, false);
>              memory_region_set_enabled(mr, true);
>              host_memory_backend_set_mapped(hmb_dc, true);
> +
> +            if (ct3d->direct_mr_enabled) {
> +                g_autofree char *direct_mapping_name =
> +                    g_strdup_printf("cxl-direct-mapping-%d", mr_idx);
> +                int region_offset = dpa - ct3d->dc.regions[rid].base;
> +                MemoryRegion *dr_dc_mr = &ct3d->dc.dc_direct_mr[mr_idx];
> +                memory_region_init_alias(dr_dc_mr, OBJECT(ct3d),
> +                                         direct_mapping_name, mr, region_offset,
> +                                         ct3d->dc.dc_decoder_window.size);
> +                memory_region_add_subregion(&fw->mr,
> +                                            ct3d->dc.dc_decoder_window.base -
> +                                                fw->base + offset,
> +                                            dr_dc_mr);
> +                /*
> +                 * for now assuming 4 extents and 4 direct mapping memory
> +                 * regions.
> +                 */
> +                ct3d->dc.cur_direct_region_idx =
> +                    (ct3d->dc.cur_direct_region_idx + 1) % 4;

Don't do a modulo as that'll just overwrite someone else.  Just check if
we are out of space.  Ultimately they will come and go in random orders
so you'll need a different data structure to avoid running out too early.

> +            }

> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index fe0c44e8d7..1a521df881 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -524,6 +524,7 @@ typedef struct CXLDCExtent {
>      uint16_t shared_seq;
>      uint8_t rsvd[0x6];
>      int rid;
> +    uint64_t offset;
>  
>      QTAILQ_ENTRY(CXLDCExtent) node;
>  } CXLDCExtent;
> @@ -589,6 +590,7 @@ struct CXLType3Dev {
>  
>      /* State */
>      MemoryRegion direct_mr[CXL_HDM_DECODER_COUNT];
> +    bool direct_mr_enabled;
>      AddressSpace hostvmem_as;
>      AddressSpace hostpmem_as;
>      CXLComponentState cxl_cstate;
> @@ -633,6 +635,14 @@ struct CXLType3Dev {
>          HostMemoryBackend *host_dc;
>          AddressSpace host_dc_as;
>          struct CXLFixedWindow *fw;
> +        int cur_direct_region_idx;
> +        /*
> +         * dc_decoder_window represents the CXL Decoder Window

What decoder? Needs more info on why this exists.
There is no particular reason a decoder maps to a DCD region but
that's probably the largest granularity we'll get. Could well point
to just part of a dc region.  I don't mind rejecting fast path
in those corner cases but we need to make the slow path work then.

> +         */
> +        struct decoder_window {
> +            hwaddr base;
> +            hwaddr size;
> +        } dc_decoder_window;
>          /*
>           * total_capacity is equivalent to the dynamic capability
>           * memory region size.
> @@ -647,6 +657,11 @@ struct CXLType3Dev {
>  
>          uint8_t num_regions; /* 0-8 regions */
>          CXLDCRegion regions[DCD_MAX_NUM_REGION];
> +        /*
> +         * Assume 4 now but many possible, each region is one alias an extent
> +         * to allow performance translation in KVM.

The KVM bit doesn't matter.  It is better with this in TCG as well.
I think we'll ultimately want a list for these - but this is fine for now.

> +         */
> +        MemoryRegion dc_direct_mr[4];
>      } dc;



  reply	other threads:[~2026-02-06 12:41 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-27 22:55 [RFC QEMU PATCH 0/7] Application Specific Tagged Memory Support in CXL Type 3 Devices Alireza Sanaee
2025-11-27 22:55 ` Alireza Sanaee via
2025-11-27 22:55 ` [RFC PATCH 1/7] hw/mem: Add tagged memory backend object Alireza Sanaee
2025-11-27 22:55   ` Alireza Sanaee via
2026-02-06 12:16   ` Jonathan Cameron
2026-02-06 12:16     ` Jonathan Cameron via qemu development
2025-11-27 22:55 ` [RFC PATCH 2/7] hw/cxl: Allow initializing type3 device with no backing device Alireza Sanaee
2025-11-27 22:55   ` Alireza Sanaee via
2026-02-06 12:28   ` Jonathan Cameron
2026-02-06 12:28     ` Jonathan Cameron via qemu development
2025-11-27 22:55 ` [RFC PATCH 3/7] hw/cxl: Change Extent add/remove APIs for lazy memory backend Alireza Sanaee
2025-11-27 22:55   ` Alireza Sanaee via
2026-02-06 12:30   ` Jonathan Cameron
2026-02-06 12:30     ` Jonathan Cameron via qemu development
2025-11-27 22:55 ` [RFC PATCH 4/7] hw/cxl: Map lazy memory backend after host acceptance Alireza Sanaee
2025-11-27 22:55   ` Alireza Sanaee via
2026-02-06 12:33   ` Jonathan Cameron
2026-02-06 12:33     ` Jonathan Cameron via qemu development
2025-11-27 22:55 ` [RFC PATCH 5/7] hw/cxl: Add performant direct mapping for extents Alireza Sanaee
2025-11-27 22:55   ` Alireza Sanaee via
2026-02-06 12:41   ` Jonathan Cameron [this message]
2026-02-06 12:41     ` Jonathan Cameron via qemu development
2025-11-27 22:55 ` [RFC PATCH 6/7] hw/cxl: Add remove alias functionality for extent direct mapping Alireza Sanaee
2025-11-27 22:55   ` Alireza Sanaee via
2026-02-06 12:43   ` Jonathan Cameron
2026-02-06 12:43     ` Jonathan Cameron via qemu development
2025-11-27 22:55 ` [RFC PATCH 7/7] hw/cxl: Add tag-based removal functionality Alireza Sanaee
2025-11-27 22:55   ` Alireza Sanaee via
2026-02-06 12:49   ` Jonathan Cameron
2026-02-06 12:49     ` Jonathan Cameron via qemu development

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