Re: [PATCH v3 2/2] hw/cxl: Add a performant (and correct) path for the non interleaved cases

[Jonathan Cameron via qemu development <qemu-devel@nongnu.org>]

On Mon, 16 Feb 2026 14:52:18 +0000
Alireza Sanaee <alireza.sanaee@huawei.com> wrote:

> The CXL address to device decoding logic is complex because of the need
> to correctly decode fine grained interleave. The current implementation
> prevents use with KVM where executed instructions may reside in that
> memory and gives very slow performance even in TCG.
> 
> In many real cases non interleaved memory configurations are useful and
> for those we can use a more conventional memory region alias allowing
> similar performance to other memory in the system.
> 
> Whether this fast path is applicable can be established once the full
> set of HDM decoders has been committed (in whatever order the guest
> decides to commit them). As such a check is performed on each
> commit/uncommit of HDM decoder to establish if the alias should be added
> or removed.
> 
> Co-developed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> Tested-by: Gregory Price <gourry@gourry.net>
It might be worth a middle patch that both adds the bool to cxl_cfmws_find_device()
and implements actually performing the check.  The usecase for that check would
then come in reduced final patch.

Maybe not worth it though and just have all that stuff in the second patch of two.

J