From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: <dave@stgolabs.net>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <dan.j.williams@intel.com>,
<bhelgaas@google.com>, <shiju.jose@huawei.com>,
<ming.li@zohomail.com>, <Smita.KoralahalliChannabasappa@amd.com>,
<rrichter@amd.com>, <dan.carpenter@linaro.org>,
<PradeepVineshReddy.Kodamati@amd.com>, <lukas@wunner.de>,
<Benjamin.Cheatham@amd.com>,
<sathyanarayanan.kuppuswamy@linux.intel.com>,
<linux-cxl@vger.kernel.org>, <vishal.l.verma@intel.com>,
<alucerop@amd.com>, <ira.weiny@intel.com>,
<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: Re: [PATCH v16 05/10] PCI: Establish common CXL Port protocol error flowUIRE
Date: Mon, 9 Mar 2026 12:45:41 +0000 [thread overview]
Message-ID: <20260309124541.000006e8@huawei.com> (raw)
In-Reply-To: <20260302203648.2886956-6-terry.bowman@amd.com>
On Mon, 2 Mar 2026 14:36:43 -0600
Terry Bowman <terry.bowman@amd.com> wrote:
> Introduce CXL Port protocol error handling callbacks to unify detection,
> logging, and recovery across CXL Ports and Endpoints. Establish a consistent
> flow for correctable and uncorrectable CXL protocol errors. Support for RCH
> Downstream Port error handling will be added in a future patch.
>
> Provide the solution by adding cxl_port_cor_error_detected() and
> cxl_port_error_detected() to handle correctable and uncorrectable handling
> through CXL RAS helpers, coordinating uncorrectable recovery in
> cxl_do_recovery(), and panicking when the handler returns PCI_ERS_RESULT_PANIC
> to preserve fatal cachemem behavior. Gate Endpoint handling on the Endpoint
> driver being bound to avoid processing errors on disabled devices.
>
> Centralize the RAS base lookup in cxl_get_ras_base(), selecting the
> downstream-port dport->regs.ras for Root/Downstream Ports and port->regs.ras
> for Upstream Ports/Endpoints.
>
> Export pcie_clear_device_status() and pci_aer_clear_fatal_status() to enable
> cxl_core to clear PCIe/AER state in these flows.
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>
Hi Terry,
It's been long enough I've pretty much forgotten what this does, so
fresh review. Might well be commenting on things that have come up
before!
Jonathan
> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
> index 44791f6d7d50..1d4be2d78469 100644
> --- a/drivers/cxl/core/ras.c
> +++ b/drivers/cxl/core/ras.c
> +static u64 cxl_serial_number(struct device *dev)
> +{
> + struct pci_dev *pdev = to_pci_dev(dev);
> + struct cxl_port *port __free(put_cxl_port) = get_cxl_port(pdev);
> + struct device *port_dev = port ? port->uport_dev : NULL;
Maybe someone else asked for this, but to my eyes it's too complex.
Would be simpler to drop this local variable and
> + struct cxl_memdev *cxlmd;
> +
if (!port || !port->uport_dev || !is_cxl_memdev(dev))
return 0;
cxlmd = to_cxl_memdev(port->uport_dev);
..
> + if (!port_dev || !is_cxl_memdev(dev))
> + return 0;
> +
> + cxlmd = to_cxl_memdev(port_dev);
> + return cxlmd->cxlds->serial;
> +}
> +static void cxl_do_recovery(struct pci_dev *pdev)
> +{
> + struct cxl_port *port __free(put_cxl_port) = get_cxl_port(pdev);
> + struct device *dev = &pdev->dev;
> + pci_ers_result_t status;
> +
> + if (!port) {
> + pci_err(pdev, "Failed to find the CXL device\n");
> + return;
> + }
> +
> + status = cxl_handle_ras(dev, cxl_serial_number(dev), cxl_get_ras_base(dev));
Extra space after =
> + if (status == PCI_ERS_RESULT_PANIC)
> + panic("CXL cachemem error.");
> +
> + if (pcie_aer_is_native(pdev)) {
> + pcie_clear_device_status(pdev);
> + pci_aer_clear_nonfatal_status(pdev);
> + pci_aer_clear_fatal_status(pdev);
> + }
> +}
> +
> void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base)
> {
> void __iomem *addr;
> @@ -327,3 +428,71 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
> +
> +static void cxl_proto_err_work_fn(struct work_struct *work)
> +{
> + struct cxl_proto_err_work_data wd;
> +
> + /*
> + * Dequeue work forwarded from the AER driver
> + * See cxl_forward_error() for matching pci_dev_get()
> + */
> + while (cxl_proto_err_kfifo_get(&wd)) {
> + struct pci_dev *pdev __free(pci_dev_put) = wd.pdev;
I'm not particularly keen on the lack of constructor / destructor pairing this is giving
us but the alternatives are fiddly. You could make cxl_proto_err_kfifo_get() return wd
/ ERR_PTR() and use a new DEFINE_FREE() for that structure. But it would require
memory allocation or a dance.
This would become something like
struct cxl_proto_err_work_data scratch;
whilst(true) {
struct cxl_proto_err_work_data *wd __free(cxl_proto_err_work_d) =
cxl_proto_err_kfifo_get(scratch);
if (IS_ERR(wd))
return;
struct cxl_port *port __free(put_cxl_port) = get_cxl_port(wd->pdev);
...
}
Hmm. Also not exactly elegant. Unless others have a better idea, let us stick
to what you have.
> + struct cxl_port *port __free(put_cxl_port) = get_cxl_port(pdev);
> +
> + if (!port) {
> + pr_err_ratelimited("%s: Failed to find parent port device in CXL topology\n",
> + pci_name(pdev));
> + continue;
> + }
> +
> + guard(device)(&port->dev);
> + if (!port->dev.driver) {
> + pr_err_ratelimited("%s: Port device is unbound, abort error handling\n",
> + dev_name(&port->dev));
> + continue;
> + }
> +
> + cxl_handle_proto_error(pdev, wd.severity);
> + }
> +}
next prev parent reply other threads:[~2026-03-09 12:45 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-02 20:36 [PATCH v16 00/10] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-03-02 20:36 ` [PATCH v16 01/10] PCI/AER: Introduce AER-CXL Kfifo Terry Bowman
2026-03-09 12:20 ` Jonathan Cameron
2026-03-28 0:28 ` Dan Williams
2026-03-29 20:33 ` Dan Williams
2026-03-30 15:33 ` Bowman, Terry
2026-03-30 15:15 ` Bowman, Terry
2026-03-02 20:36 ` [PATCH v16 02/10] PCI/CXL: Update unregistration for AER-CXL and CPER-CXL kfifos Terry Bowman
2026-03-09 12:27 ` Jonathan Cameron
2026-03-11 15:03 ` Bowman, Terry
2026-03-09 18:30 ` Dave Jiang
2026-03-29 21:27 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 03/10] cxl: Update CXL Endpoint tracing Terry Bowman
2026-03-29 21:44 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 04/10] PCI/ERR: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2026-03-29 21:57 ` Dan Williams
2026-03-30 16:40 ` Bowman, Terry
2026-03-02 20:36 ` [PATCH v16 05/10] PCI: Establish common CXL Port protocol error flow Terry Bowman
2026-03-09 12:45 ` Jonathan Cameron [this message]
2026-03-30 0:08 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 06/10] PCI/CXL: Add RCH support to CXL handlers Terry Bowman
2026-03-09 14:00 ` Jonathan Cameron
2026-03-11 15:21 ` Bowman, Terry
2026-03-30 0:31 ` Dan Williams
2026-03-30 17:02 ` Bowman, Terry
2026-03-02 20:36 ` [PATCH v16 07/10] cxl: Update error handlers to support CXL Port devices Terry Bowman
2026-03-09 14:05 ` Jonathan Cameron
2026-03-11 15:37 ` Bowman, Terry
2026-03-12 13:05 ` Jonathan Cameron
2026-03-30 1:07 ` Dan Williams
2026-03-30 16:31 ` Bowman, Terry
2026-03-31 2:11 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 08/10] cxl: Update Endpoint AER uncorrectable handler Terry Bowman
2026-03-09 14:12 ` Jonathan Cameron
2026-03-11 15:58 ` Bowman, Terry
2026-03-30 1:22 ` Dan Williams
2026-03-31 18:52 ` Bowman, Terry
2026-03-31 19:23 ` Dan Williams
2026-03-31 19:52 ` Bowman, Terry
2026-04-02 3:39 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 09/10] cxl: Remove Endpoint AER correctable handler Terry Bowman
2026-03-09 14:13 ` Jonathan Cameron
2026-03-09 18:55 ` Dave Jiang
2026-03-30 1:24 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 10/10] cxl: Enable CXL protocol error reporting Terry Bowman
2026-03-30 1:41 ` Dan Williams
2026-03-31 13:31 ` Bowman, Terry
2026-03-31 19:16 ` Dan Williams
2026-03-31 20:50 ` Bowman, Terry
2026-03-31 21:12 ` Bowman, Terry
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