From: "Bowman, Terry" <terry.bowman@amd.com>
To: Dan Williams <dan.j.williams@intel.com>,
dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, alison.schofield@intel.com,
bhelgaas@google.com, shiju.jose@huawei.com, ming.li@zohomail.com,
Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,
dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com,
lukas@wunner.de, Benjamin.Cheatham@amd.com,
sathyanarayanan.kuppuswamy@linux.intel.com,
linux-cxl@vger.kernel.org, vishal.l.verma@intel.com,
alucerop@amd.com, ira.weiny@intel.com
Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v16 10/10] cxl: Enable CXL protocol error reporting
Date: Tue, 31 Mar 2026 16:12:34 -0500 [thread overview]
Message-ID: <60ec8dbc-e081-4cae-99fa-c3042bebc996@amd.com> (raw)
In-Reply-To: <69cc1d7ee3088_1b0cc6100c3@dwillia2-mobl4.notmuch>
On 3/31/2026 2:16 PM, Dan Williams wrote:
> Bowman, Terry wrote:
>> On 3/29/2026 8:41 PM, Dan Williams wrote:
>>> Terry Bowman wrote:
>>>> CXL protocol errors are not enabled for all CXL devices after boot. These
>>>> must be enabled inorder to process CXL protocol errors.
>>>>
>>>> Introduce cxl_unmask_proto_interrupts() to call pci_aer_unmask_internal_errors().
>>>> pci_aer_unmask_internal_errors() expects the pdev->aer_cap is initialized.
>>>> But, dev->aer_cap is not initialized for CXL Upstream Switch Ports and CXL
>>>> Downstream Switch Ports. Initialize the dev->aer_cap if necessary. Enable AER
>>>> correctable internal errors and uncorrectable internal errors for all CXL
>>>> devices.
>>>>
>>>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
>>>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>>>> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
>>>> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>>>> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
>>>>
>>>> ---
>>>> drivers/cxl/core/port.c | 2 ++
>>>> drivers/cxl/core/ras.c | 22 ++++++++++++++++++++++
>>>> drivers/cxl/cxlpci.h | 4 ++++
>>>> 3 files changed, 28 insertions(+)
>>>>
>>>> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
>>>> index 27271402915f..c33d58fb7264 100644
>>>> --- a/drivers/cxl/core/port.c
>>>> +++ b/drivers/cxl/core/port.c
>>>> @@ -1852,6 +1852,8 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
>>>>
>>>> rc = cxl_add_ep(dport, &cxlmd->dev);
>>>>
>>>> + cxl_unmask_proto_interrupts(cxlmd->cxlds->dev);
>>>> +
>>>
>>> Why here? devm_cxl_port_ras_setup() will just redo it, right?
>>
>> No, I found this change is needed otherwise injection fails.
>
> Sounds like something worth fixing rather than sprinkling an out of
> place workaround. Port resource acquisition should stay logically
> grouped. I am also missing where this masking is restored on exit?
>
> I have asked about your test scripts in the past [1]. Those scripts need
> to be integrated into cxl_test proper, or at least contributed on the
> side such that anyone can clone the tests and run them. It needs to be
> the case that incremental refactoring work can move with confidence by
> simply running the tests.
>
> [1]: http://lore.kernel.org/68815a66459e4_134cc710012@dwillia2-xfh.jf.intel.com.notmuch
Hi Dan,
I sent a tgz in response here but the Intel server blocked it. I emailed it to
you and DaveJ.
- Terry
prev parent reply other threads:[~2026-03-31 21:12 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-02 20:36 [PATCH v16 00/10] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-03-02 20:36 ` [PATCH v16 01/10] PCI/AER: Introduce AER-CXL Kfifo Terry Bowman
2026-03-09 12:20 ` Jonathan Cameron
2026-03-28 0:28 ` Dan Williams
2026-03-29 20:33 ` Dan Williams
2026-03-30 15:33 ` Bowman, Terry
2026-03-30 15:15 ` Bowman, Terry
2026-03-02 20:36 ` [PATCH v16 02/10] PCI/CXL: Update unregistration for AER-CXL and CPER-CXL kfifos Terry Bowman
2026-03-09 12:27 ` Jonathan Cameron
2026-03-11 15:03 ` Bowman, Terry
2026-03-09 18:30 ` Dave Jiang
2026-03-29 21:27 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 03/10] cxl: Update CXL Endpoint tracing Terry Bowman
2026-03-29 21:44 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 04/10] PCI/ERR: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2026-03-29 21:57 ` Dan Williams
2026-03-30 16:40 ` Bowman, Terry
2026-03-02 20:36 ` [PATCH v16 05/10] PCI: Establish common CXL Port protocol error flow Terry Bowman
2026-03-09 12:45 ` [PATCH v16 05/10] PCI: Establish common CXL Port protocol error flowUIRE Jonathan Cameron
2026-03-30 0:08 ` [PATCH v16 05/10] PCI: Establish common CXL Port protocol error flow Dan Williams
2026-03-02 20:36 ` [PATCH v16 06/10] PCI/CXL: Add RCH support to CXL handlers Terry Bowman
2026-03-09 14:00 ` Jonathan Cameron
2026-03-11 15:21 ` Bowman, Terry
2026-03-30 0:31 ` Dan Williams
2026-03-30 17:02 ` Bowman, Terry
2026-03-02 20:36 ` [PATCH v16 07/10] cxl: Update error handlers to support CXL Port devices Terry Bowman
2026-03-09 14:05 ` Jonathan Cameron
2026-03-11 15:37 ` Bowman, Terry
2026-03-12 13:05 ` Jonathan Cameron
2026-03-30 1:07 ` Dan Williams
2026-03-30 16:31 ` Bowman, Terry
2026-03-31 2:11 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 08/10] cxl: Update Endpoint AER uncorrectable handler Terry Bowman
2026-03-09 14:12 ` Jonathan Cameron
2026-03-11 15:58 ` Bowman, Terry
2026-03-30 1:22 ` Dan Williams
2026-03-31 18:52 ` Bowman, Terry
2026-03-31 19:23 ` Dan Williams
2026-03-31 19:52 ` Bowman, Terry
2026-04-02 3:39 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 09/10] cxl: Remove Endpoint AER correctable handler Terry Bowman
2026-03-09 14:13 ` Jonathan Cameron
2026-03-09 18:55 ` Dave Jiang
2026-03-30 1:24 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 10/10] cxl: Enable CXL protocol error reporting Terry Bowman
2026-03-30 1:41 ` Dan Williams
2026-03-31 13:31 ` Bowman, Terry
2026-03-31 19:16 ` Dan Williams
2026-03-31 20:50 ` Bowman, Terry
2026-03-31 21:12 ` Bowman, Terry [this message]
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