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From: Herve Codina <herve.codina@bootlin.com>
To: Conor Dooley <conor@kernel.org>
Cc: linux-gpio@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Linus Walleij <linusw@kernel.org>,
	Bartosz Golaszewski <brgl@kernel.org>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v12 3/4] soc: microchip: add mpfs gpio interrupt mux driver
Date: Wed, 11 Mar 2026 17:11:29 +0100	[thread overview]
Message-ID: <20260311171129.2c382b91@bootlin.com> (raw)
In-Reply-To: <20260311-vigorous-steadfast-04afdcc9e524@spud>

Hi Conor,

On Wed, 11 Mar 2026 15:17:40 +0000
Conor Dooley <conor@kernel.org> wrote:

> From: Conor Dooley <conor.dooley@microchip.com>
> 
> On PolarFire SoC there are more GPIO interrupts than there are interrupt
> lines available on the PLIC, and a runtime configurable mux is used to
> decide which interrupts are assigned direct connections to the PLIC &
> which are relegated to sharing a line.
> 
> Add a driver so that Linux can set the mux based on the interrupt
> mapping in the devicetree.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  MAINTAINERS                         |   2 +-
>  drivers/soc/microchip/Kconfig       |  11 ++
>  drivers/soc/microchip/Makefile      |   1 +
>  drivers/soc/microchip/mpfs-irqmux.c | 181 ++++++++++++++++++++++++++++
>  4 files changed, 194 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/soc/microchip/mpfs-irqmux.c
> 

Looks good.

Reviewed-by: Herve Codina <herve.codina@bootlin.com>

Best regards,
Hervé


WARNING: multiple messages have this Message-ID (diff)
From: Herve Codina <herve.codina@bootlin.com>
To: Conor Dooley <conor@kernel.org>
Cc: linux-gpio@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Linus Walleij <linusw@kernel.org>,
	Bartosz Golaszewski <brgl@kernel.org>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v12 3/4] soc: microchip: add mpfs gpio interrupt mux driver
Date: Wed, 11 Mar 2026 17:11:29 +0100	[thread overview]
Message-ID: <20260311171129.2c382b91@bootlin.com> (raw)
In-Reply-To: <20260311-vigorous-steadfast-04afdcc9e524@spud>

Hi Conor,

On Wed, 11 Mar 2026 15:17:40 +0000
Conor Dooley <conor@kernel.org> wrote:

> From: Conor Dooley <conor.dooley@microchip.com>
> 
> On PolarFire SoC there are more GPIO interrupts than there are interrupt
> lines available on the PLIC, and a runtime configurable mux is used to
> decide which interrupts are assigned direct connections to the PLIC &
> which are relegated to sharing a line.
> 
> Add a driver so that Linux can set the mux based on the interrupt
> mapping in the devicetree.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  MAINTAINERS                         |   2 +-
>  drivers/soc/microchip/Kconfig       |  11 ++
>  drivers/soc/microchip/Makefile      |   1 +
>  drivers/soc/microchip/mpfs-irqmux.c | 181 ++++++++++++++++++++++++++++
>  4 files changed, 194 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/soc/microchip/mpfs-irqmux.c
> 

Looks good.

Reviewed-by: Herve Codina <herve.codina@bootlin.com>

Best regards,
Hervé


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  reply	other threads:[~2026-03-11 16:11 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-11 15:17 [PATCH v12 0/4] PolarFire SoC GPIO interrupt support Conor Dooley
2026-03-11 15:17 ` Conor Dooley
2026-03-11 15:17 ` [PATCH v12 1/4] gpio: mpfs: Add " Conor Dooley
2026-03-11 15:17   ` Conor Dooley
2026-03-16  9:06   ` Bartosz Golaszewski
2026-03-16  9:06     ` Bartosz Golaszewski
2026-03-16  9:22   ` Linus Walleij
2026-03-16  9:22     ` Linus Walleij
2026-03-11 15:17 ` [PATCH v12 2/4] dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux Conor Dooley
2026-03-11 15:17   ` Conor Dooley
2026-03-11 16:41   ` Rob Herring (Arm)
2026-03-11 16:41     ` Rob Herring (Arm)
2026-03-11 17:58     ` Conor Dooley
2026-03-11 17:58       ` Conor Dooley
2026-03-11 19:44       ` Rob Herring
2026-03-11 19:44         ` Rob Herring
2026-03-11 15:17 ` [PATCH v12 3/4] soc: microchip: add mpfs gpio interrupt mux driver Conor Dooley
2026-03-11 15:17   ` Conor Dooley
2026-03-11 16:11   ` Herve Codina [this message]
2026-03-11 16:11     ` Herve Codina
2026-03-16  9:27   ` Linus Walleij
2026-03-16  9:27     ` Linus Walleij
2026-03-16 10:59     ` Conor Dooley
2026-03-16 10:59       ` Conor Dooley
2026-03-19 13:37       ` Linus Walleij
2026-03-19 13:37         ` Linus Walleij
2026-03-16  9:47   ` Bartosz Golaszewski
2026-03-16  9:47     ` Bartosz Golaszewski
2026-03-11 15:17 ` [PATCH v12 4/4] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC Conor Dooley
2026-03-11 15:17   ` Conor Dooley
2026-03-16  9:27   ` Linus Walleij
2026-03-16  9:27     ` Linus Walleij

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