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From: Greg KH <gregkh@linuxfoundation.org>
To: LiuQingtao <qtliu@mail.ustc.edu.cn>
Cc: jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, neil.armstrong@linaro.org,
	bjorn.andersson@oss.qualcomm.com, marex@nabladev.com,
	dev@kael-k.io, mani@kernel.org,
	prabhakar.mahadev-lad.rj@bp.renesas.com,
	linux-serial@vger.kernel.org, linux-riscv@lists.infradead.org,
	liu.wenhong35@zte.com.cn, liu.qingtao2@zte.com.cn,
	hu.yuye@zte.com.cn, dai.hualiang@zte.com.cn,
	deng.weixian@zte.com.cn, jia.yunxiang@zte.com.cn,
	bai.lu5@zte.com.cn, yang.susheng@zte.com.cn,
	shen.lin1@zte.com.cn, tan.hu@zte.com.cn, zuo.jiang@zte.com.cn
Subject: Re: [PATCH v1 2/2] LRW UART: serial: add driver for the LRW UART
Date: Thu, 12 Mar 2026 14:45:47 +0100	[thread overview]
Message-ID: <2026031201-dense-unrefined-7bf5@gregkh> (raw)
In-Reply-To: <20260213093334.9217-3-qtliu@mail.ustc.edu.cn>

On Fri, Feb 13, 2026 at 05:33:34PM +0800, LiuQingtao wrote:
> From: Wenhong Liu <liu.wenhong35@zte.com.cn>
> 
> This commit introduces a serial driver for the LRW UART controller
> 
> Key features implemented:
> - Support for FIFO mode (16-byte depth)
> - Baud rate configuration
> - Standard asynchronous communication formats:
>   * Data bits: 5, 6, 7, 8, 9 bits
>   * Parity: odd, even, fixed, none
>   * Stop bits: 1 or 2 bits
> - Hardware flow control (RTS/CTS)
> - Multiple interrupt reporting mechanisms
> 
> Signed-off-by: Wenhong Liu <liu.wenhong35@zte.com.cn>
> Signed-off-by: Qingtao Liu <liu.qingtao2@zte.com.cn>
> ---
>  MAINTAINERS                      |    3 +
>  drivers/tty/serial/Kconfig       |   33 +
>  drivers/tty/serial/Makefile      |    1 +
>  drivers/tty/serial/lrw_uart.c    | 2822 ++++++++++++++++++++++++++++++

This really is a totally new uart?  No relation to any existing devices
at all?  Why would that be created?

Anyway, this doesn't seem to build properly, how was it tested?

> --- a/include/uapi/linux/serial_core.h
> +++ b/include/uapi/linux/serial_core.h
> @@ -231,6 +231,9 @@
>  /* Sunplus UART */
>  #define PORT_SUNPLUS	123
>  
> +/* LRW UART */
> +#define PORT_LRW	124

Why is this id needed?

thanks,

greg k-h

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linux-riscv@lists.infradead.org
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WARNING: multiple messages have this Message-ID (diff)
From: Greg KH <gregkh@linuxfoundation.org>
To: LiuQingtao <qtliu@mail.ustc.edu.cn>
Cc: jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, neil.armstrong@linaro.org,
	bjorn.andersson@oss.qualcomm.com, marex@nabladev.com,
	dev@kael-k.io, mani@kernel.org,
	prabhakar.mahadev-lad.rj@bp.renesas.com,
	linux-serial@vger.kernel.org, linux-riscv@lists.infradead.org,
	liu.wenhong35@zte.com.cn, liu.qingtao2@zte.com.cn,
	hu.yuye@zte.com.cn, dai.hualiang@zte.com.cn,
	deng.weixian@zte.com.cn, jia.yunxiang@zte.com.cn,
	bai.lu5@zte.com.cn, yang.susheng@zte.com.cn,
	shen.lin1@zte.com.cn, tan.hu@zte.com.cn, zuo.jiang@zte.com.cn
Subject: Re: [PATCH v1 2/2] LRW UART: serial: add driver for the LRW UART
Date: Thu, 12 Mar 2026 14:45:47 +0100	[thread overview]
Message-ID: <2026031201-dense-unrefined-7bf5@gregkh> (raw)
In-Reply-To: <20260213093334.9217-3-qtliu@mail.ustc.edu.cn>

On Fri, Feb 13, 2026 at 05:33:34PM +0800, LiuQingtao wrote:
> From: Wenhong Liu <liu.wenhong35@zte.com.cn>
> 
> This commit introduces a serial driver for the LRW UART controller
> 
> Key features implemented:
> - Support for FIFO mode (16-byte depth)
> - Baud rate configuration
> - Standard asynchronous communication formats:
>   * Data bits: 5, 6, 7, 8, 9 bits
>   * Parity: odd, even, fixed, none
>   * Stop bits: 1 or 2 bits
> - Hardware flow control (RTS/CTS)
> - Multiple interrupt reporting mechanisms
> 
> Signed-off-by: Wenhong Liu <liu.wenhong35@zte.com.cn>
> Signed-off-by: Qingtao Liu <liu.qingtao2@zte.com.cn>
> ---
>  MAINTAINERS                      |    3 +
>  drivers/tty/serial/Kconfig       |   33 +
>  drivers/tty/serial/Makefile      |    1 +
>  drivers/tty/serial/lrw_uart.c    | 2822 ++++++++++++++++++++++++++++++

This really is a totally new uart?  No relation to any existing devices
at all?  Why would that be created?

Anyway, this doesn't seem to build properly, how was it tested?

> --- a/include/uapi/linux/serial_core.h
> +++ b/include/uapi/linux/serial_core.h
> @@ -231,6 +231,9 @@
>  /* Sunplus UART */
>  #define PORT_SUNPLUS	123
>  
> +/* LRW UART */
> +#define PORT_LRW	124

Why is this id needed?

thanks,

greg k-h

  parent reply	other threads:[~2026-03-12 13:46 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-13  9:33 [PATCH v1 0/2] LRW UART: Patch series for LRW UART driver LiuQingtao
2026-02-13  9:33 ` LiuQingtao
2026-02-13  9:33 ` [PATCH v1 1/2] LRW UART: dt-bindings: Add binding for LRW UART LiuQingtao
2026-02-13  9:33   ` LiuQingtao
2026-02-13 10:00   ` Krzysztof Kozlowski
2026-02-13 10:00     ` Krzysztof Kozlowski
2026-02-13 14:24   ` Krzysztof Kozlowski
2026-02-13 14:24     ` Krzysztof Kozlowski
2026-02-13  9:33 ` [PATCH v1 2/2] LRW UART: serial: add driver for the " LiuQingtao
2026-02-13  9:33   ` LiuQingtao
2026-02-13 10:02   ` Krzysztof Kozlowski
2026-02-13 10:02     ` Krzysztof Kozlowski
2026-02-13 16:27   ` kernel test robot
2026-02-13 16:27     ` kernel test robot
2026-02-13 17:50   ` kernel test robot
2026-02-13 17:50     ` kernel test robot
2026-03-12 13:45   ` Greg KH [this message]
2026-03-12 13:45     ` Greg KH
  -- strict thread matches above, loose matches on Subject: below --
2026-05-13  8:43 liu.qingtao2
2026-05-13  8:43 ` liu.qingtao2
2026-05-13 18:05 ` Krzysztof Kozlowski
2026-05-13 18:05   ` Krzysztof Kozlowski
2026-05-13  8:44 liu.qingtao2
2026-05-13  8:44 ` liu.qingtao2

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