Re: [Intel-wired-lan] [PATCH iwl-next v4 1/2] ethtool: treat RXH_GTP_TEID as intrinsically symmetric

[Jakub Kicinski <kuba@kernel.org>]

On Fri, 13 Mar 2026 11:28:29 +0000 Loktionov, Aleksandr wrote:
> > -----Original Message-----
> > From: Jakub Kicinski <kuba@kernel.org>
> > Sent: Thursday, March 12, 2026 3:42 PM
> > To: Loktionov, Aleksandr <aleksandr.loktionov@intel.com>
> > Cc: intel-wired-lan@lists.osuosl.org; netdev@vger.kernel.org; Nguyen,
> > Anthony L <anthony.l.nguyen@intel.com>
> > Subject: Re: [PATCH iwl-next v4 1/2] ethtool: treat RXH_GTP_TEID as
> > intrinsically symmetric
> > 
> > On Thu, 12 Mar 2026 10:31:00 +0100 Aleksandr Loktionov wrote:  
> > > +	/* Strip TEID before checking - it carries no src/dst asymmetry  
> > */  
> > > +	rxfh &= ~(u64)RXH_GTP_TEID;  
> > 
> > No need for the u64 cast.  
> 
> But without (u64) it will work only while it defined as implicit int
> #define 	RXH_GTP_TEID	(1 << 8)
> 
> When it will be defined as BIT(8) or unsigned int it will break.
> What you'd recommend preventing such issues in the future?

We will convert the 1 to 1ULL once we actually allocate the previous 31
bits? The type is only u64 because it may come from a UINT but the upper
bits must be zeros right now.