From: Tom Rini <trini@konsulko.com>
To: Leo Liang <ycliang@andestech.com>,
Uros Stajic <uros.stajic@htecgroup.com>,
Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,
Chao-ying Fu <cfu@mips.com>
Cc: "u-boot@lists.denx.de" <u-boot@lists.denx.de>
Subject: Re: [PATCH v5 7/8] libfdt: Allow non-64b aligned memreserve entries
Date: Tue, 17 Mar 2026 07:47:36 -0600 [thread overview]
Message-ID: <20260317134736.GV502704@bill-the-cat> (raw)
In-Reply-To: <abkZr1hBcosqgBZd@swlinux02>
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On Tue, Mar 17, 2026 at 05:06:55PM +0800, Leo Liang wrote:
> Hi Uros,
>
> On Wed, Dec 24, 2025 at 03:47:17PM +0000, Uros Stajic wrote:
> > From: Chao-ying Fu <cfu@mips.com>
> >
> > Although memreserve entries in an FDT are 64-bit aligned relative to the
> > start of the FDT, we cannot guarantee that the FDT itself is 64-bit aligned
> > in memory. This is especially common when using a FIT image, where the
> > alignment of the embedded DTB cannot be controlled.
> >
> > On systems that do not support unaligned 64-bit memory accesses, this leads
> > to faults when accessing the memreserve section before the FDT is relocated.
> > To resolve this, copy the 64-bit values into suitably aligned on-stack
> > variables before accessing them.
Yes, and so you must align the device tree first. We should have
addressed all of these problems in current master now. If we have not,
please explain what the use case you're encountering now is.
[snip]
> Hi Tom,
>
> Should we accept this patch in u-boot?
No, we cannot, thanks for checking.
--
Tom
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next prev parent reply other threads:[~2026-03-17 13:47 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-24 15:44 [PATCH v5 0/8] riscv: Add support for P8700 platform on Boston board Uros Stajic
2025-12-24 15:45 ` [PATCH v5 1/8] riscv: Add initial support for P8700 SoC Uros Stajic
2026-02-09 11:24 ` Leo Liang
2026-03-17 8:36 ` Leo Liang
2026-03-27 13:46 ` Uros Stajic
2025-12-24 15:45 ` [PATCH v5 2/8] board: boston-riscv: Add initial support for P8700 Boston board Uros Stajic
2026-02-09 11:25 ` Leo Liang
2026-03-17 8:48 ` Leo Liang
2026-03-18 11:16 ` Conor Dooley
2026-03-27 13:48 ` Uros Stajic
2025-12-24 15:46 ` [PATCH v5 3/8] gpio: Add GPIO driver for Intel EG20T Uros Stajic
2025-12-24 15:46 ` [PATCH v5 4/8] pci: xilinx: Avoid writing memory base/limit for root bridge Uros Stajic
2025-12-24 15:46 ` [PATCH v5 5/8] riscv: Add syscon driver for MIPS GIC block Uros Stajic
2025-12-24 15:47 ` [PATCH v5 6/8] net: pch_gbe: Add PHY reset and MAC address fallback for RISC-V Uros Stajic
2026-03-17 8:49 ` Leo Liang
2026-03-27 13:49 ` Uros Stajic
2025-12-24 15:47 ` [PATCH v5 7/8] libfdt: Allow non-64b aligned memreserve entries Uros Stajic
2026-03-17 9:06 ` Leo Liang
2026-03-17 13:47 ` Tom Rini [this message]
2026-03-27 13:50 ` Uros Stajic
2025-12-24 15:47 ` [PATCH v5 8/8] riscv: p8700: Add Coherence Manager (CM) and IOCU support Uros Stajic
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