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From: Leo Liang <ycliang@andestech.com>
To: Uros Stajic <uros.stajic@htecgroup.com>
Cc: "u-boot@lists.denx.de" <u-boot@lists.denx.de>,
	Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,
	Chao-ying Fu <cfu@mips.com>, <trini@konsulko.com>
Subject: Re: [PATCH v5 7/8] libfdt: Allow non-64b aligned memreserve entries
Date: Tue, 17 Mar 2026 17:06:55 +0800	[thread overview]
Message-ID: <abkZr1hBcosqgBZd@swlinux02> (raw)
In-Reply-To: <20251224154449.946780-8-uros.stajic@htecgroup.com>

Hi Uros,

On Wed, Dec 24, 2025 at 03:47:17PM +0000, Uros Stajic wrote:
> From: Chao-ying Fu <cfu@mips.com>
> 
> Although memreserve entries in an FDT are 64-bit aligned relative to the
> start of the FDT, we cannot guarantee that the FDT itself is 64-bit aligned
> in memory. This is especially common when using a FIT image, where the
> alignment of the embedded DTB cannot be controlled.
> 
> On systems that do not support unaligned 64-bit memory accesses, this leads
> to faults when accessing the memreserve section before the FDT is relocated.
> To resolve this, copy the 64-bit values into suitably aligned on-stack
> variables before accessing them.
> 
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Uros Stajic <uros.stajic@htecgroup.com>
> ---
>  scripts/dtc/libfdt/fdt_ro.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/scripts/dtc/libfdt/fdt_ro.c b/scripts/dtc/libfdt/fdt_ro.c
> index d65656aaa8b..1c18aea66ab 100644
> --- a/scripts/dtc/libfdt/fdt_ro.c
> +++ b/scripts/dtc/libfdt/fdt_ro.c
> @@ -174,6 +174,7 @@ static const struct fdt_reserve_entry *fdt_mem_rsv(const void *fdt, int n)
>  
>  int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
>  {
> +	uint64_t u64;
>  	const struct fdt_reserve_entry *re;
>  
>  	FDT_RO_PROBE(fdt);
> @@ -181,8 +182,10 @@ int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
>  	if (fdt_chk_extra() && !re)
>  		return -FDT_ERR_BADOFFSET;
>  
> -	*address = fdt64_to_cpu(re->address);
> -	*size = fdt64_to_cpu(re->size);
> +	memcpy(&u64, &re->address, sizeof(u64));
> +	*address = fdt64_to_cpu(u64);
> +	memcpy(&u64, &re->size, sizeof(u64));
> +	*size = fdt64_to_cpu(u64);

There are API for unaligned access: fdt64_ld().

>  	return 0;
>  }
>  
> @@ -190,9 +193,11 @@ int fdt_num_mem_rsv(const void *fdt)
>  {
>  	int i;
>  	const struct fdt_reserve_entry *re;
> +	uint64_t u64;
>  
>  	for (i = 0; (re = fdt_mem_rsv(fdt, i)) != NULL; i++) {
> -		if (fdt64_to_cpu(re->size) == 0)
> +		memcpy(&u64, &re->size, sizeof(u64));
> +		if (fdt64_to_cpu(u64) == 0)

Ditto.

>  			return i;
>  	}
>  	return -FDT_ERR_TRUNCATED;


But other than that, this issue seemed to be discussed before
and decided to use API that does not support unaligned access.
https://github.com/dgibson/dtc/commit/a7c40409934971ac1bd934ccc411bc6932b86564

Hi Tom,

Should we accept this patch in u-boot?

Best regards,
Leo

  reply	other threads:[~2026-03-17  9:07 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-24 15:44 [PATCH v5 0/8] riscv: Add support for P8700 platform on Boston board Uros Stajic
2025-12-24 15:45 ` [PATCH v5 1/8] riscv: Add initial support for P8700 SoC Uros Stajic
2026-02-09 11:24   ` Leo Liang
2026-03-17  8:36   ` Leo Liang
2026-03-27 13:46     ` Uros Stajic
2025-12-24 15:45 ` [PATCH v5 2/8] board: boston-riscv: Add initial support for P8700 Boston board Uros Stajic
2026-02-09 11:25   ` Leo Liang
2026-03-17  8:48   ` Leo Liang
2026-03-18 11:16   ` Conor Dooley
2026-03-27 13:48     ` Uros Stajic
2025-12-24 15:46 ` [PATCH v5 3/8] gpio: Add GPIO driver for Intel EG20T Uros Stajic
2025-12-24 15:46 ` [PATCH v5 4/8] pci: xilinx: Avoid writing memory base/limit for root bridge Uros Stajic
2025-12-24 15:46 ` [PATCH v5 5/8] riscv: Add syscon driver for MIPS GIC block Uros Stajic
2025-12-24 15:47 ` [PATCH v5 6/8] net: pch_gbe: Add PHY reset and MAC address fallback for RISC-V Uros Stajic
2026-03-17  8:49   ` Leo Liang
2026-03-27 13:49     ` Uros Stajic
2025-12-24 15:47 ` [PATCH v5 7/8] libfdt: Allow non-64b aligned memreserve entries Uros Stajic
2026-03-17  9:06   ` Leo Liang [this message]
2026-03-17 13:47     ` Tom Rini
2026-03-27 13:50       ` Uros Stajic
2025-12-24 15:47 ` [PATCH v5 8/8] riscv: p8700: Add Coherence Manager (CM) and IOCU support Uros Stajic

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