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From: Yixun Lan <dlan@kernel.org>
To: Chukun Pan <amadeus@jmu.edu.cn>
Cc: Rob Herring <robh@kernel.org>, Paul Walmsley <pjw@kernel.org>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Conor Dooley <conor+dt@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, spacemit@lists.linux.dev
Subject: Re: [PATCH 1/1] riscv: dts: spacemit: reorder phy nodes for K1
Date: Thu, 19 Mar 2026 12:01:38 +0800	[thread overview]
Message-ID: <20260319040138-GKA497893@kernel.org> (raw)
In-Reply-To: <20260318100000.3934516-1-amadeus@jmu.edu.cn>

Hi Chukun, 

On 18:00 Wed 18 Mar     , Chukun Pan wrote:
> Reorder the PHY nodes of USB and PCIe to the correct positions based on
> the register address. This improves the readability and maintainability
> of the DT. No functional change is introduced by this reordering.
> 
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>

Reviewed-by: Yixun Lan <dlan@kernel.org>

> ---
>  arch/riscv/boot/dts/spacemit/k1.dtsi | 108 +++++++++++++--------------
>  1 file changed, 54 insertions(+), 54 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index d2015201f8e5..f0bad6855c97 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -359,6 +359,60 @@ syscon_rcpu2: system-controller@c0888000 {
>  			#reset-cells = <1>;
>  		};
>  
> +		usbphy2: phy@c0a30000 {
> +			compatible = "spacemit,k1-usb2-phy";
> +			reg = <0x0 0xc0a30000 0x0 0x200>;
> +			clocks = <&syscon_apmu CLK_USB30>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		combo_phy: phy@c0b10000 {
> +			compatible = "spacemit,k1-combo-phy";
> +			reg = <0x0 0xc0b10000 0x0 0x1000>;
> +			clocks = <&vctcxo_24m>,
> +				 <&syscon_apmu CLK_PCIE0_DBI>,
> +				 <&syscon_apmu CLK_PCIE0_MASTER>,
> +				 <&syscon_apmu CLK_PCIE0_SLAVE>;
> +			clock-names = "refclk",
> +				      "dbi",
> +				      "mstr",
> +				      "slv";
> +			resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
> +				 <&syscon_apmu RESET_PCIE0_DBI>,
> +				 <&syscon_apmu RESET_PCIE0_MASTER>,
> +				 <&syscon_apmu RESET_PCIE0_SLAVE>;
> +			reset-names = "phy",
> +				      "dbi",
> +				      "mstr",
> +				      "slv";
> +			#phy-cells = <1>;
> +			spacemit,apmu = <&syscon_apmu>;
> +			status = "disabled";
> +		};
> +
> +		pcie1_phy: phy@c0c10000 {
> +			compatible = "spacemit,k1-pcie-phy";
> +			reg = <0x0 0xc0c10000 0x0 0x1000>;
> +			clocks = <&vctcxo_24m>;
> +			clock-names = "refclk";
> +			resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
> +			reset-names = "phy";
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		pcie2_phy: phy@c0d10000 {
> +			compatible = "spacemit,k1-pcie-phy";
> +			reg = <0x0 0xc0d10000 0x0 0x1000>;
> +			clocks = <&vctcxo_24m>;
> +			clock-names = "refclk";
> +			resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
> +			reset-names = "phy";
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		i2c0: i2c@d4010800 {
>  			compatible = "spacemit,k1-i2c";
>  			reg = <0x0 0xd4010800 0x0 0x38>;
> @@ -429,60 +483,6 @@ i2c5: i2c@d4013800 {
>  			status = "disabled";
>  		};
>  
> -		usbphy2: phy@c0a30000 {
> -			compatible = "spacemit,k1-usb2-phy";
> -			reg = <0x0 0xc0a30000 0x0 0x200>;
> -			clocks = <&syscon_apmu CLK_USB30>;
> -			#phy-cells = <0>;
> -			status = "disabled";
> -		};
> -
> -		combo_phy: phy@c0b10000 {
> -			compatible = "spacemit,k1-combo-phy";
> -			reg = <0x0 0xc0b10000 0x0 0x1000>;
> -			clocks = <&vctcxo_24m>,
> -				 <&syscon_apmu CLK_PCIE0_DBI>,
> -				 <&syscon_apmu CLK_PCIE0_MASTER>,
> -				 <&syscon_apmu CLK_PCIE0_SLAVE>;
> -			clock-names = "refclk",
> -				      "dbi",
> -				      "mstr",
> -				      "slv";
> -			resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
> -				 <&syscon_apmu RESET_PCIE0_DBI>,
> -				 <&syscon_apmu RESET_PCIE0_MASTER>,
> -				 <&syscon_apmu RESET_PCIE0_SLAVE>;
> -			reset-names = "phy",
> -				      "dbi",
> -				      "mstr",
> -				      "slv";
> -			#phy-cells = <1>;
> -			spacemit,apmu = <&syscon_apmu>;
> -			status = "disabled";
> -		};
> -
> -		pcie1_phy: phy@c0c10000 {
> -			compatible = "spacemit,k1-pcie-phy";
> -			reg = <0x0 0xc0c10000 0x0 0x1000>;
> -			clocks = <&vctcxo_24m>;
> -			clock-names = "refclk";
> -			resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
> -			reset-names = "phy";
> -			#phy-cells = <0>;
> -			status = "disabled";
> -		};
> -
> -		pcie2_phy: phy@c0d10000 {
> -			compatible = "spacemit,k1-pcie-phy";
> -			reg = <0x0 0xc0d10000 0x0 0x1000>;
> -			clocks = <&vctcxo_24m>;
> -			clock-names = "refclk";
> -			resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
> -			reset-names = "phy";
> -			#phy-cells = <0>;
> -			status = "disabled";
> -		};
> -
>  		syscon_apbc: system-controller@d4015000 {
>  			compatible = "spacemit,k1-syscon-apbc";
>  			reg = <0x0 0xd4015000 0x0 0x1000>;
> -- 
> 2.34.1
> 
> 

-- 
Yixun Lan (dlan)

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Yixun Lan <dlan@kernel.org>
To: Chukun Pan <amadeus@jmu.edu.cn>
Cc: Rob Herring <robh@kernel.org>, Paul Walmsley <pjw@kernel.org>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Conor Dooley <conor+dt@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, spacemit@lists.linux.dev
Subject: Re: [PATCH 1/1] riscv: dts: spacemit: reorder phy nodes for K1
Date: Thu, 19 Mar 2026 12:01:38 +0800	[thread overview]
Message-ID: <20260319040138-GKA497893@kernel.org> (raw)
In-Reply-To: <20260318100000.3934516-1-amadeus@jmu.edu.cn>

Hi Chukun, 

On 18:00 Wed 18 Mar     , Chukun Pan wrote:
> Reorder the PHY nodes of USB and PCIe to the correct positions based on
> the register address. This improves the readability and maintainability
> of the DT. No functional change is introduced by this reordering.
> 
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>

Reviewed-by: Yixun Lan <dlan@kernel.org>

> ---
>  arch/riscv/boot/dts/spacemit/k1.dtsi | 108 +++++++++++++--------------
>  1 file changed, 54 insertions(+), 54 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index d2015201f8e5..f0bad6855c97 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -359,6 +359,60 @@ syscon_rcpu2: system-controller@c0888000 {
>  			#reset-cells = <1>;
>  		};
>  
> +		usbphy2: phy@c0a30000 {
> +			compatible = "spacemit,k1-usb2-phy";
> +			reg = <0x0 0xc0a30000 0x0 0x200>;
> +			clocks = <&syscon_apmu CLK_USB30>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		combo_phy: phy@c0b10000 {
> +			compatible = "spacemit,k1-combo-phy";
> +			reg = <0x0 0xc0b10000 0x0 0x1000>;
> +			clocks = <&vctcxo_24m>,
> +				 <&syscon_apmu CLK_PCIE0_DBI>,
> +				 <&syscon_apmu CLK_PCIE0_MASTER>,
> +				 <&syscon_apmu CLK_PCIE0_SLAVE>;
> +			clock-names = "refclk",
> +				      "dbi",
> +				      "mstr",
> +				      "slv";
> +			resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
> +				 <&syscon_apmu RESET_PCIE0_DBI>,
> +				 <&syscon_apmu RESET_PCIE0_MASTER>,
> +				 <&syscon_apmu RESET_PCIE0_SLAVE>;
> +			reset-names = "phy",
> +				      "dbi",
> +				      "mstr",
> +				      "slv";
> +			#phy-cells = <1>;
> +			spacemit,apmu = <&syscon_apmu>;
> +			status = "disabled";
> +		};
> +
> +		pcie1_phy: phy@c0c10000 {
> +			compatible = "spacemit,k1-pcie-phy";
> +			reg = <0x0 0xc0c10000 0x0 0x1000>;
> +			clocks = <&vctcxo_24m>;
> +			clock-names = "refclk";
> +			resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
> +			reset-names = "phy";
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		pcie2_phy: phy@c0d10000 {
> +			compatible = "spacemit,k1-pcie-phy";
> +			reg = <0x0 0xc0d10000 0x0 0x1000>;
> +			clocks = <&vctcxo_24m>;
> +			clock-names = "refclk";
> +			resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
> +			reset-names = "phy";
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		i2c0: i2c@d4010800 {
>  			compatible = "spacemit,k1-i2c";
>  			reg = <0x0 0xd4010800 0x0 0x38>;
> @@ -429,60 +483,6 @@ i2c5: i2c@d4013800 {
>  			status = "disabled";
>  		};
>  
> -		usbphy2: phy@c0a30000 {
> -			compatible = "spacemit,k1-usb2-phy";
> -			reg = <0x0 0xc0a30000 0x0 0x200>;
> -			clocks = <&syscon_apmu CLK_USB30>;
> -			#phy-cells = <0>;
> -			status = "disabled";
> -		};
> -
> -		combo_phy: phy@c0b10000 {
> -			compatible = "spacemit,k1-combo-phy";
> -			reg = <0x0 0xc0b10000 0x0 0x1000>;
> -			clocks = <&vctcxo_24m>,
> -				 <&syscon_apmu CLK_PCIE0_DBI>,
> -				 <&syscon_apmu CLK_PCIE0_MASTER>,
> -				 <&syscon_apmu CLK_PCIE0_SLAVE>;
> -			clock-names = "refclk",
> -				      "dbi",
> -				      "mstr",
> -				      "slv";
> -			resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
> -				 <&syscon_apmu RESET_PCIE0_DBI>,
> -				 <&syscon_apmu RESET_PCIE0_MASTER>,
> -				 <&syscon_apmu RESET_PCIE0_SLAVE>;
> -			reset-names = "phy",
> -				      "dbi",
> -				      "mstr",
> -				      "slv";
> -			#phy-cells = <1>;
> -			spacemit,apmu = <&syscon_apmu>;
> -			status = "disabled";
> -		};
> -
> -		pcie1_phy: phy@c0c10000 {
> -			compatible = "spacemit,k1-pcie-phy";
> -			reg = <0x0 0xc0c10000 0x0 0x1000>;
> -			clocks = <&vctcxo_24m>;
> -			clock-names = "refclk";
> -			resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
> -			reset-names = "phy";
> -			#phy-cells = <0>;
> -			status = "disabled";
> -		};
> -
> -		pcie2_phy: phy@c0d10000 {
> -			compatible = "spacemit,k1-pcie-phy";
> -			reg = <0x0 0xc0d10000 0x0 0x1000>;
> -			clocks = <&vctcxo_24m>;
> -			clock-names = "refclk";
> -			resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
> -			reset-names = "phy";
> -			#phy-cells = <0>;
> -			status = "disabled";
> -		};
> -
>  		syscon_apbc: system-controller@d4015000 {
>  			compatible = "spacemit,k1-syscon-apbc";
>  			reg = <0x0 0xd4015000 0x0 0x1000>;
> -- 
> 2.34.1
> 
> 

-- 
Yixun Lan (dlan)

  reply	other threads:[~2026-03-19  4:01 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-18 10:00 [PATCH 1/1] riscv: dts: spacemit: reorder phy nodes for K1 Chukun Pan
2026-03-18 10:00 ` Chukun Pan
2026-03-19  4:01 ` Yixun Lan [this message]
2026-03-19  4:01   ` Yixun Lan
2026-03-24  6:39 ` Yixun Lan
2026-03-24  6:39   ` Yixun Lan

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