From: Stephen Hemminger <stephen@networkplumber.org>
To: Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com>
Cc: <dev@dpdk.org>, <Selwin.Sebastian@amd.com>, <stable@dpdk.org>
Subject: Re: [PATCH v1 1/4] net/axgbe: fix MAC TCR speed select field width
Date: Fri, 27 Mar 2026 09:21:08 -0700 [thread overview]
Message-ID: <20260327092108.6117948f@phoenix.local> (raw)
In-Reply-To: <20260327122011.1534-1-ashokkumar.natarajan@amd.com>
On Fri, 27 Mar 2026 17:50:03 +0530
Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com> wrote:
> The MAC Transmit Configuration Register (TCR) speed select (SS)
> field is defined as 2 bits wide, while the hardware specification
> defines this field as 3 bits to encode all supported MAC speeds.
>
> Update the SS field width to 3 bits to match the hardware
> specification and avoid truncation of speed select values.
>
> Fixes: 69e209be5464 ("net/axgbe: add register map and related macros")
> Cc: stable@dpdk.org
>
> Signed-off-by: Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com>
> ---
Applied to next-net
prev parent reply other threads:[~2026-03-27 16:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-27 12:20 [PATCH v1 1/4] net/axgbe: fix MAC TCR speed select field width Ashok Kumar Natarajan
2026-03-27 12:20 ` [PATCH v1 2/4] net/axgbe: add 100 Mbps MAC speed select Ashok Kumar Natarajan
2026-03-27 12:20 ` [PATCH v1 3/4] net/axgbe: fix auto-neg advert/supported defs Ashok Kumar Natarajan
2026-03-27 12:20 ` [PATCH v1 4/4] net/axgbe: fix SGMII autoneg status bits Ashok Kumar Natarajan
2026-03-27 16:21 ` Stephen Hemminger [this message]
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