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From: Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com>
To: <dev@dpdk.org>
Cc: <Selwin.Sebastian@amd.com>,
	Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com>,
	<stable@dpdk.org>
Subject: [PATCH v1 1/4] net/axgbe: fix MAC TCR speed select field width
Date: Fri, 27 Mar 2026 17:50:03 +0530	[thread overview]
Message-ID: <20260327122011.1534-1-ashokkumar.natarajan@amd.com> (raw)

The MAC Transmit Configuration Register (TCR) speed select (SS)
field is defined as 2 bits wide, while the hardware specification
defines this field as 3 bits to encode all supported MAC speeds.

Update the SS field width to 3 bits to match the hardware
specification and avoid truncation of speed select values.

Fixes: 69e209be5464 ("net/axgbe: add register map and related macros")
Cc: stable@dpdk.org

Signed-off-by: Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com>
---
 drivers/net/axgbe/axgbe_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 0bceff5774..842077d972 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -492,7 +492,7 @@
 #define MAC_SSIR_SSINC_INDEX		16
 #define MAC_SSIR_SSINC_WIDTH		8
 #define MAC_TCR_SS_INDEX		29
-#define MAC_TCR_SS_WIDTH		2
+#define MAC_TCR_SS_WIDTH		3
 #define MAC_TCR_TE_INDEX		0
 #define MAC_TCR_TE_WIDTH		1
 #define MAC_TSCR_AV8021ASMEN_INDEX	28
-- 
2.34.1


             reply	other threads:[~2026-03-27 12:21 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-27 12:20 Ashok Kumar Natarajan [this message]
2026-03-27 12:20 ` [PATCH v1 2/4] net/axgbe: add 100 Mbps MAC speed select Ashok Kumar Natarajan
2026-03-27 12:20 ` [PATCH v1 3/4] net/axgbe: fix auto-neg advert/supported defs Ashok Kumar Natarajan
2026-03-27 12:20 ` [PATCH v1 4/4] net/axgbe: fix SGMII autoneg status bits Ashok Kumar Natarajan
2026-03-27 16:21 ` [PATCH v1 1/4] net/axgbe: fix MAC TCR speed select field width Stephen Hemminger

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